1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the Hexagon register file.
12 //===----------------------------------------------------------------------===//
14 let Namespace = "Hexagon" in {
16 class HexagonReg<bits<5> num, string n, list<string> alt = [],
17 list<Register> alias = []> : Register<n, alt> {
19 let HWEncoding{4-0} = num;
22 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
23 list<string> alt = []> :
24 RegisterWithSubRegs<n, subregs> {
26 let HWEncoding{4-0} = num;
29 // Registers are identified with 5-bit ID numbers.
30 // Ri - 32-bit integer registers.
31 class Ri<bits<5> num, string n, list<string> alt = []> :
32 HexagonReg<num, n, alt>;
34 // Rf - 32-bit floating-point registers.
35 class Rf<bits<5> num, string n> : HexagonReg<num, n>;
37 // Rd - 64-bit registers.
38 class Rd<bits<5> num, string n, list<Register> subregs,
39 list<string> alt = []> :
40 HexagonDoubleReg<num, n, subregs, alt> {
41 let SubRegs = subregs;
44 // Rp - predicate registers
45 class Rp<bits<5> num, string n> : HexagonReg<num, n>;
48 // Rq - vector predicate registers
49 class Rq<bits<3> num, string n> : Register<n, []> {
50 let HWEncoding{2-0} = num;
53 // Rc - control registers
54 class Rc<bits<5> num, string n,
55 list<string> alt = [], list<Register> alias = []> :
56 HexagonReg<num, n, alt, alias>;
58 // Rcc - 64-bit control registers.
59 class Rcc<bits<5> num, string n, list<Register> subregs,
60 list<string> alt = []> :
61 HexagonDoubleReg<num, n, subregs, alt> {
62 let SubRegs = subregs;
65 // Mx - address modifier registers
66 class Mx<bits<1> num, string n> : Register<n, []> {
67 let HWEncoding{0} = num;
70 def isub_lo : SubRegIndex<32>;
71 def isub_hi : SubRegIndex<32, 32>;
72 def vsub_lo : SubRegIndex<512>;
73 def vsub_hi : SubRegIndex<512, 512>;
74 def subreg_overflow : SubRegIndex<1, 0>;
78 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
81 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
82 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
83 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
85 // Aliases of the R* registers used to hold 64-bit int values (doubles).
86 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
87 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
88 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
89 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
90 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
91 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
92 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
93 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
94 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
95 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
96 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
97 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
98 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
99 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
100 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
101 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
102 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
105 // Predicate registers.
106 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
107 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
108 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
109 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
111 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
112 // tions modify this bit, and multiple such instructions are allowed in the
113 // same packet. We need to ignore output dependencies on this bit, but not
114 // on the entire USR.
115 def USR_OVF : Rc<?, "usr.ovf">;
117 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> {
118 let SubRegIndices = [subreg_overflow];
119 let SubRegs = [USR_OVF];
122 // Control registers.
123 def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>;
124 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>;
125 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
126 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
127 def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>,
129 // When defining more Cn registers, make sure to explicitly mark them
130 // as reserved in HexagonRegisterInfo.cpp.
131 def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>;
132 def M0: Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>;
133 def M1: Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>;
134 // Define C8 separately and make it aliased with USR.
135 // The problem is that USR has subregisters (e.g. overflow). If USR was
136 // specified as a subregister of C9_8, it would imply that subreg_overflow
137 // and isub_lo can be composed, which leads to all kinds of issues
139 def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>;
140 def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>;
141 def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>;
142 def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>;
143 def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>;
144 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>;
145 def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>;
146 def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
147 def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>;
148 def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>;
149 def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>;
150 def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>;
151 def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>;
152 def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>;
154 // Control registers pairs.
155 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
156 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
157 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
158 def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>;
159 def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>;
160 // Use C8 instead of USR as a subregister of C9_8.
161 def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>;
162 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>;
163 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>;
164 def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>,
166 def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>;
167 def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>,
169 def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>,
173 foreach i = 0-31 in {
174 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>;
176 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
178 // Aliases of the V* registers used to hold double vec values.
179 let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in {
180 def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>;
181 def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>;
182 def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>;
183 def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>;
184 def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>;
185 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>;
186 def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>;
187 def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>;
188 def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>;
189 def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>;
190 def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>;
191 def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>;
192 def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>;
193 def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>;
194 def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>;
195 def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>;
198 // Vector Predicate registers.
199 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
200 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
201 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
202 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
208 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
209 [v512i1, v512i1, v1024i1, v1024i1, v512i1]>;
211 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
212 [v64i8, v64i8, v128i8, v128i8, v64i8]>;
214 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
215 [v32i16, v32i16, v64i16, v64i16, v32i16]>;
217 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
218 [v16i32, v16i32, v32i32, v32i32, v16i32]>;
220 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
221 [v128i8, v128i8, v256i8, v256i8, v128i8]>;
223 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
224 [v64i16, v64i16, v128i16, v128i16, v64i16]>;
226 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
227 [v32i32, v32i32, v64i32, v64i32, v32i32]>;
229 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
230 [v64i1, v64i1, v128i1, v128i1, v64i1]>;
232 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
233 [v32i1, v32i1, v64i1, v64i1, v32i1]>;
235 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
236 [v16i1, v16i1, v32i1, v32i1, v16i1]>;
238 // HVX register classes
242 // FIXME: the register order should be defined in terms of the preferred
243 // allocation order...
245 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v32i1, v4i8, v2i16], 32,
246 (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28),
247 R10, R11, R29, R30, R31)>;
249 // Registers are listed in reverse order for allocation preference reasons.
250 def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32,
251 (add R23, R22, R21, R20, R19, R18, R17, R16,
252 R7, R6, R5, R4, R3, R2, R1, R0)>;
254 def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
255 (add R7, R6, R5, R4, R3, R2, R1, R0)> ;
257 def DoubleRegs : RegisterClass<"Hexagon",
258 [i64, f64, v64i1, v8i8, v4i16, v2i32], 64,
259 (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>;
261 def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64,
262 (add D11, D10, D9, D8, D3, D2, D1, D0)>;
264 def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512,
265 (add (sequence "V%u", 0, 31), VTMP)> {
266 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
267 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
270 def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024,
271 (add (sequence "W%u", 0, 15))> {
272 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
273 [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>;
276 def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 512,
277 (add Q0, Q1, Q2, Q3)> {
278 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
279 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
283 def PredRegs : RegisterClass<"Hexagon",
284 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
287 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
289 let Size = 32, isAllocatable = 0 in
290 def CtrRegs : RegisterClass<"Hexagon", [i32], 32,
291 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
292 UPCYCLELO, UPCYCLEHI,
293 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI,
296 let isAllocatable = 0 in
297 def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>;
299 let Size = 64, isAllocatable = 0 in
300 def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
301 (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16,
304 // These registers are new for v62 and onward.
305 // The function RegisterMatchesArch() uses this list for validation.
306 let isAllocatable = 0 in
307 def V62Regs : RegisterClass<"Hexagon", [i32], 32,
308 (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT,
309 UTIMERLO, UTIMERHI, UTIMER)>;
311 // These registers are new for v65 and onward.
312 let Size = 32, isAllocatable = 0 in
313 def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>;
318 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
319 R24, R25, R26, R27)>;