1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
11 // This file describes that machine information.
14 // |===========|==================================================|
15 // | PIPELINE | Instruction Classes |
16 // |===========|==================================================|
17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
18 // |-----------|--------------------------------------------------|
19 // | SLOT1 | LD ST ALU32 |
20 // |-----------|--------------------------------------------------|
21 // | SLOT2 | XTYPE ALU32 J JR |
22 // |-----------|--------------------------------------------------|
23 // | SLOT3 | XTYPE ALU32 J CR |
24 // |===========|==================================================|
31 // Endloop is a pseudo instruction that is encoded with 2 bits in a packet
32 // rather than taking an execution slot. This special unit is needed
33 // to schedule an ENDLOOP with 4 other instructions.
34 def SLOT_ENDLOOP: FuncUnit;
37 def PSEUDO : InstrItinClass;
38 def PSEUDOM : InstrItinClass;
39 // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
40 def DUPLEX : InstrItinClass;
41 def PREFIX : InstrItinClass;
42 def COMPOUND_CJ_ARCHDEPSLOT : InstrItinClass;
43 def COMPOUND : InstrItinClass;
45 def ALU32_2op_tc_1_SLOT0123 : InstrItinClass;
46 def ALU32_2op_tc_2early_SLOT0123 : InstrItinClass;
47 def ALU32_3op_tc_2early_SLOT0123 : InstrItinClass;
48 def ALU32_3op_tc_1_SLOT0123 : InstrItinClass;
49 def ALU32_3op_tc_2_SLOT0123 : InstrItinClass;
50 def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass;
51 def ALU64_tc_1_SLOT23 : InstrItinClass;
52 def ALU64_tc_2_SLOT23 : InstrItinClass;
53 def ALU64_tc_2early_SLOT23 : InstrItinClass;
54 def ALU64_tc_3x_SLOT23 : InstrItinClass;
55 def CR_tc_2_SLOT3 : InstrItinClass;
56 def CR_tc_2early_SLOT23 : InstrItinClass;
57 def CR_tc_2early_SLOT3 : InstrItinClass;
58 def CR_tc_3x_SLOT23 : InstrItinClass;
59 def CR_tc_3x_SLOT3 : InstrItinClass;
60 def J_tc_2early_SLOT23 : InstrItinClass;
61 def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass;
62 def J_tc_2early_SLOT2 : InstrItinClass;
63 def LD_tc_ld_SLOT01 : InstrItinClass;
64 def LD_tc_ld_SLOT0 : InstrItinClass;
65 def LD_tc_3or4stall_SLOT0 : InstrItinClass;
66 def M_tc_2_SLOT23 : InstrItinClass;
67 def M_tc_3_SLOT23 : InstrItinClass;
68 def M_tc_1_SLOT23 : InstrItinClass;
69 def M_tc_3x_SLOT23 : InstrItinClass;
70 def M_tc_3or4x_SLOT23 : InstrItinClass;
71 def ST_tc_st_SLOT01 : InstrItinClass;
72 def ST_tc_st_SLOT0 : InstrItinClass;
73 def ST_tc_ld_SLOT0 : InstrItinClass;
74 def ST_tc_3stall_SLOT0 : InstrItinClass;
75 def S_2op_tc_1_SLOT23 : InstrItinClass;
76 def S_2op_tc_2_SLOT23 : InstrItinClass;
77 def S_2op_tc_2early_SLOT23 : InstrItinClass;
78 def S_2op_tc_3or4x_SLOT23 : InstrItinClass;
79 def S_3op_tc_1_SLOT23 : InstrItinClass;
80 def S_3op_tc_2_SLOT23 : InstrItinClass;
81 def S_3op_tc_2early_SLOT23 : InstrItinClass;
82 def S_3op_tc_3_SLOT23 : InstrItinClass;
83 def S_3op_tc_3x_SLOT23 : InstrItinClass;
84 def NCJ_tc_3or4stall_SLOT0 : InstrItinClass;
85 def V2LDST_tc_ld_SLOT01 : InstrItinClass;
86 def V2LDST_tc_st_SLOT0 : InstrItinClass;
87 def V2LDST_tc_st_SLOT01 : InstrItinClass;
88 def V4LDST_tc_ld_SLOT01 : InstrItinClass;
89 def V4LDST_tc_st_SLOT0 : InstrItinClass;
90 def V4LDST_tc_st_SLOT01 : InstrItinClass;
91 def J_tc_2early_SLOT0123 : InstrItinClass;
92 def EXTENDER_tc_1_SLOT0123 : InstrItinClass;
93 def S_3op_tc_3stall_SLOT23 : InstrItinClass;
95 def HexagonItinerariesV4 :
96 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
98 InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
99 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
100 InstrItinData<ALU32_2op_tc_2early_SLOT0123,
101 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
102 InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
104 InstrItinData<ALU32_3op_tc_2early_SLOT0123,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
106 InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
108 InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
112 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
113 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
114 InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
115 InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
118 InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>]>,
119 InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>]>,
120 InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>]>,
122 // Jump (conditional/unconditional/return etc)
124 InstrItinData<CR_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
125 InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
127 InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
128 InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
130 InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>]>,
133 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
134 InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
135 InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
138 InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
139 InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
140 InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
141 InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
142 InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
146 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
148 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
149 InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
152 InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
153 InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
154 InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
155 InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
156 InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
157 InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
158 InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
159 InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
160 InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
161 InstrItinData<S_3op_tc_3stall_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
164 InstrItinData<ST_tc_3stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
166 // New Value Compare Jump
167 InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
170 InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
171 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
172 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
173 InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
174 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
175 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
177 InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
180 InstrItinData<J_tc_2early_SLOT0123 , [InstrStage<1, [SLOT_ENDLOOP]>]>,
183 InstrItinData<EXTENDER_tc_1_SLOT0123,
184 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
186 InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
187 InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
188 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
189 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
190 InstrStage<1, [SLOT2, SLOT3]>]>
193 def HexagonModelV4 : SchedMachineModel {
194 // Max issue per cycle == bundle width.
196 let Itineraries = HexagonItinerariesV4;
198 let CompleteModel = 0;
201 //===----------------------------------------------------------------------===//
202 // Hexagon V4 Resource Definitions -
203 //===----------------------------------------------------------------------===//