1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
11 // This file describes that machine information.
14 // |===========|==================================================|
15 // | PIPELINE | Instruction Classes |
16 // |===========|==================================================|
17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
18 // |-----------|--------------------------------------------------|
19 // | SLOT1 | LD ST ALU32 |
20 // |-----------|--------------------------------------------------|
21 // | SLOT2 | XTYPE ALU32 J JR |
22 // |-----------|--------------------------------------------------|
23 // | SLOT3 | XTYPE ALU32 J CR |
24 // |===========|==================================================|
26 def CJ_tc_1_SLOT23 : InstrItinClass;
27 def CJ_tc_2early_SLOT23 : InstrItinClass;
28 def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
29 def COPROC_VX_vtc_long_SLOT23 : InstrItinClass;
30 def COPROC_VX_vtc_SLOT23 : InstrItinClass;
31 def J_tc_3stall_SLOT2 : InstrItinClass;
32 def MAPPING_tc_1_SLOT0123 : InstrItinClass;
33 def M_tc_3stall_SLOT23 : InstrItinClass;
35 def HexagonItinerariesV55 :
36 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
38 InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
39 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
40 InstrItinData<ALU32_2op_tc_2early_SLOT0123,
41 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
42 InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
43 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
44 InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
45 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
46 InstrItinData<ALU32_3op_tc_2early_SLOT0123,
47 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
48 InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
49 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
52 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
54 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
56 InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
58 InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
62 InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
63 InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
64 InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>,
66 // Jump (conditional/unconditional/return etc)
67 InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
69 InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
71 InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
73 InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
75 InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
77 InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT,
78 [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1, 1]>,
81 InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>,
82 InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>,
85 InstrItinData<EXTENDER_tc_1_SLOT0123,
86 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
89 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
91 InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>,
92 InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>,
95 InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
97 InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
99 InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
101 InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
103 InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
105 InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
109 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
111 InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
112 InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
113 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
116 InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
118 InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
120 InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
122 InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
124 InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
126 InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
128 InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
130 InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
132 InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
134 InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
137 // New Value Compare Jump
138 InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>],
142 InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
144 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
146 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
148 InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
150 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
152 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
156 InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>],
160 InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
161 [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 1]>,
162 InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
163 [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
164 InstrItinData<COPROC_VX_vtc_SLOT23 ,
165 [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
166 InstrItinData<MAPPING_tc_1_SLOT0123 ,
167 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
171 InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>],
173 InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>],
175 InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
176 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
178 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
180 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
181 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>
184 def HexagonModelV55 : SchedMachineModel {
185 // Max issue per cycle == bundle width.
187 let Itineraries = HexagonItinerariesV55;
189 let CompleteModel = 0;
192 //===----------------------------------------------------------------------===//
193 // Hexagon V4 Resource Definitions -
194 //===----------------------------------------------------------------------===//