contrib/llvm/lib/Target/Hexagon/HexagonScheduleV55.td

   1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
  11 // This file describes that machine information.
  12
  13 //
  14 //    |===========|==================================================|
  15 //    | PIPELINE  |              Instruction Classes                 |
  16 //    |===========|==================================================|
  17 //    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
  18 //    |-----------|--------------------------------------------------|
  19 //    | SLOT1     |  LD       ST    ALU32                            |
  20 //    |-----------|--------------------------------------------------|
  21 //    | SLOT2     |  XTYPE          ALU32     J         JR           |
  22 //    |-----------|--------------------------------------------------|
  23 //    | SLOT3     |  XTYPE          ALU32     J         CR           |
  24 //    |===========|==================================================|
  25
  26 def CJ_tc_1_SLOT23              : InstrItinClass;
  27 def CJ_tc_2early_SLOT23         : InstrItinClass;
  28 def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
  29 def COPROC_VX_vtc_long_SLOT23   : InstrItinClass;
  30 def COPROC_VX_vtc_SLOT23        : InstrItinClass;
  31 def J_tc_3stall_SLOT2           : InstrItinClass;
  32 def MAPPING_tc_1_SLOT0123       : InstrItinClass;
  33 def M_tc_3stall_SLOT23          : InstrItinClass;
  34
  35 def HexagonItinerariesV55 :
  36       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
  37         // ALU32
  38         InstrItinData<ALU32_2op_tc_1_SLOT0123     ,
  39                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
  40         InstrItinData<ALU32_2op_tc_2early_SLOT0123,
  41                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
  42         InstrItinData<ALU32_3op_tc_1_SLOT0123     ,
  43                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
  44         InstrItinData<ALU32_3op_tc_2_SLOT0123     ,
  45                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
  46         InstrItinData<ALU32_3op_tc_2early_SLOT0123,
  47                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
  48         InstrItinData<ALU32_ADDI_tc_1_SLOT0123    ,
  49                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
  50
  51         // ALU64
  52         InstrItinData<ALU64_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
  53                                               [1, 1, 1]>,
  54         InstrItinData<ALU64_tc_2_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
  55                                               [2, 1, 1]>,
  56         InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
  57                                               [2, 1, 1]>,
  58         InstrItinData<ALU64_tc_3x_SLOT23    , [InstrStage<1, [SLOT2, SLOT3]>],
  59                                               [3, 1, 1]>,
  60
  61         // CR -> System
  62         InstrItinData<CR_tc_2_SLOT3      , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
  63         InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
  64         InstrItinData<CR_tc_3x_SLOT3     , [InstrStage<1, [SLOT3]>], [3, 1, 1]>,
  65
  66         // Jump (conditional/unconditional/return etc)
  67         InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
  68                                            [2, 1, 1, 1]>,
  69         InstrItinData<CR_tc_3x_SLOT23    , [InstrStage<1, [SLOT2, SLOT3]>],
  70                                            [3, 1, 1, 1]>,
  71         InstrItinData<CJ_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
  72                                            [1, 1, 1, 1]>,
  73         InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
  74                                            [2, 1, 1, 1]>,
  75         InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
  76                                            [2, 1, 1, 1]>,
  77         InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT,
  78                                  [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1, 1]>,
  79
  80         // JR
  81         InstrItinData<J_tc_2early_SLOT2  , [InstrStage<1, [SLOT2]>], [2, 1, 1]>,
  82         InstrItinData<J_tc_3stall_SLOT2  , [InstrStage<1, [SLOT2]>], [3, 1, 1]>,
  83
  84         // Extender
  85         InstrItinData<EXTENDER_tc_1_SLOT0123,
  86                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
  87
  88         // Load
  89         InstrItinData<LD_tc_ld_SLOT01      , [InstrStage<1, [SLOT0, SLOT1]>],
  90                                              [2, 1]>,
  91         InstrItinData<LD_tc_ld_pi_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>],
  92                                              [2, 1]>,
  93         InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>,
  94         InstrItinData<LD_tc_ld_SLOT0       , [InstrStage<1, [SLOT0]>], [2, 1]>,
  95
  96         // M
  97         InstrItinData<M_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
  98                                           [1, 1, 1]>,
  99         InstrItinData<M_tc_2_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 100                                           [2, 1, 1]>,
 101         InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
 102                                           [2, 1, 1]>,
 103         InstrItinData<M_tc_3_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 104                                           [1, 1, 1]>,
 105         InstrItinData<M_tc_3x_SLOT23    , [InstrStage<1, [SLOT2, SLOT3]>],
 106                                           [3, 1, 1]>,
 107         InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
 108                                           [3, 1, 1, 1]>,
 109         InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
 110                                           [3, 1, 1]>,
 111         InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
 112                                           [3, 1, 1]>,
 113         InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
 114                                           [3, 1, 1]>,
 115
 116         // Store
 117         InstrItinData<ST_tc_st_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>],
 118                                           [1, 1, 1]>,
 119         InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
 120                                           [1, 1, 1]>,
 121         InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
 122         InstrItinData<ST_tc_ld_SLOT0    , [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
 123         InstrItinData<ST_tc_st_SLOT0    , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
 124         InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
 125
 126         // S
 127         InstrItinData<S_2op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 128                                               [1, 1, 1]>,
 129         InstrItinData<S_2op_tc_2_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 130                                               [2, 1, 1]>,
 131         InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
 132                                               [2, 1, 1]>,
 133         InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
 134                                               [3, 1, 1]>,
 135         InstrItinData<S_3op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 136                                               [1, 1, 1]>,
 137         InstrItinData<S_3op_tc_2_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 138                                               [2, 1, 1]>,
 139         InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
 140                                               [2, 1, 1]>,
 141         InstrItinData<S_3op_tc_3_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>],
 142                                               [3, 1, 1]>,
 143         InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
 144                                               [3, 1, 1]>,
 145         InstrItinData<S_3op_tc_3x_SLOT23    , [InstrStage<1, [SLOT2, SLOT3]>],
 146                                               [3, 1, 1]>,
 147
 148         // New Value Compare Jump
 149         InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>],
 150                                               [3, 1, 1, 1]>,
 151
 152         // Mem ops
 153         InstrItinData<V2LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>],
 154                                             [1, 1, 1, 1]>,
 155         InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
 156                                             [2, 1, 1, 1]>,
 157         InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
 158                                             [1, 1, 1, 1]>,
 159         InstrItinData<V4LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>],
 160                                             [1, 1, 1, 1]>,
 161         InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
 162                                             [3, 1, 1, 1]>,
 163         InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
 164                                             [1, 1, 1, 1]>,
 165
 166         // Endloop
 167         InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>],
 168                                             [2]>,
 169
 170         // Vector
 171         InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
 172                       [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 1]>,
 173         InstrItinData<COPROC_VX_vtc_long_SLOT23  ,
 174                       [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
 175         InstrItinData<COPROC_VX_vtc_SLOT23 ,
 176                       [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
 177         InstrItinData<MAPPING_tc_1_SLOT0123      ,
 178                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
 179                       [1, 1, 1, 1]>,
 180
 181         // Misc
 182         InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>],
 183                                                 [1, 1, 1]>,
 184         InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>],
 185                                  [1, 1, 1]>,
 186         InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
 187         InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
 188                                [1, 1, 1]>,
 189         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
 190                                [1, 1, 1]>,
 191         InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
 192                                 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>
 193       ]>;
 194
 195 def HexagonModelV55 : SchedMachineModel {
 196   // Max issue per cycle == bundle width.
 197   let IssueWidth = 4;
 198   let Itineraries = HexagonItinerariesV55;
 199   let LoadLatency = 1;
 200   let CompleteModel = 0;
 201 }
 202
 203 //===----------------------------------------------------------------------===//
 204 // Hexagon V4 Resource Definitions -
 205 //===----------------------------------------------------------------------===//