contrib/llvm/lib/Target/Hexagon/HexagonScheduleV62.td

   1 //=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // V62 follows the same schedule as V60 with following exceptions:
  11 // Following instructions are permissible on any slot on V62:
  12 // V4_J4_cmpeq_fp0_jump_nt
  13 // V4_J4_cmpeq_fp0_jump_t
  14 // V4_J4_cmpeq_fp1_jump_nt
  15 // V4_J4_cmpeq_fp1_jump_t
  16 // V4_J4_cmpeq_tp0_jump_nt
  17 // V4_J4_cmpeq_tp0_jump_t
  18 // V4_J4_cmpeq_tp1_jump_nt
  19 // V4_J4_cmpeq_tp1_jump_t
  20 // V4_J4_cmpeqi_fp0_jump_nt
  21 // V4_J4_cmpeqi_fp0_jump_t
  22 // V4_J4_cmpeqi_fp1_jump_nt
  23 // V4_J4_cmpeqi_fp1_jump_t
  24 // V4_J4_cmpeqi_tp0_jump_nt
  25 // V4_J4_cmpeqi_tp0_jump_t
  26 // V4_J4_cmpeqi_tp1_jump_nt
  27 // V4_J4_cmpeqi_tp1_jump_t
  28 // V4_J4_cmpeqn1_fp0_jump_nt
  29 // V4_J4_cmpeqn1_fp0_jump_t
  30 // V4_J4_cmpeqn1_fp1_jump_nt
  31 // V4_J4_cmpeqn1_fp1_jump_t
  32 // V4_J4_cmpeqn1_tp0_jump_nt
  33 // V4_J4_cmpeqn1_tp0_jump_t
  34 // V4_J4_cmpeqn1_tp1_jump_nt
  35 // V4_J4_cmpeqn1_tp1_jump_t
  36 // V4_J4_cmpgt_fp0_jump_nt
  37 // V4_J4_cmpgt_fp0_jump_t
  38 // V4_J4_cmpgt_fp1_jump_nt
  39 // V4_J4_cmpgt_fp1_jump_t
  40 // V4_J4_cmpgt_tp0_jump_nt
  41 // V4_J4_cmpgt_tp0_jump_t
  42 // V4_J4_cmpgt_tp1_jump_nt
  43 // V4_J4_cmpgt_tp1_jump_t
  44 // V4_J4_cmpgti_fp0_jump_nt
  45 // V4_J4_cmpgti_fp0_jump_t
  46 // V4_J4_cmpgti_fp1_jump_nt
  47 // V4_J4_cmpgti_fp1_jump_t
  48 // V4_J4_cmpgti_tp0_jump_nt
  49 // V4_J4_cmpgti_tp0_jump_t
  50 // V4_J4_cmpgti_tp1_jump_nt
  51 // V4_J4_cmpgti_tp1_jump_t
  52 // V4_J4_cmpgtn1_fp0_jump_nt
  53 // V4_J4_cmpgtn1_fp0_jump_t
  54 // V4_J4_cmpgtn1_fp1_jump_nt
  55 // V4_J4_cmpgtn1_fp1_jump_t
  56 // V4_J4_cmpgtn1_tp0_jump_nt
  57 // V4_J4_cmpgtn1_tp0_jump_t
  58 // V4_J4_cmpgtn1_tp1_jump_nt
  59 // V4_J4_cmpgtn1_tp1_jump_t
  60 // V4_J4_cmpgtu_fp0_jump_nt
  61 // V4_J4_cmpgtu_fp0_jump_t
  62 // V4_J4_cmpgtu_fp1_jump_nt
  63 // V4_J4_cmpgtu_fp1_jump_t
  64 // V4_J4_cmpgtu_tp0_jump_nt
  65 // V4_J4_cmpgtu_tp0_jump_t
  66 // V4_J4_cmpgtu_tp1_jump_nt
  67 // V4_J4_cmpgtu_tp1_jump_t
  68 // V4_J4_cmpgtui_fp0_jump_nt
  69 // V4_J4_cmpgtui_fp0_jump_t
  70 // V4_J4_cmpgtui_fp1_jump_nt
  71 // V4_J4_cmpgtui_fp1_jump_t
  72 // V4_J4_cmpgtui_tp0_jump_nt
  73 // V4_J4_cmpgtui_tp0_jump_t
  74 // V4_J4_cmpgtui_tp1_jump_nt
  75 // V4_J4_cmpgtui_tp1_jump_t
  76 // V4_J4_tstbit0_fp0_jump_nt
  77 // V4_J4_tstbit0_fp0_jump_t
  78 // V4_J4_tstbit0_fp1_jump_nt
  79 // V4_J4_tstbit0_fp1_jump_t
  80 // V4_J4_tstbit0_tp0_jump_nt
  81 // V4_J4_tstbit0_tp0_jump_t
  82 // V4_J4_tstbit0_tp1_jump_nt
  83 // V4_J4_tstbit0_tp1_jump_t
  84 // JMP
  85 // JMPEXT
  86 // JMPEXT_f
  87 // JMPEXT_fnew_nt
  88 // JMPEXT_fnew_t
  89 // JMPEXT_t
  90 // JMPEXT_tnew_nt
  91 // JMPEXT_tnew_t
  92 // JMPNOTEXT
  93 // JMPNOTEXT_f
  94 // JMPNOTEXT_fnew_nt
  95 // JMPNOTEXT_fnew_t
  96 // JMPNOTEXT_t
  97 // JMPNOTEXT_tnew_nt
  98 // JMPNOTEXT_tnew_t
  99 // JMP_f
 100 // JMP_fnew_nt
 101 // JMP_fnew_t
 102 // JMP_t
 103 // JMP_tnew_nt
 104 // JMP_tnew_t
 105 // RESTORE_DEALLOC_RET_JMP_V4
 106 // RESTORE_DEALLOC_RET_JMP_V4_EXT
 107
 108 def HexagonV62ItinList : ScalarItin, HVXV62Itin {
 109   list<InstrItinData> ItinList =
 110     !listconcat(ScalarItin_list, HVXV62Itin_list);
 111 }
 112
 113 def HexagonItinerariesV62 :
 114       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
 115                             CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
 116                             CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL],
 117                            [], HexagonV62ItinList.ItinList>;
 118
 119 def HexagonModelV62 : SchedMachineModel {
 120   // Max issue per cycle == bundle width.
 121   let IssueWidth = 4;
 122   let Itineraries = HexagonItinerariesV62;
 123   let LoadLatency = 1;
 124   let CompleteModel = 0;
 125 }
 126
 127 //===----------------------------------------------------------------------===//
 128 // Hexagon V62 Resource Definitions -
 129 //===----------------------------------------------------------------------===//