1 //=-HexagonScheduleV66.td - HexagonV66 Scheduling Definitions *- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // ScalarItin and HVXItin contain some old itineraries
12 // still used by a handful of instructions. Hopefully, we will be able
13 // to get rid of them soon.
15 def HexagonV66ItinList : DepScalarItinV66, ScalarItin,
16 DepHVXItinV66, HVXItin, PseudoItin {
17 list<InstrItinData> ItinList =
18 !listconcat(DepScalarItinV66_list, ScalarItin_list,
19 DepHVXItinV66_list, HVXItin_list, PseudoItin_list);
22 def HexagonItinerariesV66 :
23 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
24 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
25 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
26 CVI_ALL_NOMEM, CVI_ZW],
28 HexagonV66ItinList.ItinList>;
30 def HexagonModelV66 : SchedMachineModel {
31 // Max issue per cycle == bundle width.
33 let Itineraries = HexagonItinerariesV66;
35 let CompleteModel = 0;
38 //===----------------------------------------------------------------------===//
39 // Hexagon V66 Resource Definitions -
40 //===----------------------------------------------------------------------===//