1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
18 //===----------------------------------------------------------------------===//
20 #include "HexagonMachineFunctionInfo.h"
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
23 #include "HexagonTargetObjectFile.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/CodeGen/LatencyPriorityQueue.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
46 #define DEBUG_TYPE "xfer"
50 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
51 const HexagonTargetMachine &QTM;
55 HexagonSplitConst32AndConst64(const HexagonTargetMachine &TM)
56 : MachineFunctionPass(ID), QTM(TM) {}
58 const char *getPassName() const override {
59 return "Hexagon Split Const32s and Const64s";
61 bool runOnMachineFunction(MachineFunction &Fn) override;
65 char HexagonSplitConst32AndConst64::ID = 0;
68 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
70 const HexagonTargetObjectFile &TLOF =
71 (const HexagonTargetObjectFile &)
72 QTM.getTargetLowering()->getObjFileLowering();
73 if (TLOF.IsSmallDataEnabled())
76 const TargetInstrInfo *TII = QTM.getInstrInfo();
78 // Loop over all of the basic blocks
79 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
80 MBBb != MBBe; ++MBBb) {
81 MachineBasicBlock* MBB = MBBb;
82 // Traverse the basic block
83 MachineBasicBlock::iterator MII = MBB->begin();
84 MachineBasicBlock::iterator MIE = MBB->end ();
86 MachineInstr *MI = MII;
87 int Opc = MI->getOpcode();
88 if (Opc == Hexagon::CONST32_set) {
89 int DestReg = MI->getOperand(0).getReg();
90 MachineOperand &Symbol = MI->getOperand (1);
92 BuildMI (*MBB, MII, MI->getDebugLoc(),
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
94 BuildMI (*MBB, MII, MI->getDebugLoc(),
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
96 // MBB->erase returns the iterator to the next instruction, which is the
97 // one we want to process next
98 MII = MBB->erase (MI);
101 else if (Opc == Hexagon::CONST32_set_jt) {
102 int DestReg = MI->getOperand(0).getReg();
103 MachineOperand &Symbol = MI->getOperand (1);
105 BuildMI (*MBB, MII, MI->getDebugLoc(),
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
107 BuildMI (*MBB, MII, MI->getDebugLoc(),
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
109 // MBB->erase returns the iterator to the next instruction, which is the
110 // one we want to process next
111 MII = MBB->erase (MI);
114 else if (Opc == Hexagon::CONST32_Label) {
115 int DestReg = MI->getOperand(0).getReg();
116 MachineOperand &Symbol = MI->getOperand (1);
118 BuildMI (*MBB, MII, MI->getDebugLoc(),
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
120 BuildMI (*MBB, MII, MI->getDebugLoc(),
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
122 // MBB->erase returns the iterator to the next instruction, which is the
123 // one we want to process next
124 MII = MBB->erase (MI);
127 else if (Opc == Hexagon::CONST32_Int_Real) {
128 int DestReg = MI->getOperand(0).getReg();
129 int64_t ImmValue = MI->getOperand(1).getImm ();
131 BuildMI (*MBB, MII, MI->getDebugLoc(),
132 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
133 BuildMI (*MBB, MII, MI->getDebugLoc(),
134 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
135 MII = MBB->erase (MI);
138 else if (Opc == Hexagon::CONST64_Int_Real) {
139 int DestReg = MI->getOperand(0).getReg();
140 int64_t ImmValue = MI->getOperand(1).getImm ();
142 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
144 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
146 int32_t LowWord = (ImmValue & 0xFFFFFFFF);
147 int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
149 // Lower Registers Lower Half
150 BuildMI (*MBB, MII, MI->getDebugLoc(),
151 TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
152 // Lower Registers Higher Half
153 BuildMI (*MBB, MII, MI->getDebugLoc(),
154 TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
155 // Higher Registers Lower Half
156 BuildMI (*MBB, MII, MI->getDebugLoc(),
157 TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
158 // Higher Registers Higher Half.
159 BuildMI (*MBB, MII, MI->getDebugLoc(),
160 TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
161 MII = MBB->erase (MI);
173 //===----------------------------------------------------------------------===//
174 // Public Constructor Functions
175 //===----------------------------------------------------------------------===//
178 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
179 return new HexagonSplitConst32AndConst64(TM);