1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonSubtarget.h"
16 #include "HexagonRegisterInfo.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/ErrorHandling.h"
25 #define DEBUG_TYPE "hexagon-subtarget"
27 #define GET_SUBTARGETINFO_CTOR
28 #define GET_SUBTARGETINFO_TARGET_DESC
29 #include "HexagonGenSubtargetInfo.inc"
31 static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
32 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
33 cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
35 static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
36 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
37 cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
39 static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
40 cl::Hidden, cl::ZeroOrMore, cl::init(false),
41 cl::desc("Generate non-chopped conversion from fp to int."));
43 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
44 cl::Hidden, cl::ZeroOrMore, cl::init(true));
46 static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
47 cl::Hidden, cl::ZeroOrMore, cl::init(false),
48 cl::desc("Enable Hexagon Double Vector eXtensions"));
50 static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
51 cl::Hidden, cl::ZeroOrMore, cl::init(false),
52 cl::desc("Enable Hexagon Vector eXtensions"));
54 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
55 cl::Hidden, cl::ZeroOrMore, cl::init(false));
57 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
58 cl::Hidden, cl::ZeroOrMore, cl::init(true),
59 cl::desc("Enable the scheduler to generate .cur"));
61 static cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched",
62 cl::Hidden, cl::ZeroOrMore, cl::init(true));
64 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
65 cl::Hidden, cl::ZeroOrMore, cl::init(false),
66 cl::desc("Disable Hexagon MI Scheduling"));
68 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
69 cl::Hidden, cl::ZeroOrMore, cl::init(false),
70 cl::desc("Enable subregister liveness tracking for Hexagon"));
72 void HexagonSubtarget::initializeEnvironment() {
74 ModeIEEERndNear = false;
75 UseBSBScheduling = false;
79 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
80 CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU);
82 static std::map<StringRef, HexagonArchEnum> CpuTable {
85 { "hexagonv55", V55 },
86 { "hexagonv60", V60 },
89 auto foundIt = CpuTable.find(CPUString);
90 if (foundIt != CpuTable.end())
91 HexagonArchVersion = foundIt->second;
93 llvm_unreachable("Unrecognized Hexagon processor version");
97 ParseSubtargetFeatures(CPUString, FS);
99 if (EnableHexagonHVX.getPosition())
100 UseHVXOps = EnableHexagonHVX;
101 if (EnableHexagonHVXDouble.getPosition())
102 UseHVXDblOps = EnableHexagonHVXDouble;
107 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
108 StringRef FS, const TargetMachine &TM)
109 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
110 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
113 initializeEnvironment();
115 // Initialize scheduling itinerary for the specified CPU.
116 InstrItins = getInstrItineraryForCPU(CPUString);
118 // UseMemOps on by default unless disabled explicitly
121 else if (EnableMemOps)
126 if (EnableIEEERndNear)
127 ModeIEEERndNear = true;
129 ModeIEEERndNear = false;
131 UseBSBScheduling = hasV60TOps() && EnableBSBSched;
135 void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
136 for (auto &SU : DAG->SUnits) {
139 SmallVector<SDep, 4> Erase;
140 for (auto &D : SU.Preds)
141 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
143 for (auto &E : Erase)
147 for (auto &SU : DAG->SUnits) {
148 // Update the latency of chain edges between v60 vector load or store
149 // instructions to be 1. These instructions cannot be scheduled in the
151 MachineInstr *MI1 = SU.getInstr();
152 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
153 bool IsStoreMI1 = MI1->mayStore();
154 bool IsLoadMI1 = MI1->mayLoad();
155 if (!QII->isV60VectorInstruction(MI1) || !(IsStoreMI1 || IsLoadMI1))
157 for (auto &SI : SU.Succs) {
158 if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
160 MachineInstr *MI2 = SI.getSUnit()->getInstr();
161 if (!QII->isV60VectorInstruction(MI2))
163 if ((IsStoreMI1 && MI2->mayStore()) || (IsLoadMI1 && MI2->mayLoad())) {
166 // Change the dependence in the opposite direction too.
167 for (auto &PI : SI.getSUnit()->Preds) {
168 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
171 SI.getSUnit()->setDepthDirty();
179 void HexagonSubtarget::getPostRAMutations(
180 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
181 Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
185 // Pin the vtable to this file.
186 void HexagonSubtarget::anchor() {}
188 bool HexagonSubtarget::enableMachineScheduler() const {
189 if (DisableHexagonMISched.getNumOccurrences())
190 return !DisableHexagonMISched;
194 bool HexagonSubtarget::enableSubRegLiveness() const {
195 return EnableSubregLiveness;
198 // This helper function is responsible for increasing the latency only.
199 void HexagonSubtarget::updateLatency(MachineInstr *SrcInst,
200 MachineInstr *DstInst, SDep &Dep) const {
204 auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
206 if (EnableVecFrwdSched && QII.addLatencyToSchedule(SrcInst, DstInst)) {
207 // Vec frwd scheduling.
208 Dep.setLatency(Dep.getLatency() + 1);
209 } else if (useBSBScheduling() &&
210 QII.isLateInstrFeedsEarlyInstr(SrcInst, DstInst)) {
212 Dep.setLatency(Dep.getLatency() + 1);
213 } else if (EnableTCLatencySched) {
214 // TClass latency scheduling.
215 // Check if SrcInst produces in 2C an operand of DstInst taken in stage 2B.
216 if (QII.isTC1(SrcInst) || QII.isTC2(SrcInst))
217 if (!QII.isTC1(DstInst) && !QII.isTC2(DstInst))
218 Dep.setLatency(Dep.getLatency() + 1);
222 /// If the SUnit has a zero latency edge, return the other SUnit.
223 static SUnit *getZeroLatency(SUnit *N, SmallVector<SDep, 4> &Deps) {
225 if (I.isAssignedRegDep() && I.getLatency() == 0 &&
226 !I.getSUnit()->getInstr()->isPseudo())
231 /// Change the latency between the two SUnits.
232 void HexagonSubtarget::changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps,
233 SUnit *Dst, unsigned Lat) const {
234 MachineInstr *SrcI = Src->getInstr();
235 for (auto &I : Deps) {
236 if (I.getSUnit() != Dst)
239 SUnit *UpdateDst = I.getSUnit();
240 updateLatency(SrcI, UpdateDst->getInstr(), I);
241 // Update the latency of opposite edge too.
242 for (auto &PI : UpdateDst->Preds) {
243 if (PI.getSUnit() != Src || !PI.isAssignedRegDep())
246 updateLatency(SrcI, UpdateDst->getInstr(), PI);
251 // Return true if these are the best two instructions to schedule
252 // together with a zero latency. Only one dependence should have a zero
253 // latency. If there are multiple choices, choose the best, and change
254 // ther others, if needed.
255 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
256 const HexagonInstrInfo *TII) const {
257 MachineInstr *SrcInst = Src->getInstr();
258 MachineInstr *DstInst = Dst->getInstr();
260 if (SrcInst->isPHI() || DstInst->isPHI())
263 // Check if the Dst instruction is the best candidate first.
264 SUnit *Best = nullptr;
265 SUnit *DstBest = nullptr;
266 SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
267 if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
268 // Check that Src doesn't have a better candidate.
269 DstBest = getZeroLatency(Src, Src->Succs);
270 if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
276 // The caller frequents adds the same dependence twice. If so, then
277 // return true for this case too.
278 if (Src == SrcBest && Dst == DstBest)
281 // Reassign the latency for the previous bests, which requires setting
282 // the dependence edge in both directions.
283 if (SrcBest != nullptr)
284 changeLatency(SrcBest, SrcBest->Succs, Dst, 1);
285 if (DstBest != nullptr)
286 changeLatency(Src, Src->Succs, DstBest, 1);
287 // If there is an edge from SrcBest to DstBst, then try to change that
289 if (SrcBest && DstBest)
290 changeLatency(SrcBest, SrcBest->Succs, DstBest, 0);
295 // Update the latency of a Phi when the Phi bridges two instructions that
296 // require a multi-cycle latency.
297 void HexagonSubtarget::changePhiLatency(MachineInstr *SrcInst, SUnit *Dst,
299 if (!SrcInst->isPHI() || Dst->NumPreds == 0 || Dep.getLatency() != 0)
302 for (const SDep &PI : Dst->Preds) {
303 if (PI.getLatency() != 0)
310 /// \brief Perform target specific adjustments to the latency of a schedule
312 void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
314 MachineInstr *SrcInst = Src->getInstr();
315 MachineInstr *DstInst = Dst->getInstr();
316 if (!Src->isInstr() || !Dst->isInstr())
319 const HexagonInstrInfo *QII = static_cast<const HexagonInstrInfo *>(getInstrInfo());
321 // Instructions with .new operands have zero latency.
322 if (QII->canExecuteInBundle(SrcInst, DstInst) &&
323 isBestZeroLatency(Src, Dst, QII)) {
331 // Don't adjust the latency of post-increment part of the instruction.
332 if (QII->isPostIncrement(SrcInst) && Dep.isAssignedRegDep()) {
333 if (SrcInst->mayStore())
335 if (Dep.getReg() != SrcInst->getOperand(0).getReg())
337 } else if (QII->isPostIncrement(DstInst) && Dep.getKind() == SDep::Anti) {
338 if (DstInst->mayStore())
340 if (Dep.getReg() != DstInst->getOperand(0).getReg())
342 } else if (QII->isPostIncrement(DstInst) && DstInst->mayStore() &&
343 Dep.isAssignedRegDep()) {
344 MachineOperand &Op = DstInst->getOperand(DstInst->getNumOperands() - 1);
345 if (Op.isReg() && Dep.getReg() != Op.getReg())
349 // Check if we need to change any the latency values when Phis are added.
350 if (useBSBScheduling() && SrcInst->isPHI()) {
351 changePhiLatency(SrcInst, Dst, Dep);
355 // If it's a REG_SEQUENCE, use its destination instruction to determine
356 // the correct latency.
357 if (DstInst->isRegSequence() && Dst->NumSuccs == 1)
358 DstInst = Dst->Succs[0].getSUnit()->getInstr();
360 // Try to schedule uses near definitions to generate .cur.
361 if (EnableDotCurSched && QII->isToBeScheduledASAP(SrcInst, DstInst) &&
362 isBestZeroLatency(Src, Dst, QII)) {
367 updateLatency(SrcInst, DstInst, Dep);