1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
17 #include "HexagonDepArch.h"
18 #include "HexagonFrameLowering.h"
19 #include "HexagonISelLowering.h"
20 #include "HexagonInstrInfo.h"
21 #include "HexagonRegisterInfo.h"
22 #include "HexagonSelectionDAGInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/CodeGen/ScheduleDAGMutation.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/MC/MCInstrItineraries.h"
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
43 class HexagonSubtarget : public HexagonGenSubtargetInfo {
44 virtual void anchor();
46 bool UseHVX64BOps = false;
47 bool UseHVX128BOps = false;
49 bool UseLongCalls = false;
50 bool UseMemops = false;
51 bool UsePackets = false;
52 bool UseNewValueJumps = false;
53 bool UseNewValueStores = false;
54 bool UseSmallData = false;
55 bool UseZRegOps = false;
57 bool HasMemNoShuf = false;
58 bool EnableDuplex = false;
59 bool ReservedR19 = false;
60 bool NoreturnStackElim = false;
63 Hexagon::ArchEnum HexagonArchVersion;
64 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
65 CodeGenOpt::Level OptLevel;
66 /// True if the target should use Back-Skip-Back scheduling. This is the
68 bool UseBSBScheduling;
70 struct UsrOverflowMutation : public ScheduleDAGMutation {
71 void apply(ScheduleDAGInstrs *DAG) override;
73 struct HVXMemLatencyMutation : public ScheduleDAGMutation {
74 void apply(ScheduleDAGInstrs *DAG) override;
76 struct CallMutation : public ScheduleDAGMutation {
77 void apply(ScheduleDAGInstrs *DAG) override;
79 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
80 const SUnit &Inst1, const SUnit &Inst2) const;
82 struct BankConflictMutation : public ScheduleDAGMutation {
83 void apply(ScheduleDAGInstrs *DAG) override;
87 std::string CPUString;
88 HexagonInstrInfo InstrInfo;
89 HexagonRegisterInfo RegInfo;
90 HexagonTargetLowering TLInfo;
91 HexagonSelectionDAGInfo TSInfo;
92 HexagonFrameLowering FrameLowering;
93 InstrItineraryData InstrItins;
96 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
97 const TargetMachine &TM);
99 /// getInstrItins - Return the instruction itineraries based on subtarget
101 const InstrItineraryData *getInstrItineraryData() const override {
104 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
105 const HexagonRegisterInfo *getRegisterInfo() const override {
108 const HexagonTargetLowering *getTargetLowering() const override {
111 const HexagonFrameLowering *getFrameLowering() const override {
112 return &FrameLowering;
114 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
118 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
121 /// ParseSubtargetFeatures - Parses features string setting specified
122 /// subtarget options. Definition of function is auto generated by tblgen.
123 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
125 bool hasV5Ops() const {
126 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
128 bool hasV5OpsOnly() const {
129 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
131 bool hasV55Ops() const {
132 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
134 bool hasV55OpsOnly() const {
135 return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
137 bool hasV60Ops() const {
138 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
140 bool hasV60OpsOnly() const {
141 return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
143 bool hasV62Ops() const {
144 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
146 bool hasV62OpsOnly() const {
147 return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
149 bool hasV65Ops() const {
150 return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
152 bool hasV65OpsOnly() const {
153 return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
155 bool hasV66Ops() const {
156 return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
158 bool hasV66OpsOnly() const {
159 return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
162 bool useLongCalls() const { return UseLongCalls; }
163 bool useMemops() const { return UseMemops; }
164 bool usePackets() const { return UsePackets; }
165 bool useNewValueJumps() const { return UseNewValueJumps; }
166 bool useNewValueStores() const { return UseNewValueStores; }
167 bool useSmallData() const { return UseSmallData; }
168 bool useZRegOps() const { return UseZRegOps; }
170 bool useHVXOps() const {
171 return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
173 bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
174 bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
176 bool hasMemNoShuf() const { return HasMemNoShuf; }
177 bool hasReservedR19() const { return ReservedR19; }
178 bool usePredicatedCalls() const;
180 bool noreturnStackElim() const { return NoreturnStackElim; }
182 bool useBSBScheduling() const { return UseBSBScheduling; }
183 bool enableMachineScheduler() const override;
185 // Always use the TargetLowering default scheduler.
186 // FIXME: This will use the vliw scheduler which is probably just hurting
187 // compiler time and will be removed eventually anyway.
188 bool enableMachineSchedDefaultSched() const override { return false; }
190 AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
191 bool enablePostRAScheduler() const override { return true; }
193 bool enableSubRegLiveness() const override;
195 const std::string &getCPUString () const { return CPUString; }
197 const Hexagon::ArchEnum &getHexagonArchVersion() const {
198 return HexagonArchVersion;
201 void getPostRAMutations(
202 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
205 void getSMSMutations(
206 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
209 /// Enable use of alias analysis during code generation (during MI
210 /// scheduling, DAGCombine, etc.).
211 bool useAA() const override;
213 /// Perform target specific adjustments to the latency of a schedule
215 void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
217 unsigned getVectorLength() const {
223 llvm_unreachable("Invalid HVX vector length settings");
226 ArrayRef<MVT> getHVXElementTypes() const {
227 static MVT Types[] = { MVT::i8, MVT::i16, MVT::i32 };
228 return makeArrayRef(Types);
231 bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
232 if (!VecTy.isVector() || !useHVXOps())
234 MVT ElemTy = VecTy.getVectorElementType();
235 if (!IncludeBool && ElemTy == MVT::i1)
238 unsigned HwLen = getVectorLength();
239 unsigned NumElems = VecTy.getVectorNumElements();
240 ArrayRef<MVT> ElemTypes = getHVXElementTypes();
242 if (IncludeBool && ElemTy == MVT::i1) {
243 // Special case for the v512i1, etc.
244 if (8*HwLen == NumElems)
246 // Boolean HVX vector types are formed from regular HVX vector types
247 // by replacing the element type with i1.
248 for (MVT T : ElemTypes)
249 if (NumElems * T.getSizeInBits() == 8*HwLen)
254 unsigned VecWidth = VecTy.getSizeInBits();
255 if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
257 return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
260 unsigned getTypeAlignment(MVT Ty) const {
261 if (isHVXVectorType(Ty, true))
262 return getVectorLength();
263 return Ty.getSizeInBits() / 8;
266 unsigned getL1CacheLineSize() const;
267 unsigned getL1PrefetchDistance() const;
270 // Helper function responsible for increasing the latency only.
271 void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
273 void restoreLatency(SUnit *Src, SUnit *Dst) const;
274 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
275 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
276 SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
279 } // end namespace llvm
281 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H