1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
17 #include "HexagonFrameLowering.h"
18 #include "HexagonInstrInfo.h"
19 #include "HexagonISelLowering.h"
20 #include "HexagonSelectionDAGInfo.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/CodeGen/ScheduleDAGMutation.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
30 #define GET_SUBTARGETINFO_HEADER
31 #include "HexagonGenSubtargetInfo.inc"
33 #define Hexagon_SMALL_DATA_THRESHOLD 8
34 #define Hexagon_SLOTS 4
44 class HexagonSubtarget : public HexagonGenSubtargetInfo {
45 virtual void anchor();
47 bool UseMemOps, UseHVXOps, UseHVXDblOps;
52 #include "HexagonDepArch.h"
54 HexagonArchEnum HexagonArchVersion;
55 /// True if the target should use Back-Skip-Back scheduling. This is the
57 bool UseBSBScheduling;
59 class HexagonDAGMutation : public ScheduleDAGMutation {
61 void apply(ScheduleDAGInstrs *DAG) override;
65 std::string CPUString;
66 HexagonInstrInfo InstrInfo;
67 HexagonTargetLowering TLInfo;
68 HexagonSelectionDAGInfo TSInfo;
69 HexagonFrameLowering FrameLowering;
70 InstrItineraryData InstrItins;
72 void initializeEnvironment();
75 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
76 const TargetMachine &TM);
78 /// getInstrItins - Return the instruction itineraries based on subtarget
80 const InstrItineraryData *getInstrItineraryData() const override {
83 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
84 const HexagonRegisterInfo *getRegisterInfo() const override {
85 return &InstrInfo.getRegisterInfo();
87 const HexagonTargetLowering *getTargetLowering() const override {
90 const HexagonFrameLowering *getFrameLowering() const override {
91 return &FrameLowering;
93 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
97 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
100 /// ParseSubtargetFeatures - Parses features string setting specified
101 /// subtarget options. Definition of function is auto generated by tblgen.
102 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
104 bool useMemOps() const { return UseMemOps; }
105 bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
106 bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
107 bool hasV55TOps() const { return getHexagonArchVersion() >= V55; }
108 bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; }
109 bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
110 bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
111 bool hasV62TOps() const { return getHexagonArchVersion() >= V62; }
112 bool hasV62TOpsOnly() const { return getHexagonArchVersion() == V62; }
114 bool modeIEEERndNear() const { return ModeIEEERndNear; }
115 bool useHVXOps() const { return UseHVXOps; }
116 bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }
117 bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
118 bool useLongCalls() const { return UseLongCalls; }
119 bool usePredicatedCalls() const;
121 bool useBSBScheduling() const { return UseBSBScheduling; }
122 bool enableMachineScheduler() const override;
124 // Always use the TargetLowering default scheduler.
125 // FIXME: This will use the vliw scheduler which is probably just hurting
126 // compiler time and will be removed eventually anyway.
127 bool enableMachineSchedDefaultSched() const override { return false; }
129 AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
130 bool enablePostRAScheduler() const override { return true; }
132 bool enableSubRegLiveness() const override;
134 const std::string &getCPUString () const { return CPUString; }
136 // Threshold for small data section
137 unsigned getSmallDataThreshold() const {
138 return Hexagon_SMALL_DATA_THRESHOLD;
141 const HexagonArchEnum &getHexagonArchVersion() const {
142 return HexagonArchVersion;
145 void getPostRAMutations(
146 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
149 void getSMSMutations(
150 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
153 /// \brief Perform target specific adjustments to the latency of a schedule
155 void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
157 unsigned getL1CacheLineSize() const;
158 unsigned getL1PrefetchDistance() const;
161 // Helper function responsible for increasing the latency only.
162 void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
164 void restoreLatency(SUnit *Src, SUnit *Dst) const;
165 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
166 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
167 SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
170 } // end namespace llvm
172 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H