1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32 cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35 cl::init(true), cl::desc("Enable RDF-based optimizations"));
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41 cl::Hidden, cl::ZeroOrMore, cl::init(false),
42 cl::desc("Disable Hexagon Addressing Mode Optimization"));
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45 cl::Hidden, cl::ZeroOrMore, cl::init(false),
46 cl::desc("Disable Hexagon CFG Optimization"));
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49 cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52 cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55 cl::init(true), cl::Hidden, cl::ZeroOrMore,
56 cl::desc("Early expansion of MUX"));
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59 cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71 cl::desc("Enable converting conditional transfers into MUX instructions"));
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75 "predicate instructions"));
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78 cl::init(false), cl::Hidden, cl::ZeroOrMore,
79 cl::desc("Enable loop data prefetch on Hexagon"));
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82 cl::desc("Disable splitting double registers"));
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85 cl::Hidden, cl::desc("Bit simplification"));
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88 cl::Hidden, cl::desc("Loop rescheduling"));
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91 cl::Hidden, cl::desc("Disable backend optimizations"));
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94 cl::Hidden, cl::ZeroOrMore, cl::init(false),
95 cl::desc("Enable Hexagon Vector print instr pass"));
97 static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
98 cl::Hidden, cl::ZeroOrMore, cl::init(false),
99 cl::desc("Enable generating trap for unreachable"));
101 /// HexagonTargetMachineModule - Note that this is used on hosts that
102 /// cannot link in a library unless there are references into the
103 /// library. In particular, it seems that it is not possible to get
104 /// things to work on Win32 without this. Though it is unused, do not
106 extern "C" int HexagonTargetMachineModule;
107 int HexagonTargetMachineModule = 0;
109 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
110 ScheduleDAGMILive *DAG =
111 new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
112 DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
113 DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
114 DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
115 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
119 static MachineSchedRegistry
120 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
121 createVLIWMachineSched);
124 extern char &HexagonExpandCondsetsID;
125 void initializeHexagonConstExtendersPass(PassRegistry&);
126 void initializeHexagonEarlyIfConversionPass(PassRegistry&);
127 void initializeHexagonExpandCondsetsPass(PassRegistry&);
128 void initializeHexagonGenMuxPass(PassRegistry&);
129 void initializeHexagonHardwareLoopsPass(PassRegistry&);
130 void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
131 void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
132 void initializeHexagonNewValueJumpPass(PassRegistry&);
133 void initializeHexagonOptAddrModePass(PassRegistry&);
134 void initializeHexagonPacketizerPass(PassRegistry&);
135 void initializeHexagonRDFOptPass(PassRegistry&);
136 Pass *createHexagonLoopIdiomPass();
137 Pass *createHexagonVectorLoopCarriedReusePass();
139 FunctionPass *createHexagonBitSimplify();
140 FunctionPass *createHexagonBranchRelaxation();
141 FunctionPass *createHexagonCallFrameInformation();
142 FunctionPass *createHexagonCFGOptimizer();
143 FunctionPass *createHexagonCommonGEP();
144 FunctionPass *createHexagonConstExtenders();
145 FunctionPass *createHexagonConstPropagationPass();
146 FunctionPass *createHexagonCopyToCombine();
147 FunctionPass *createHexagonEarlyIfConversion();
148 FunctionPass *createHexagonFixupHwLoops();
149 FunctionPass *createHexagonGatherPacketize();
150 FunctionPass *createHexagonGenExtract();
151 FunctionPass *createHexagonGenInsert();
152 FunctionPass *createHexagonGenMux();
153 FunctionPass *createHexagonGenPredicate();
154 FunctionPass *createHexagonHardwareLoops();
155 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
156 CodeGenOpt::Level OptLevel);
157 FunctionPass *createHexagonLoopRescheduling();
158 FunctionPass *createHexagonNewValueJump();
159 FunctionPass *createHexagonOptimizeSZextends();
160 FunctionPass *createHexagonOptAddrMode();
161 FunctionPass *createHexagonPacketizer();
162 FunctionPass *createHexagonPeephole();
163 FunctionPass *createHexagonRDFOpt();
164 FunctionPass *createHexagonSplitConst32AndConst64();
165 FunctionPass *createHexagonSplitDoubleRegs();
166 FunctionPass *createHexagonStoreWidening();
167 FunctionPass *createHexagonVectorPrint();
168 } // end namespace llvm;
170 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
172 return Reloc::Static;
176 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
179 return CodeModel::Small;
182 extern "C" void LLVMInitializeHexagonTarget() {
183 // Register the target.
184 RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
186 PassRegistry &PR = *PassRegistry::getPassRegistry();
187 initializeHexagonConstExtendersPass(PR);
188 initializeHexagonEarlyIfConversionPass(PR);
189 initializeHexagonGenMuxPass(PR);
190 initializeHexagonHardwareLoopsPass(PR);
191 initializeHexagonLoopIdiomRecognizePass(PR);
192 initializeHexagonVectorLoopCarriedReusePass(PR);
193 initializeHexagonNewValueJumpPass(PR);
194 initializeHexagonOptAddrModePass(PR);
195 initializeHexagonPacketizerPass(PR);
196 initializeHexagonRDFOptPass(PR);
199 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
200 StringRef CPU, StringRef FS,
201 const TargetOptions &Options,
202 Optional<Reloc::Model> RM,
203 Optional<CodeModel::Model> CM,
204 CodeGenOpt::Level OL, bool JIT)
205 // Specify the vector alignment explicitly. For v512x1, the calculated
206 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
207 // the required minimum of 64 bytes.
210 "e-m:e-p:32:32:32-a:0-n16:32-"
211 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
212 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
213 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
214 getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
215 TLOF(make_unique<HexagonTargetObjectFile>()) {
216 if (EnableTrapUnreachable)
217 this->Options.TrapUnreachable = true;
218 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
222 const HexagonSubtarget *
223 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
224 AttributeList FnAttrs = F.getAttributes();
226 FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
228 FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
230 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
231 ? CPUAttr.getValueAsString().str()
233 std::string FS = !FSAttr.hasAttribute(Attribute::None)
234 ? FSAttr.getValueAsString().str()
237 auto &I = SubtargetMap[CPU + FS];
239 // This needs to be done before we create a new subtarget since any
240 // creation will depend on the TM and the code generation flags on the
241 // function that reside in TargetOptions.
242 resetTargetOptions(F);
243 I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
248 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
250 PassManagerBuilder::EP_LateLoopOptimizations,
251 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
252 PM.add(createHexagonLoopIdiomPass());
255 PassManagerBuilder::EP_LoopOptimizerEnd,
256 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
257 PM.add(createHexagonVectorLoopCarriedReusePass());
261 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
262 return TargetIRAnalysis([this](const Function &F) {
263 return TargetTransformInfo(HexagonTTIImpl(this, F));
268 HexagonTargetMachine::~HexagonTargetMachine() {}
271 /// Hexagon Code Generator Pass Configuration Options.
272 class HexagonPassConfig : public TargetPassConfig {
274 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
275 : TargetPassConfig(TM, PM) {}
277 HexagonTargetMachine &getHexagonTargetMachine() const {
278 return getTM<HexagonTargetMachine>();
282 createMachineScheduler(MachineSchedContext *C) const override {
283 return createVLIWMachineSched(C);
286 void addIRPasses() override;
287 bool addInstSelector() override;
288 void addPreRegAlloc() override;
289 void addPostRegAlloc() override;
290 void addPreSched2() override;
291 void addPreEmitPass() override;
295 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
296 return new HexagonPassConfig(*this, PM);
299 void HexagonPassConfig::addIRPasses() {
300 TargetPassConfig::addIRPasses();
301 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
303 addPass(createAtomicExpandPass());
305 if (EnableLoopPrefetch)
306 addPass(createLoopDataPrefetchPass());
308 addPass(createHexagonCommonGEP());
309 // Replace certain combinations of shifts and ands with extracts.
310 if (EnableGenExtract)
311 addPass(createHexagonGenExtract());
315 bool HexagonPassConfig::addInstSelector() {
316 HexagonTargetMachine &TM = getHexagonTargetMachine();
317 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
320 addPass(createHexagonOptimizeSZextends());
322 addPass(createHexagonISelDag(TM, getOptLevel()));
325 // Create logical operations on predicate registers.
327 addPass(createHexagonGenPredicate());
328 // Rotate loops to expose bit-simplification opportunities.
329 if (EnableLoopResched)
330 addPass(createHexagonLoopRescheduling());
331 // Split double registers.
333 addPass(createHexagonSplitDoubleRegs());
334 // Bit simplification.
335 if (EnableBitSimplify)
336 addPass(createHexagonBitSimplify());
337 addPass(createHexagonPeephole());
338 // Constant propagation.
340 addPass(createHexagonConstPropagationPass());
341 addPass(&UnreachableMachineBlockElimID);
344 addPass(createHexagonGenInsert());
346 addPass(createHexagonEarlyIfConversion());
352 void HexagonPassConfig::addPreRegAlloc() {
353 if (getOptLevel() != CodeGenOpt::None) {
355 addPass(createHexagonConstExtenders());
356 if (EnableExpandCondsets)
357 insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
358 if (!DisableStoreWidening)
359 addPass(createHexagonStoreWidening());
360 if (!DisableHardwareLoops)
361 addPass(createHexagonHardwareLoops());
363 if (TM->getOptLevel() >= CodeGenOpt::Default)
364 addPass(&MachinePipelinerID);
367 void HexagonPassConfig::addPostRegAlloc() {
368 if (getOptLevel() != CodeGenOpt::None) {
370 addPass(createHexagonRDFOpt());
371 if (!DisableHexagonCFGOpt)
372 addPass(createHexagonCFGOptimizer());
373 if (!DisableAModeOpt)
374 addPass(createHexagonOptAddrMode());
378 void HexagonPassConfig::addPreSched2() {
379 addPass(createHexagonCopyToCombine());
380 if (getOptLevel() != CodeGenOpt::None)
381 addPass(&IfConverterID);
382 addPass(createHexagonSplitConst32AndConst64());
385 void HexagonPassConfig::addPreEmitPass() {
386 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
389 addPass(createHexagonNewValueJump());
391 addPass(createHexagonBranchRelaxation());
395 if (!DisableHardwareLoops)
396 addPass(createHexagonFixupHwLoops());
397 // Generate MUX from pairs of conditional transfers.
399 addPass(createHexagonGenMux());
402 // Create packets for 2 instructions that consitute a gather instruction.
403 // Do this regardless of the opt level.
404 addPass(createHexagonGatherPacketize(), false);
407 addPass(createHexagonPacketizer(), false);
409 if (EnableVectorPrint)
410 addPass(createHexagonVectorPrint(), false);
412 // Add CFI instructions if necessary.
413 addPass(createHexagonCallFrameInformation(), false);