1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
20 #include "HexagonVLIWPacketizer.h"
22 #include "HexagonInstrInfo.h"
23 #include "HexagonRegisterInfo.h"
24 #include "HexagonSubtarget.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
31 #include "llvm/CodeGen/MachineDominators.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBundle.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/MachineOperand.h"
39 #include "llvm/CodeGen/ScheduleDAG.h"
40 #include "llvm/CodeGen/TargetRegisterInfo.h"
41 #include "llvm/CodeGen/TargetSubtargetInfo.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/raw_ostream.h"
55 #define DEBUG_TYPE "packets"
57 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
58 cl::ZeroOrMore, cl::init(false),
59 cl::desc("Disable Hexagon packetizer pass"));
61 cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
62 cl::ZeroOrMore, cl::init(true),
63 cl::desc("Allow slot1 store and slot0 load"));
65 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
66 cl::ZeroOrMore, cl::Hidden, cl::init(true),
67 cl::desc("Allow non-solo packetization of volatile memory references"));
69 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
70 cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
72 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
73 cl::init(false), cl::Hidden, cl::ZeroOrMore,
74 cl::desc("Disable vector double new-value-stores"));
76 extern cl::opt<bool> ScheduleInlineAsm;
80 FunctionPass *createHexagonPacketizer();
81 void initializeHexagonPacketizerPass(PassRegistry&);
83 } // end namespace llvm
87 class HexagonPacketizer : public MachineFunctionPass {
91 HexagonPacketizer() : MachineFunctionPass(ID) {}
93 void getAnalysisUsage(AnalysisUsage &AU) const override {
95 AU.addRequired<AAResultsWrapperPass>();
96 AU.addRequired<MachineBranchProbabilityInfo>();
97 AU.addRequired<MachineDominatorTree>();
98 AU.addRequired<MachineLoopInfo>();
99 AU.addPreserved<MachineDominatorTree>();
100 AU.addPreserved<MachineLoopInfo>();
101 MachineFunctionPass::getAnalysisUsage(AU);
104 StringRef getPassName() const override { return "Hexagon Packetizer"; }
105 bool runOnMachineFunction(MachineFunction &Fn) override;
107 MachineFunctionProperties getRequiredProperties() const override {
108 return MachineFunctionProperties().set(
109 MachineFunctionProperties::Property::NoVRegs);
113 const HexagonInstrInfo *HII;
114 const HexagonRegisterInfo *HRI;
117 } // end anonymous namespace
119 char HexagonPacketizer::ID = 0;
121 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
122 "Hexagon Packetizer", false, false)
123 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
124 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
125 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
126 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
127 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
128 "Hexagon Packetizer", false, false)
130 HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
131 MachineLoopInfo &MLI, AliasAnalysis *AA,
132 const MachineBranchProbabilityInfo *MBPI)
133 : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI) {
134 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
135 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
137 addMutation(llvm::make_unique<HexagonSubtarget::UsrOverflowMutation>());
138 addMutation(llvm::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
139 addMutation(llvm::make_unique<HexagonSubtarget::BankConflictMutation>());
142 // Check if FirstI modifies a register that SecondI reads.
143 static bool hasWriteToReadDep(const MachineInstr &FirstI,
144 const MachineInstr &SecondI,
145 const TargetRegisterInfo *TRI) {
146 for (auto &MO : FirstI.operands()) {
147 if (!MO.isReg() || !MO.isDef())
149 unsigned R = MO.getReg();
150 if (SecondI.readsRegister(R, TRI))
157 static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
158 MachineBasicBlock::iterator BundleIt, bool Before) {
159 MachineBasicBlock::instr_iterator InsertPt;
161 InsertPt = BundleIt.getInstrIterator();
163 InsertPt = std::next(BundleIt).getInstrIterator();
165 MachineBasicBlock &B = *MI.getParent();
166 // The instruction should at least be bundled with the preceding instruction
167 // (there will always be one, i.e. BUNDLE, if nothing else).
168 assert(MI.isBundledWithPred());
169 if (MI.isBundledWithSucc()) {
170 MI.clearFlag(MachineInstr::BundledSucc);
171 MI.clearFlag(MachineInstr::BundledPred);
173 // If it's not bundled with the successor (i.e. it is the last one
174 // in the bundle), then we can simply unbundle it from the predecessor,
175 // which will take care of updating the predecessor's flag.
176 MI.unbundleFromPred();
178 B.splice(InsertPt, &B, MI.getIterator());
180 // Get the size of the bundle without asserting.
181 MachineBasicBlock::const_instr_iterator I = BundleIt.getInstrIterator();
182 MachineBasicBlock::const_instr_iterator E = B.instr_end();
184 for (++I; I != E && I->isBundledWithPred(); ++I)
187 // If there are still two or more instructions, then there is nothing
192 // Otherwise, extract the single instruction out and delete the bundle.
193 MachineBasicBlock::iterator NextIt = std::next(BundleIt);
194 MachineInstr &SingleI = *BundleIt->getNextNode();
195 SingleI.unbundleFromPred();
196 assert(!SingleI.isBundledWithSucc());
197 BundleIt->eraseFromParent();
201 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
202 auto &HST = MF.getSubtarget<HexagonSubtarget>();
203 if (DisablePacketizer || !HST.usePackets() || skipFunction(MF.getFunction()))
206 HII = HST.getInstrInfo();
207 HRI = HST.getRegisterInfo();
208 auto &MLI = getAnalysis<MachineLoopInfo>();
209 auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
210 auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
212 if (EnableGenAllInsnClass)
213 HII->genAllInsnTimingClasses(MF);
215 // Instantiate the packetizer.
216 HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI);
218 // DFA state table should not be empty.
219 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
221 // Loop over all basic blocks and remove KILL pseudo-instructions
222 // These instructions confuse the dependence analysis. Consider:
224 // R0 = KILL R0, D0 (Insn 1)
226 // Here, Insn 1 will result in the dependence graph not emitting an output
227 // dependence between Insn 0 and Insn 2. This can lead to incorrect
229 for (auto &MB : MF) {
231 auto MI = MB.begin();
233 auto NextI = std::next(MI);
242 // Loop over all of the basic blocks.
243 for (auto &MB : MF) {
244 auto Begin = MB.begin(), End = MB.end();
245 while (Begin != End) {
246 // Find the first non-boundary starting from the end of the last
247 // scheduling region.
248 MachineBasicBlock::iterator RB = Begin;
249 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
251 // Find the first boundary starting from the beginning of the new
253 MachineBasicBlock::iterator RE = RB;
254 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
256 // Add the scheduling boundary if it's not block end.
259 // If RB == End, then RE == End.
261 Packetizer.PacketizeMIs(&MB, RB, RE);
267 Packetizer.unpacketizeSoloInstrs(MF);
271 // Reserve resources for a constant extender. Trigger an assertion if the
272 // reservation fails.
273 void HexagonPacketizerList::reserveResourcesForConstExt() {
274 if (!tryAllocateResourcesForConstExt(true))
275 llvm_unreachable("Resources not available");
278 bool HexagonPacketizerList::canReserveResourcesForConstExt() {
279 return tryAllocateResourcesForConstExt(false);
282 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
283 // return true, otherwise, return false.
284 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(bool Reserve) {
285 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
286 bool Avail = ResourceTracker->canReserveResources(*ExtMI);
287 if (Reserve && Avail)
288 ResourceTracker->reserveResources(*ExtMI);
289 MF.DeleteMachineInstr(ExtMI);
293 bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
294 SDep::Kind DepType, unsigned DepReg) {
295 // Check for LR dependence.
296 if (DepReg == HRI->getRARegister())
299 if (HII->isDeallocRet(MI))
300 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
303 // Call-like instructions can be packetized with preceding instructions
304 // that define registers implicitly used or modified by the call. Explicit
305 // uses are still prohibited, as in the case of indirect calls:
308 if (DepType == SDep::Data) {
309 for (const MachineOperand MO : MI.operands())
310 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
317 static bool isRegDependence(const SDep::Kind DepType) {
318 return DepType == SDep::Data || DepType == SDep::Anti ||
319 DepType == SDep::Output;
322 static bool isDirectJump(const MachineInstr &MI) {
323 return MI.getOpcode() == Hexagon::J2_jump;
326 static bool isSchedBarrier(const MachineInstr &MI) {
327 switch (MI.getOpcode()) {
328 case Hexagon::Y2_barrier:
334 static bool isControlFlow(const MachineInstr &MI) {
335 return MI.getDesc().isTerminator() || MI.getDesc().isCall();
338 /// Returns true if the instruction modifies a callee-saved register.
339 static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
340 const TargetRegisterInfo *TRI) {
341 const MachineFunction &MF = *MI.getParent()->getParent();
342 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
343 if (MI.modifiesRegister(*CSR, TRI))
348 // Returns true if an instruction can be promoted to .new predicate or
350 bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
351 const TargetRegisterClass *NewRC) {
352 // Vector stores can be predicated, and can be new-value stores, but
353 // they cannot be predicated on a .new predicate value.
354 if (NewRC == &Hexagon::PredRegsRegClass) {
355 if (HII->isHVXVec(MI) && MI.mayStore())
357 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
359 // If the class is not PredRegs, it could only apply to new-value stores.
360 return HII->mayBeNewStore(MI);
363 // Promote an instructiont to its .cur form.
364 // At this time, we have already made a call to canPromoteToDotCur and made
365 // sure that it can *indeed* be promoted.
366 bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI,
367 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
368 const TargetRegisterClass* RC) {
369 assert(DepType == SDep::Data);
370 int CurOpcode = HII->getDotCurOp(MI);
371 MI.setDesc(HII->get(CurOpcode));
375 void HexagonPacketizerList::cleanUpDotCur() {
376 MachineInstr *MI = nullptr;
377 for (auto BI : CurrentPacketMIs) {
378 LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
379 if (HII->isDotCurInst(*BI)) {
384 for (auto &MO : BI->operands())
385 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
391 // We did not find a use of the CUR, so de-cur it.
392 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
393 LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
396 // Check to see if an instruction can be dot cur.
397 bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
398 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
399 const TargetRegisterClass *RC) {
400 if (!HII->isHVXVec(MI))
402 if (!HII->isHVXVec(*MII))
405 // Already a dot new instruction.
406 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
409 if (!HII->mayBeCurLoad(MI))
412 // The "cur value" cannot come from inline asm.
413 if (PacketSU->getInstr()->isInlineAsm())
416 // Make sure candidate instruction uses cur.
417 LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();
418 dbgs() << "in packet\n";);
419 MachineInstr &MJ = *MII;
421 dbgs() << "Checking CUR against ";
424 unsigned DestReg = MI.getOperand(0).getReg();
425 bool FoundMatch = false;
426 for (auto &MO : MJ.operands())
427 if (MO.isReg() && MO.getReg() == DestReg)
432 // Check for existing uses of a vector register within the packet which
433 // would be affected by converting a vector load into .cur formt.
434 for (auto BI : CurrentPacketMIs) {
435 LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
436 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
440 LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
441 // We can convert the opcode into a .cur.
445 // Promote an instruction to its .new form. At this time, we have already
446 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
448 bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
449 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
450 const TargetRegisterClass* RC) {
451 assert(DepType == SDep::Data);
453 if (RC == &Hexagon::PredRegsRegClass)
454 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
456 NewOpcode = HII->getDotNewOp(MI);
457 MI.setDesc(HII->get(NewOpcode));
461 bool HexagonPacketizerList::demoteToDotOld(MachineInstr &MI) {
462 int NewOpcode = HII->getDotOldOp(MI);
463 MI.setDesc(HII->get(NewOpcode));
467 bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
468 unsigned Opc = MI.getOpcode();
470 case Hexagon::S2_storerd_io:
471 case Hexagon::S2_storeri_io:
472 case Hexagon::S2_storerh_io:
473 case Hexagon::S2_storerb_io:
476 llvm_unreachable("Unexpected instruction");
478 unsigned FrameSize = MF.getFrameInfo().getStackSize();
479 MachineOperand &Off = MI.getOperand(1);
480 int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
481 if (HII->isValidOffset(Opc, NewOff, HRI)) {
488 void HexagonPacketizerList::useCalleesSP(MachineInstr &MI) {
489 unsigned Opc = MI.getOpcode();
491 case Hexagon::S2_storerd_io:
492 case Hexagon::S2_storeri_io:
493 case Hexagon::S2_storerh_io:
494 case Hexagon::S2_storerb_io:
497 llvm_unreachable("Unexpected instruction");
499 unsigned FrameSize = MF.getFrameInfo().getStackSize();
500 MachineOperand &Off = MI.getOperand(1);
501 Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
504 /// Return true if we can update the offset in MI so that MI and MJ
505 /// can be packetized together.
506 bool HexagonPacketizerList::updateOffset(SUnit *SUI, SUnit *SUJ) {
507 assert(SUI->getInstr() && SUJ->getInstr());
508 MachineInstr &MI = *SUI->getInstr();
509 MachineInstr &MJ = *SUJ->getInstr();
512 if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
515 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
517 unsigned Reg = MI.getOperand(BPI).getReg();
518 if (Reg != MJ.getOperand(BPJ).getReg())
520 // Make sure that the dependences do not restrict adding MI to the packet.
521 // That is, ignore anti dependences, and make sure the only data dependence
522 // involves the specific register.
523 for (const auto &PI : SUI->Preds)
524 if (PI.getKind() != SDep::Anti &&
525 (PI.getKind() != SDep::Data || PI.getReg() != Reg))
528 if (!HII->getIncrementValue(MJ, Incr))
531 int64_t Offset = MI.getOperand(OPI).getImm();
532 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
535 MI.getOperand(OPI).setImm(Offset + Incr);
536 ChangedOffset = Offset;
540 /// Undo the changed offset. This is needed if the instruction cannot be
541 /// added to the current packet due to a different instruction.
542 void HexagonPacketizerList::undoChangedOffset(MachineInstr &MI) {
544 if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
545 llvm_unreachable("Unable to find base and offset operands.");
546 MI.getOperand(OP).setImm(ChangedOffset);
555 /// Returns true if an instruction is predicated on p0 and false if it's
556 /// predicated on !p0.
557 static PredicateKind getPredicateSense(const MachineInstr &MI,
558 const HexagonInstrInfo *HII) {
559 if (!HII->isPredicated(MI))
561 if (HII->isPredicatedTrue(MI))
566 static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
567 const HexagonInstrInfo *HII) {
568 assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
570 // Post Increment means duplicates. Use dense map to find duplicates in the
571 // list. Caution: Densemap initializes with the minimum of 64 buckets,
572 // whereas there are at most 5 operands in the post increment.
573 DenseSet<unsigned> DefRegsSet;
574 for (auto &MO : MI.operands())
575 if (MO.isReg() && MO.isDef())
576 DefRegsSet.insert(MO.getReg());
578 for (auto &MO : MI.operands())
579 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
583 const MachineOperand &Op1 = MI.getOperand(1);
584 // The 2nd operand is always the post increment operand in load.
585 assert(Op1.isReg() && "Post increment operand has be to a register.");
588 if (MI.getDesc().mayStore()) {
589 const MachineOperand &Op0 = MI.getOperand(0);
590 // The 1st operand is always the post increment operand in store.
591 assert(Op0.isReg() && "Post increment operand has be to a register.");
595 // we should never come here.
596 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
599 // Get the value being stored.
600 static const MachineOperand& getStoreValueOperand(const MachineInstr &MI) {
601 // value being stored is always the last operand.
602 return MI.getOperand(MI.getNumOperands()-1);
605 static bool isLoadAbsSet(const MachineInstr &MI) {
606 unsigned Opc = MI.getOpcode();
608 case Hexagon::L4_loadrd_ap:
609 case Hexagon::L4_loadrb_ap:
610 case Hexagon::L4_loadrh_ap:
611 case Hexagon::L4_loadrub_ap:
612 case Hexagon::L4_loadruh_ap:
613 case Hexagon::L4_loadri_ap:
619 static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
620 assert(isLoadAbsSet(MI));
621 return MI.getOperand(1);
624 // Can be new value store?
625 // Following restrictions are to be respected in convert a store into
626 // a new value store.
627 // 1. If an instruction uses auto-increment, its address register cannot
628 // be a new-value register. Arch Spec 5.4.2.1
629 // 2. If an instruction uses absolute-set addressing mode, its address
630 // register cannot be a new-value register. Arch Spec 5.4.2.1.
631 // 3. If an instruction produces a 64-bit result, its registers cannot be used
632 // as new-value registers. Arch Spec 5.4.2.2.
633 // 4. If the instruction that sets the new-value register is conditional, then
634 // the instruction that uses the new-value register must also be conditional,
635 // and both must always have their predicates evaluate identically.
636 // Arch Spec 5.4.2.3.
637 // 5. There is an implied restriction that a packet cannot have another store,
638 // if there is a new value store in the packet. Corollary: if there is
639 // already a store in a packet, there can not be a new value store.
640 // Arch Spec: 3.4.4.2
641 bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
642 const MachineInstr &PacketMI, unsigned DepReg) {
643 // Make sure we are looking at the store, that can be promoted.
644 if (!HII->mayBeNewStore(MI))
647 // Make sure there is dependency and can be new value'd.
648 const MachineOperand &Val = getStoreValueOperand(MI);
649 if (Val.isReg() && Val.getReg() != DepReg)
652 const MCInstrDesc& MCID = PacketMI.getDesc();
654 // First operand is always the result.
655 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
656 // Double regs can not feed into new value store: PRM section: 5.4.2.2.
657 if (PacketRC == &Hexagon::DoubleRegsRegClass)
660 // New-value stores are of class NV (slot 0), dual stores require class ST
661 // in slot 0 (PRM 5.5).
662 for (auto I : CurrentPacketMIs) {
663 SUnit *PacketSU = MIToSUnit.find(I)->second;
664 if (PacketSU->getInstr()->mayStore())
668 // Make sure it's NOT the post increment register that we are going to
670 if (HII->isPostIncrement(MI) &&
671 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
675 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
676 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
677 // If source is post_inc, or absolute-set addressing, it can not feed
678 // into new value store
680 // memw(r30 + #-1404) = r2.new -> can not be new value store
681 // arch spec section: 5.4.2.1.
685 if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
688 // If the source that feeds the store is predicated, new value store must
689 // also be predicated.
690 if (HII->isPredicated(PacketMI)) {
691 if (!HII->isPredicated(MI))
694 // Check to make sure that they both will have their predicates
695 // evaluate identically.
696 unsigned predRegNumSrc = 0;
697 unsigned predRegNumDst = 0;
698 const TargetRegisterClass* predRegClass = nullptr;
700 // Get predicate register used in the source instruction.
701 for (auto &MO : PacketMI.operands()) {
704 predRegNumSrc = MO.getReg();
705 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
706 if (predRegClass == &Hexagon::PredRegsRegClass)
709 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
710 "predicate register not found in a predicated PacketMI instruction");
712 // Get predicate register used in new-value store instruction.
713 for (auto &MO : MI.operands()) {
716 predRegNumDst = MO.getReg();
717 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
718 if (predRegClass == &Hexagon::PredRegsRegClass)
721 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
722 "predicate register not found in a predicated MI instruction");
724 // New-value register producer and user (store) need to satisfy these
726 // 1) Both instructions should be predicated on the same register.
727 // 2) If producer of the new-value register is .new predicated then store
728 // should also be .new predicated and if producer is not .new predicated
729 // then store should not be .new predicated.
730 // 3) Both new-value register producer and user should have same predicate
731 // sense, i.e, either both should be negated or both should be non-negated.
732 if (predRegNumDst != predRegNumSrc ||
733 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
734 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
738 // Make sure that other than the new-value register no other store instruction
739 // register has been modified in the same packet. Predicate registers can be
740 // modified by they should not be modified between the producer and the store
741 // instruction as it will make them both conditional on different values.
742 // We already know this to be true for all the instructions before and
743 // including PacketMI. Howerver, we need to perform the check for the
744 // remaining instructions in the packet.
746 unsigned StartCheck = 0;
748 for (auto I : CurrentPacketMIs) {
749 SUnit *TempSU = MIToSUnit.find(I)->second;
750 MachineInstr &TempMI = *TempSU->getInstr();
752 // Following condition is true for all the instructions until PacketMI is
753 // reached (StartCheck is set to 0 before the for loop).
754 // StartCheck flag is 1 for all the instructions after PacketMI.
755 if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
756 continue; // encountering PacketMI.
759 if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
762 for (auto &MO : MI.operands())
763 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
767 // Make sure that for non-POST_INC stores:
768 // 1. The only use of reg is DepReg and no other registers.
769 // This handles V4 base+index registers.
770 // The following store can not be dot new.
771 // Eg. r0 = add(r0, #3)
772 // memw(r1+r0<<#2) = r0
773 if (!HII->isPostIncrement(MI)) {
774 for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
775 const MachineOperand &MO = MI.getOperand(opNum);
776 if (MO.isReg() && MO.getReg() == DepReg)
781 // If data definition is because of implicit definition of the register,
782 // do not newify the store. Eg.
783 // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
784 // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
785 for (auto &MO : PacketMI.operands()) {
786 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
788 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
790 unsigned R = MO.getReg();
791 if (R == DepReg || HRI->isSuperRegister(DepReg, R))
795 // Handle imp-use of super reg case. There is a target independent side
796 // change that should prevent this situation but I am handling it for
797 // just-in-case. For example, we cannot newify R2 in the following case:
799 // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
800 for (auto &MO : MI.operands()) {
801 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
805 // Can be dot new store.
809 // Can this MI to promoted to either new value store or new value jump.
810 bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr &MI,
811 const SUnit *PacketSU, unsigned DepReg,
812 MachineBasicBlock::iterator &MII) {
813 if (!HII->mayBeNewStore(MI))
816 // Check to see the store can be new value'ed.
817 MachineInstr &PacketMI = *PacketSU->getInstr();
818 if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
821 // Check to see the compare/jump can be new value'ed.
822 // This is done as a pass on its own. Don't need to check it here.
826 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
828 for (auto &MO : I.operands()) {
829 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
831 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
833 if (CheckDef == MO.isDef())
839 // Check to see if an instruction can be dot new
840 // There are three kinds.
841 // 1. dot new on predicate - V2/V3/V4
842 // 2. dot new on stores NV/ST - V4
843 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
844 bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
845 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
846 const TargetRegisterClass* RC) {
847 // Already a dot new instruction.
848 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
851 if (!isNewifiable(MI, RC))
854 const MachineInstr &PI = *PacketSU->getInstr();
856 // The "new value" cannot come from inline asm.
857 if (PI.isInlineAsm())
860 // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
862 if (PI.isImplicitDef())
865 // If dependency is trough an implicitly defined register, we should not
867 if (isImplicitDependency(PI, true, DepReg) ||
868 isImplicitDependency(MI, false, DepReg))
871 const MCInstrDesc& MCID = PI.getDesc();
872 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
873 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
877 if (RC == &Hexagon::PredRegsRegClass)
878 return HII->predCanBeUsedAsDotNew(PI, DepReg);
880 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
883 // Create a dot new machine instruction to see if resources can be
884 // allocated. If not, bail out now.
885 int NewOpcode = HII->getDotNewOp(MI);
886 const MCInstrDesc &D = HII->get(NewOpcode);
887 MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
888 bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
889 MF.DeleteMachineInstr(NewMI);
890 if (!ResourcesAvailable)
893 // New Value Store only. New Value Jump generated as a separate pass.
894 if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
900 // Go through the packet instructions and search for an anti dependency between
901 // them and DepReg from MI. Consider this case:
903 // a) %r1 = TFRI_cdNotPt %p3, 2
906 // b) %p0 = C2_or killed %p3, killed %p0
907 // c) %p3 = C2_tfrrp %r23
908 // d) %r1 = C2_cmovenewit %p3, 4
910 // The P3 from a) and d) will be complements after
911 // a)'s P3 is converted to .new form
912 // Anti-dep between c) and b) is irrelevant for this case
913 bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
915 SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
917 for (auto I : CurrentPacketMIs) {
918 // We only care for dependencies to predicated instructions
919 if (!HII->isPredicated(*I))
922 // Scheduling Unit for current insn in the packet
923 SUnit *PacketSU = MIToSUnit.find(I)->second;
925 // Look at dependencies between current members of the packet and
926 // predicate defining instruction MI. Make sure that dependency is
927 // on the exact register we care about.
928 if (PacketSU->isSucc(PacketSUDep)) {
929 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
930 auto &Dep = PacketSU->Succs[i];
931 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
932 Dep.getReg() == DepReg)
941 /// Gets the predicate register of a predicated instruction.
942 static unsigned getPredicatedRegister(MachineInstr &MI,
943 const HexagonInstrInfo *QII) {
944 /// We use the following rule: The first predicate register that is a use is
945 /// the predicate register of a predicated instruction.
946 assert(QII->isPredicated(MI) && "Must be predicated instruction");
948 for (auto &Op : MI.operands()) {
949 if (Op.isReg() && Op.getReg() && Op.isUse() &&
950 Hexagon::PredRegsRegClass.contains(Op.getReg()))
954 llvm_unreachable("Unknown instruction operand layout");
958 // Given two predicated instructions, this function detects whether
959 // the predicates are complements.
960 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
962 // If we don't know the predicate sense of the instructions bail out early, we
964 if (getPredicateSense(MI1, HII) == PK_Unknown ||
965 getPredicateSense(MI2, HII) == PK_Unknown)
968 // Scheduling unit for candidate.
969 SUnit *SU = MIToSUnit[&MI1];
971 // One corner case deals with the following scenario:
973 // a) %r24 = A2_tfrt %p0, %r25
976 // b) %r25 = A2_tfrf %p0, %r24
977 // c) %p0 = C2_cmpeqi %r26, 1
980 // On general check a) and b) are complements, but presence of c) will
981 // convert a) to .new form, and then it is not a complement.
982 // We attempt to detect it by analyzing existing dependencies in the packet.
984 // Analyze relationships between all existing members of the packet.
985 // Look for Anti dependecy on the same predicate reg as used in the
987 for (auto I : CurrentPacketMIs) {
988 // Scheduling Unit for current insn in the packet.
989 SUnit *PacketSU = MIToSUnit.find(I)->second;
991 // If this instruction in the packet is succeeded by the candidate...
992 if (PacketSU->isSucc(SU)) {
993 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
994 auto Dep = PacketSU->Succs[i];
995 // The corner case exist when there is true data dependency between
996 // candidate and one of current packet members, this dep is on
997 // predicate reg, and there already exist anti dep on the same pred in
999 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
1000 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
1001 // Here I know that I is predicate setting instruction with true
1002 // data dep to candidate on the register we care about - c) in the
1003 // above example. Now I need to see if there is an anti dependency
1004 // from c) to any other instruction in the same packet on the pred
1006 if (restrictingDepExistInPacket(*I, Dep.getReg()))
1013 // If the above case does not apply, check regular complement condition.
1014 // Check that the predicate register is the same and that the predicate
1015 // sense is different We also need to differentiate .old vs. .new: !p0
1016 // is not complementary to p0.new.
1017 unsigned PReg1 = getPredicatedRegister(MI1, HII);
1018 unsigned PReg2 = getPredicatedRegister(MI2, HII);
1019 return PReg1 == PReg2 &&
1020 Hexagon::PredRegsRegClass.contains(PReg1) &&
1021 Hexagon::PredRegsRegClass.contains(PReg2) &&
1022 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1023 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1026 // Initialize packetizer flags.
1027 void HexagonPacketizerList::initPacketizerState() {
1029 PromotedToDotNew = false;
1030 GlueToNewValueJump = false;
1031 GlueAllocframeStore = false;
1032 FoundSequentialDependence = false;
1033 ChangedOffset = INT64_MAX;
1036 // Ignore bundling of pseudo instructions.
1037 bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
1038 const MachineBasicBlock *) {
1039 if (MI.isDebugInstr())
1042 if (MI.isCFIInstruction())
1045 // We must print out inline assembly.
1046 if (MI.isInlineAsm())
1049 if (MI.isImplicitDef())
1052 // We check if MI has any functional units mapped to it. If it doesn't,
1053 // we ignore the instruction.
1054 const MCInstrDesc& TID = MI.getDesc();
1055 auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1056 unsigned FuncUnits = IS->getUnits();
1060 bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) {
1061 // Ensure any bundles created by gather packetize remain seperate.
1065 if (MI.isEHLabel() || MI.isCFIInstruction())
1068 // Consider inline asm to not be a solo instruction by default.
1069 // Inline asm will be put in a packet temporarily, but then it will be
1070 // removed, and placed outside of the packet (before or after, depending
1071 // on dependencies). This is to reduce the impact of inline asm as a
1072 // "packet splitting" instruction.
1073 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1076 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1077 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
1078 // They must not be grouped with other instructions in a packet.
1079 if (isSchedBarrier(MI))
1082 if (HII->isSolo(MI))
1085 if (MI.getOpcode() == Hexagon::A2_nop)
1091 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1092 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1093 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1094 // For full test call this function twice:
1095 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1096 // Doing the test only one way saves the amount of code in this function,
1097 // since every test would need to be repeated with the MI and MJ reversed.
1098 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1099 const HexagonInstrInfo &HII) {
1100 const MachineFunction *MF = MI.getParent()->getParent();
1101 if (MF->getSubtarget<HexagonSubtarget>().hasV60OpsOnly() &&
1102 HII.isHVXMemWithAIndirect(MI, MJ))
1105 // An inline asm cannot be together with a branch, because we may not be
1106 // able to remove the asm out after packetizing (i.e. if the asm must be
1107 // moved past the bundle). Similarly, two asms cannot be together to avoid
1108 // complications when determining their relative order outside of a bundle.
1109 if (MI.isInlineAsm())
1110 return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1111 MJ.isCall() || MJ.isTerminator();
1113 switch (MI.getOpcode()) {
1114 case Hexagon::S2_storew_locked:
1115 case Hexagon::S4_stored_locked:
1116 case Hexagon::L2_loadw_locked:
1117 case Hexagon::L4_loadd_locked:
1118 case Hexagon::Y2_dccleana:
1119 case Hexagon::Y2_dccleaninva:
1120 case Hexagon::Y2_dcinva:
1121 case Hexagon::Y2_dczeroa:
1122 case Hexagon::Y4_l2fetch:
1123 case Hexagon::Y5_l2fetch: {
1124 // These instructions can only be grouped with ALU32 or non-floating-point
1125 // XTYPE instructions. Since there is no convenient way of identifying fp
1126 // XTYPE instructions, only allow grouping with ALU32 for now.
1127 unsigned TJ = HII.getType(MJ);
1128 if (TJ != HexagonII::TypeALU32_2op &&
1129 TJ != HexagonII::TypeALU32_3op &&
1130 TJ != HexagonII::TypeALU32_ADDI)
1138 // "False" really means that the quick check failed to determine if
1139 // I and J cannot coexist.
1143 // Full, symmetric check.
1144 bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI,
1145 const MachineInstr &MJ) {
1146 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1149 void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) {
1150 for (auto &B : MF) {
1151 MachineBasicBlock::iterator BundleIt;
1152 MachineBasicBlock::instr_iterator NextI;
1153 for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1154 NextI = std::next(I);
1155 MachineInstr &MI = *I;
1158 if (!MI.isInsideBundle())
1161 // Decide on where to insert the instruction that we are pulling out.
1162 // Debug instructions always go before the bundle, but the placement of
1163 // INLINE_ASM depends on potential dependencies. By default, try to
1164 // put it before the bundle, but if the asm writes to a register that
1165 // other instructions in the bundle read, then we need to place it
1166 // after the bundle (to preserve the bundle semantics).
1167 bool InsertBeforeBundle;
1168 if (MI.isInlineAsm())
1169 InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1170 else if (MI.isDebugValue())
1171 InsertBeforeBundle = true;
1175 BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1180 // Check if a given instruction is of class "system".
1181 static bool isSystemInstr(const MachineInstr &MI) {
1182 unsigned Opc = MI.getOpcode();
1184 case Hexagon::Y2_barrier:
1185 case Hexagon::Y2_dcfetchbo:
1186 case Hexagon::Y4_l2fetch:
1187 case Hexagon::Y5_l2fetch:
1193 bool HexagonPacketizerList::hasDeadDependence(const MachineInstr &I,
1194 const MachineInstr &J) {
1195 // The dependence graph may not include edges between dead definitions,
1196 // so without extra checks, we could end up packetizing two instruction
1197 // defining the same (dead) register.
1198 if (I.isCall() || J.isCall())
1200 if (HII->isPredicated(I) || HII->isPredicated(J))
1203 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1204 for (auto &MO : I.operands()) {
1205 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1207 DeadDefs[MO.getReg()] = true;
1210 for (auto &MO : J.operands()) {
1211 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1213 unsigned R = MO.getReg();
1214 if (R != Hexagon::USR_OVF && DeadDefs[R])
1220 bool HexagonPacketizerList::hasControlDependence(const MachineInstr &I,
1221 const MachineInstr &J) {
1222 // A save callee-save register function call can only be in a packet
1223 // with instructions that don't write to the callee-save registers.
1224 if ((HII->isSaveCalleeSavedRegsCall(I) &&
1225 doesModifyCalleeSavedReg(J, HRI)) ||
1226 (HII->isSaveCalleeSavedRegsCall(J) &&
1227 doesModifyCalleeSavedReg(I, HRI)))
1230 // Two control flow instructions cannot go in the same packet.
1231 if (isControlFlow(I) && isControlFlow(J))
1234 // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1235 // contain a speculative indirect jump,
1236 // a new-value compare jump or a dealloc_return.
1237 auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1238 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1240 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1245 if (HII->isLoopN(I) && isBadForLoopN(J))
1247 if (HII->isLoopN(J) && isBadForLoopN(I))
1250 // dealloc_return cannot appear in the same packet as a conditional or
1251 // unconditional jump.
1252 return HII->isDeallocRet(I) &&
1253 (J.isBranch() || J.isCall() || J.isBarrier());
1256 bool HexagonPacketizerList::hasRegMaskDependence(const MachineInstr &I,
1257 const MachineInstr &J) {
1258 // Adding I to a packet that has J.
1260 // Regmasks are not reflected in the scheduling dependency graph, so
1261 // we need to check them manually. This code assumes that regmasks only
1262 // occur on calls, and the problematic case is when we add an instruction
1263 // defining a register R to a packet that has a call that clobbers R via
1264 // a regmask. Those cannot be packetized together, because the call will
1265 // be executed last. That's also a reson why it is ok to add a call
1266 // clobbering R to a packet that defines R.
1268 // Look for regmasks in J.
1269 for (const MachineOperand &OpJ : J.operands()) {
1270 if (!OpJ.isRegMask())
1272 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1273 for (const MachineOperand &OpI : I.operands()) {
1275 if (OpJ.clobbersPhysReg(OpI.getReg()))
1277 } else if (OpI.isRegMask()) {
1278 // Both are regmasks. Assume that they intersect.
1286 bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I,
1287 const MachineInstr &J) {
1288 bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1289 bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1290 if ((SysI && StoreJ) || (SysJ && StoreI))
1293 if (StoreI && StoreJ) {
1294 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1297 // A memop cannot be in the same packet with another memop or a store.
1298 // Two stores can be together, but here I and J cannot both be stores.
1299 bool MopStI = HII->isMemOp(I) || StoreI;
1300 bool MopStJ = HII->isMemOp(J) || StoreJ;
1301 if (MopStI && MopStJ)
1305 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1308 // SUI is the current instruction that is out side of the current packet.
1309 // SUJ is the current instruction inside the current packet against which that
1310 // SUI will be packetized.
1311 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
1312 assert(SUI->getInstr() && SUJ->getInstr());
1313 MachineInstr &I = *SUI->getInstr();
1314 MachineInstr &J = *SUJ->getInstr();
1316 // Clear IgnoreDepMIs when Packet starts.
1317 if (CurrentPacketMIs.size() == 1)
1318 IgnoreDepMIs.clear();
1320 MachineBasicBlock::iterator II = I.getIterator();
1322 // Solo instructions cannot go in the packet.
1323 assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1325 if (cannotCoexist(I, J))
1328 Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
1332 // Regmasks are not accounted for in the scheduling graph, so we need
1333 // to explicitly check for dependencies caused by them. They should only
1334 // appear on calls, so it's not too pessimistic to reject all regmask
1336 Dependence = hasRegMaskDependence(I, J);
1340 // V4 allows dual stores. It does not allow second store, if the first
1341 // store is not in SLOT0. New value store, new value jump, dealloc_return
1342 // and memop always take SLOT0. Arch spec 3.4.4.2.
1343 Dependence = hasV4SpecificDependence(I, J);
1347 // If an instruction feeds new value jump, glue it.
1348 MachineBasicBlock::iterator NextMII = I.getIterator();
1350 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1351 MachineInstr &NextMI = *NextMII;
1353 bool secondRegMatch = false;
1354 const MachineOperand &NOp0 = NextMI.getOperand(0);
1355 const MachineOperand &NOp1 = NextMI.getOperand(1);
1357 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1358 secondRegMatch = true;
1360 for (MachineInstr *PI : CurrentPacketMIs) {
1361 // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1367 // 1. Packet does not have a store in it.
1368 // 2. If the first operand of the nvj is newified, and the second
1369 // operand is also a reg, it (second reg) is not defined in
1371 // 3. If the second operand of the nvj is newified, (which means
1372 // first operand is also a reg), first reg is not defined in
1374 if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1375 HII->isLoopN(*PI)) {
1380 const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1381 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1387 GlueToNewValueJump = true;
1392 // There no dependency between a prolog instruction and its successor.
1393 if (!SUJ->isSucc(SUI))
1396 for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1397 if (FoundSequentialDependence)
1400 if (SUJ->Succs[i].getSUnit() != SUI)
1403 SDep::Kind DepType = SUJ->Succs[i].getKind();
1404 // For direct calls:
1405 // Ignore register dependences for call instructions for packetization
1406 // purposes except for those due to r31 and predicate registers.
1408 // For indirect calls:
1409 // Same as direct calls + check for true dependences to the register
1410 // used in the indirect call.
1412 // We completely ignore Order dependences for call instructions.
1415 // Ignore register dependences for return instructions like jumpr,
1416 // dealloc return unless we have dependencies on the explicit uses
1417 // of the registers used by jumpr (like r31) or dealloc return
1418 // (like r29 or r30).
1419 unsigned DepReg = 0;
1420 const TargetRegisterClass *RC = nullptr;
1421 if (DepType == SDep::Data) {
1422 DepReg = SUJ->Succs[i].getReg();
1423 RC = HRI->getMinimalPhysRegClass(DepReg);
1426 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1427 if (!isRegDependence(DepType))
1429 if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1433 if (DepType == SDep::Data) {
1434 if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1435 if (promoteToDotCur(J, DepType, II, RC))
1439 // Data dpendence ok if we have load.cur.
1440 if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1441 if (HII->isHVXVec(I))
1445 // For instructions that can be promoted to dot-new, try to promote.
1446 if (DepType == SDep::Data) {
1447 if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1448 if (promoteToDotNew(I, DepType, II, RC)) {
1449 PromotedToDotNew = true;
1450 if (cannotCoexist(I, J))
1451 FoundSequentialDependence = true;
1455 if (HII->isNewValueJump(I))
1459 // For predicated instructions, if the predicates are complements then
1460 // there can be no dependence.
1461 if (HII->isPredicated(I) && HII->isPredicated(J) &&
1462 arePredicatesComplements(I, J)) {
1463 // Not always safe to do this translation.
1464 // DAG Builder attempts to reduce dependence edges using transitive
1465 // nature of dependencies. Here is an example:
1467 // r0 = tfr_pt ... (1)
1468 // r0 = tfr_pf ... (2)
1469 // r0 = tfr_pt ... (3)
1471 // There will be an output dependence between (1)->(2) and (2)->(3).
1472 // However, there is no dependence edge between (1)->(3). This results
1473 // in all 3 instructions going in the same packet. We ignore dependce
1474 // only once to avoid this situation.
1475 auto Itr = find(IgnoreDepMIs, &J);
1476 if (Itr != IgnoreDepMIs.end()) {
1480 IgnoreDepMIs.push_back(&I);
1484 // Ignore Order dependences between unconditional direct branches
1485 // and non-control-flow instructions.
1486 if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1487 DepType == SDep::Order)
1490 // Ignore all dependences for jumps except for true and output
1492 if (I.isConditionalBranch() && DepType != SDep::Data &&
1493 DepType != SDep::Output)
1496 if (DepType == SDep::Output) {
1497 FoundSequentialDependence = true;
1501 // For Order dependences:
1502 // 1. On V4 or later, volatile loads/stores can be packetized together,
1503 // unless other rules prevent is.
1504 // 2. Store followed by a load is not allowed.
1505 // 3. Store followed by a store is only valid on V4 or later.
1506 // 4. Load followed by any memory operation is allowed.
1507 if (DepType == SDep::Order) {
1508 if (!PacketizeVolatiles) {
1509 bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1511 FoundSequentialDependence = true;
1515 // J is first, I is second.
1516 bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1517 bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1518 bool NVStoreJ = HII->isNewValueStore(J);
1519 bool NVStoreI = HII->isNewValueStore(I);
1520 bool IsVecJ = HII->isHVXVec(J);
1521 bool IsVecI = HII->isHVXVec(I);
1523 if (Slot1Store && MF.getSubtarget<HexagonSubtarget>().hasV65Ops() &&
1524 ((LoadJ && StoreI && !NVStoreI) ||
1525 (StoreJ && LoadI && !NVStoreJ)) &&
1526 (J.getOpcode() != Hexagon::S2_allocframe &&
1527 I.getOpcode() != Hexagon::S2_allocframe) &&
1528 (J.getOpcode() != Hexagon::L2_deallocframe &&
1529 I.getOpcode() != Hexagon::L2_deallocframe) &&
1530 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1531 setmemShufDisabled(true);
1533 if (StoreJ && LoadI && alias(J, I)) {
1534 FoundSequentialDependence = true;
1539 if (!LoadJ || (!LoadI && !StoreI)) {
1540 // If J is neither load nor store, assume a dependency.
1541 // If J is a load, but I is neither, also assume a dependency.
1542 FoundSequentialDependence = true;
1545 // Store followed by store: not OK on V2.
1546 // Store followed by load: not OK on all.
1547 // Load followed by store: OK on all.
1548 // Load followed by load: OK on all.
1552 // For V4, special case ALLOCFRAME. Even though there is dependency
1553 // between ALLOCFRAME and subsequent store, allow it to be packetized
1554 // in a same packet. This implies that the store is using the caller's
1555 // SP. Hence, offset needs to be updated accordingly.
1556 if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1557 unsigned Opc = I.getOpcode();
1559 case Hexagon::S2_storerd_io:
1560 case Hexagon::S2_storeri_io:
1561 case Hexagon::S2_storerh_io:
1562 case Hexagon::S2_storerb_io:
1563 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1564 // Since this store is to be glued with allocframe in the same
1565 // packet, it will use SP of the previous stack frame, i.e.
1566 // caller's SP. Therefore, we need to recalculate offset
1567 // according to this change.
1568 GlueAllocframeStore = useCallersSP(I);
1569 if (GlueAllocframeStore)
1577 // There are certain anti-dependencies that cannot be ignored.
1579 // J2_call ... implicit-def %r0 ; SUJ
1581 // Those cannot be packetized together, since the call will observe
1582 // the effect of the assignment to R0.
1583 if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1584 // Check if I defines any volatile register. We should also check
1585 // registers that the call may read, but these happen to be a
1586 // subset of the volatile register set.
1587 for (const MachineOperand &Op : I.operands()) {
1588 if (Op.isReg() && Op.isDef()) {
1589 unsigned R = Op.getReg();
1590 if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1592 } else if (!Op.isRegMask()) {
1593 // If I has a regmask assume dependency.
1596 FoundSequentialDependence = true;
1601 // Skip over remaining anti-dependences. Two instructions that are
1602 // anti-dependent can share a packet, since in most such cases all
1603 // operands are read before any modifications take place.
1604 // The exceptions are branch and call instructions, since they are
1605 // executed after all other instructions have completed (at least
1607 if (DepType != SDep::Anti) {
1608 FoundSequentialDependence = true;
1613 if (FoundSequentialDependence) {
1621 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1622 assert(SUI->getInstr() && SUJ->getInstr());
1623 MachineInstr &I = *SUI->getInstr();
1624 MachineInstr &J = *SUJ->getInstr();
1626 bool Coexist = !cannotCoexist(I, J);
1628 if (Coexist && !Dependence)
1631 // Check if the instruction was promoted to a dot-new. If so, demote it
1632 // back into a dot-old.
1633 if (PromotedToDotNew)
1637 // Check if the instruction (must be a store) was glued with an allocframe
1638 // instruction. If so, restore its offset to its original value, i.e. use
1639 // current SP instead of caller's SP.
1640 if (GlueAllocframeStore) {
1642 GlueAllocframeStore = false;
1645 if (ChangedOffset != INT64_MAX)
1646 undoChangedOffset(I);
1648 if (GlueToNewValueJump) {
1649 // Putting I and J together would prevent the new-value jump from being
1650 // packetized with the producer. In that case I and J must be separated.
1651 GlueToNewValueJump = false;
1655 if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
1656 FoundSequentialDependence = false;
1665 bool HexagonPacketizerList::foundLSInPacket() {
1666 bool FoundLoad = false;
1667 bool FoundStore = false;
1669 for (auto MJ : CurrentPacketMIs) {
1670 unsigned Opc = MJ->getOpcode();
1671 if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
1673 if (HII->isMemOp(*MJ))
1677 if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1680 return FoundLoad && FoundStore;
1684 MachineBasicBlock::iterator
1685 HexagonPacketizerList::addToPacket(MachineInstr &MI) {
1686 MachineBasicBlock::iterator MII = MI.getIterator();
1687 MachineBasicBlock *MBB = MI.getParent();
1689 if (CurrentPacketMIs.empty())
1690 PacketStalls = false;
1691 PacketStalls |= producesStall(MI);
1693 if (MI.isImplicitDef()) {
1694 // Add to the packet to allow subsequent instructions to be checked
1696 CurrentPacketMIs.push_back(&MI);
1699 assert(ResourceTracker->canReserveResources(MI));
1701 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1704 if (GlueToNewValueJump) {
1705 MachineInstr &NvjMI = *++MII;
1706 // We need to put both instructions in the same packet: MI and NvjMI.
1707 // Either of them can require a constant extender. Try to add both to
1708 // the current packet, and if that fails, end the packet and start a
1710 ResourceTracker->reserveResources(MI);
1712 Good = tryAllocateResourcesForConstExt(true);
1714 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1716 if (ResourceTracker->canReserveResources(NvjMI))
1717 ResourceTracker->reserveResources(NvjMI);
1721 if (Good && ExtNvjMI)
1722 Good = tryAllocateResourcesForConstExt(true);
1726 assert(ResourceTracker->canReserveResources(MI));
1727 ResourceTracker->reserveResources(MI);
1729 assert(canReserveResourcesForConstExt());
1730 tryAllocateResourcesForConstExt(true);
1732 assert(ResourceTracker->canReserveResources(NvjMI));
1733 ResourceTracker->reserveResources(NvjMI);
1735 assert(canReserveResourcesForConstExt());
1736 reserveResourcesForConstExt();
1739 CurrentPacketMIs.push_back(&MI);
1740 CurrentPacketMIs.push_back(&NvjMI);
1744 ResourceTracker->reserveResources(MI);
1745 if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1747 if (PromotedToDotNew)
1749 if (GlueAllocframeStore) {
1751 GlueAllocframeStore = false;
1753 ResourceTracker->reserveResources(MI);
1754 reserveResourcesForConstExt();
1757 CurrentPacketMIs.push_back(&MI);
1761 void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB,
1762 MachineBasicBlock::iterator MI) {
1763 // Replace VLIWPacketizerList::endPacket(MBB, MI).
1765 bool memShufDisabled = getmemShufDisabled();
1766 if (memShufDisabled && !foundLSInPacket()) {
1767 setmemShufDisabled(false);
1768 LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");
1770 memShufDisabled = getmemShufDisabled();
1772 if (CurrentPacketMIs.size() > 1) {
1773 MachineBasicBlock::instr_iterator FirstMI(CurrentPacketMIs.front());
1774 MachineBasicBlock::instr_iterator LastMI(MI.getInstrIterator());
1775 finalizeBundle(*MBB, FirstMI, LastMI);
1777 auto BundleMII = std::prev(FirstMI);
1778 if (memShufDisabled)
1779 HII->setBundleNoShuf(BundleMII);
1781 setmemShufDisabled(false);
1783 OldPacketMIs = CurrentPacketMIs;
1784 CurrentPacketMIs.clear();
1786 ResourceTracker->clearResources();
1787 LLVM_DEBUG(dbgs() << "End packet\n");
1790 bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
1791 return !producesStall(MI);
1794 // V60 forward scheduling.
1795 bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
1796 // If the packet already stalls, then ignore the stall from a subsequent
1797 // instruction in the same packet.
1801 // Check whether the previous packet is in a different loop. If this is the
1802 // case, there is little point in trying to avoid a stall because that would
1803 // favor the rare case (loop entry) over the common case (loop iteration).
1805 // TODO: We should really be able to check all the incoming edges if this is
1806 // the first packet in a basic block, so we can avoid stalls from the loop
1808 if (!OldPacketMIs.empty()) {
1809 auto *OldBB = OldPacketMIs.front()->getParent();
1810 auto *ThisBB = I.getParent();
1811 if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1815 SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1817 // If the latency is 0 and there is a data dependence between this
1818 // instruction and any instruction in the current packet, we disregard any
1819 // potential stalls due to the instructions in the previous packet. Most of
1820 // the instruction pairs that can go together in the same packet have 0
1821 // latency between them. The exceptions are
1822 // 1. NewValueJumps as they're generated much later and the latencies can't
1823 // be changed at that point.
1824 // 2. .cur instructions, if its consumer has a 0 latency successor (such as
1825 // .new). In this case, the latency between .cur and the consumer stays
1826 // non-zero even though we can have both .cur and .new in the same packet.
1827 // Changing the latency to 0 is not an option as it causes software pipeliner
1828 // to not pipeline in some cases.
1832 // I1: v6.cur = vmem(r0++#1)
1833 // I2: v7 = valign(v6,v4,r2)
1834 // I3: vmem(r5++#1) = v7.new
1836 // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1838 for (auto J : CurrentPacketMIs) {
1839 SUnit *SUJ = MIToSUnit[J];
1840 for (auto &Pred : SUI->Preds)
1841 if (Pred.getSUnit() == SUJ)
1842 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
1843 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1847 // Check if the latency is greater than one between this instruction and any
1848 // instruction in the previous packet.
1849 for (auto J : OldPacketMIs) {
1850 SUnit *SUJ = MIToSUnit[J];
1851 for (auto &Pred : SUI->Preds)
1852 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1859 //===----------------------------------------------------------------------===//
1860 // Public Constructor Functions
1861 //===----------------------------------------------------------------------===//
1863 FunctionPass *llvm::createHexagonPacketizer() {
1864 return new HexagonPacketizer();