1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #include "HexagonVLIWPacketizer.h"
20 #include "HexagonRegisterInfo.h"
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
34 #define DEBUG_TYPE "packets"
36 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
37 cl::ZeroOrMore, cl::init(false),
38 cl::desc("Disable Hexagon packetizer pass"));
40 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
41 cl::ZeroOrMore, cl::Hidden, cl::init(true),
42 cl::desc("Allow non-solo packetization of volatile memory references"));
44 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
45 cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
47 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
48 cl::init(false), cl::Hidden, cl::ZeroOrMore,
49 cl::desc("Disable vector double new-value-stores"));
51 extern cl::opt<bool> ScheduleInlineAsm;
54 FunctionPass *createHexagonPacketizer();
55 void initializeHexagonPacketizerPass(PassRegistry&);
60 class HexagonPacketizer : public MachineFunctionPass {
63 HexagonPacketizer() : MachineFunctionPass(ID) {}
65 void getAnalysisUsage(AnalysisUsage &AU) const override {
67 AU.addRequired<AAResultsWrapperPass>();
68 AU.addRequired<MachineBranchProbabilityInfo>();
69 AU.addRequired<MachineDominatorTree>();
70 AU.addRequired<MachineLoopInfo>();
71 AU.addPreserved<MachineDominatorTree>();
72 AU.addPreserved<MachineLoopInfo>();
73 MachineFunctionPass::getAnalysisUsage(AU);
75 StringRef getPassName() const override { return "Hexagon Packetizer"; }
76 bool runOnMachineFunction(MachineFunction &Fn) override;
77 MachineFunctionProperties getRequiredProperties() const override {
78 return MachineFunctionProperties().set(
79 MachineFunctionProperties::Property::NoVRegs);
83 const HexagonInstrInfo *HII;
84 const HexagonRegisterInfo *HRI;
87 char HexagonPacketizer::ID = 0;
90 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
91 "Hexagon Packetizer", false, false)
92 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
93 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
94 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
95 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
96 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
97 "Hexagon Packetizer", false, false)
99 HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
100 MachineLoopInfo &MLI, AliasAnalysis *AA,
101 const MachineBranchProbabilityInfo *MBPI)
102 : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI) {
103 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
104 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
106 addMutation(make_unique<HexagonSubtarget::HexagonDAGMutation>());
109 // Check if FirstI modifies a register that SecondI reads.
110 static bool hasWriteToReadDep(const MachineInstr &FirstI,
111 const MachineInstr &SecondI,
112 const TargetRegisterInfo *TRI) {
113 for (auto &MO : FirstI.operands()) {
114 if (!MO.isReg() || !MO.isDef())
116 unsigned R = MO.getReg();
117 if (SecondI.readsRegister(R, TRI))
124 static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
125 MachineBasicBlock::iterator BundleIt, bool Before) {
126 MachineBasicBlock::instr_iterator InsertPt;
128 InsertPt = BundleIt.getInstrIterator();
130 InsertPt = std::next(BundleIt).getInstrIterator();
132 MachineBasicBlock &B = *MI.getParent();
133 // The instruction should at least be bundled with the preceding instruction
134 // (there will always be one, i.e. BUNDLE, if nothing else).
135 assert(MI.isBundledWithPred());
136 if (MI.isBundledWithSucc()) {
137 MI.clearFlag(MachineInstr::BundledSucc);
138 MI.clearFlag(MachineInstr::BundledPred);
140 // If it's not bundled with the successor (i.e. it is the last one
141 // in the bundle), then we can simply unbundle it from the predecessor,
142 // which will take care of updating the predecessor's flag.
143 MI.unbundleFromPred();
145 B.splice(InsertPt, &B, MI.getIterator());
147 // Get the size of the bundle without asserting.
148 MachineBasicBlock::const_instr_iterator I = BundleIt.getInstrIterator();
149 MachineBasicBlock::const_instr_iterator E = B.instr_end();
151 for (++I; I != E && I->isBundledWithPred(); ++I)
154 // If there are still two or more instructions, then there is nothing
159 // Otherwise, extract the single instruction out and delete the bundle.
160 MachineBasicBlock::iterator NextIt = std::next(BundleIt);
161 MachineInstr &SingleI = *BundleIt->getNextNode();
162 SingleI.unbundleFromPred();
163 assert(!SingleI.isBundledWithSucc());
164 BundleIt->eraseFromParent();
169 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
170 if (DisablePacketizer || skipFunction(*MF.getFunction()))
173 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
174 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
175 auto &MLI = getAnalysis<MachineLoopInfo>();
176 auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
177 auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
179 if (EnableGenAllInsnClass)
180 HII->genAllInsnTimingClasses(MF);
182 // Instantiate the packetizer.
183 HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI);
185 // DFA state table should not be empty.
186 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
189 // Loop over all basic blocks and remove KILL pseudo-instructions
190 // These instructions confuse the dependence analysis. Consider:
192 // R0 = KILL R0, D0 (Insn 1)
194 // Here, Insn 1 will result in the dependence graph not emitting an output
195 // dependence between Insn 0 and Insn 2. This can lead to incorrect
198 for (auto &MB : MF) {
200 auto MI = MB.begin();
202 auto NextI = std::next(MI);
211 // Loop over all of the basic blocks.
212 for (auto &MB : MF) {
213 auto Begin = MB.begin(), End = MB.end();
214 while (Begin != End) {
215 // Find the first non-boundary starting from the end of the last
216 // scheduling region.
217 MachineBasicBlock::iterator RB = Begin;
218 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
220 // Find the first boundary starting from the beginning of the new
222 MachineBasicBlock::iterator RE = RB;
223 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
225 // Add the scheduling boundary if it's not block end.
228 // If RB == End, then RE == End.
230 Packetizer.PacketizeMIs(&MB, RB, RE);
236 Packetizer.unpacketizeSoloInstrs(MF);
241 // Reserve resources for a constant extender. Trigger an assertion if the
242 // reservation fails.
243 void HexagonPacketizerList::reserveResourcesForConstExt() {
244 if (!tryAllocateResourcesForConstExt(true))
245 llvm_unreachable("Resources not available");
248 bool HexagonPacketizerList::canReserveResourcesForConstExt() {
249 return tryAllocateResourcesForConstExt(false);
252 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
253 // return true, otherwise, return false.
254 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(bool Reserve) {
255 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
256 bool Avail = ResourceTracker->canReserveResources(*ExtMI);
257 if (Reserve && Avail)
258 ResourceTracker->reserveResources(*ExtMI);
259 MF.DeleteMachineInstr(ExtMI);
264 bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
265 SDep::Kind DepType, unsigned DepReg) {
266 // Check for LR dependence.
267 if (DepReg == HRI->getRARegister())
270 if (HII->isDeallocRet(MI))
271 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
274 // Call-like instructions can be packetized with preceding instructions
275 // that define registers implicitly used or modified by the call. Explicit
276 // uses are still prohibited, as in the case of indirect calls:
279 if (DepType == SDep::Data) {
280 for (const MachineOperand MO : MI.operands())
281 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
288 static bool isRegDependence(const SDep::Kind DepType) {
289 return DepType == SDep::Data || DepType == SDep::Anti ||
290 DepType == SDep::Output;
293 static bool isDirectJump(const MachineInstr &MI) {
294 return MI.getOpcode() == Hexagon::J2_jump;
297 static bool isSchedBarrier(const MachineInstr &MI) {
298 switch (MI.getOpcode()) {
299 case Hexagon::Y2_barrier:
305 static bool isControlFlow(const MachineInstr &MI) {
306 return MI.getDesc().isTerminator() || MI.getDesc().isCall();
310 /// Returns true if the instruction modifies a callee-saved register.
311 static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
312 const TargetRegisterInfo *TRI) {
313 const MachineFunction &MF = *MI.getParent()->getParent();
314 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
315 if (MI.modifiesRegister(*CSR, TRI))
320 // Returns true if an instruction can be promoted to .new predicate or
322 bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
323 const TargetRegisterClass *NewRC) {
324 // Vector stores can be predicated, and can be new-value stores, but
325 // they cannot be predicated on a .new predicate value.
326 if (NewRC == &Hexagon::PredRegsRegClass) {
327 if (HII->isHVXVec(MI) && MI.mayStore())
329 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
331 // If the class is not PredRegs, it could only apply to new-value stores.
332 return HII->mayBeNewStore(MI);
335 // Promote an instructiont to its .cur form.
336 // At this time, we have already made a call to canPromoteToDotCur and made
337 // sure that it can *indeed* be promoted.
338 bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI,
339 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
340 const TargetRegisterClass* RC) {
341 assert(DepType == SDep::Data);
342 int CurOpcode = HII->getDotCurOp(MI);
343 MI.setDesc(HII->get(CurOpcode));
347 void HexagonPacketizerList::cleanUpDotCur() {
348 MachineInstr *MI = nullptr;
349 for (auto BI : CurrentPacketMIs) {
350 DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
351 if (HII->isDotCurInst(*BI)) {
356 for (auto &MO : BI->operands())
357 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
363 // We did not find a use of the CUR, so de-cur it.
364 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
365 DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
368 // Check to see if an instruction can be dot cur.
369 bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
370 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
371 const TargetRegisterClass *RC) {
372 if (!HII->isHVXVec(MI))
374 if (!HII->isHVXVec(*MII))
377 // Already a dot new instruction.
378 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
381 if (!HII->mayBeCurLoad(MI))
384 // The "cur value" cannot come from inline asm.
385 if (PacketSU->getInstr()->isInlineAsm())
388 // Make sure candidate instruction uses cur.
389 DEBUG(dbgs() << "Can we DOT Cur Vector MI\n";
391 dbgs() << "in packet\n";);
392 MachineInstr &MJ = *MII;
394 dbgs() << "Checking CUR against ";
397 unsigned DestReg = MI.getOperand(0).getReg();
398 bool FoundMatch = false;
399 for (auto &MO : MJ.operands())
400 if (MO.isReg() && MO.getReg() == DestReg)
405 // Check for existing uses of a vector register within the packet which
406 // would be affected by converting a vector load into .cur formt.
407 for (auto BI : CurrentPacketMIs) {
408 DEBUG(dbgs() << "packet has "; BI->dump(););
409 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
413 DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
414 // We can convert the opcode into a .cur.
418 // Promote an instruction to its .new form. At this time, we have already
419 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
421 bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
422 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
423 const TargetRegisterClass* RC) {
424 assert (DepType == SDep::Data);
426 if (RC == &Hexagon::PredRegsRegClass)
427 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
429 NewOpcode = HII->getDotNewOp(MI);
430 MI.setDesc(HII->get(NewOpcode));
434 bool HexagonPacketizerList::demoteToDotOld(MachineInstr &MI) {
435 int NewOpcode = HII->getDotOldOp(MI);
436 MI.setDesc(HII->get(NewOpcode));
440 bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
441 unsigned Opc = MI.getOpcode();
443 case Hexagon::S2_storerd_io:
444 case Hexagon::S2_storeri_io:
445 case Hexagon::S2_storerh_io:
446 case Hexagon::S2_storerb_io:
449 llvm_unreachable("Unexpected instruction");
451 unsigned FrameSize = MF.getFrameInfo().getStackSize();
452 MachineOperand &Off = MI.getOperand(1);
453 int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
454 if (HII->isValidOffset(Opc, NewOff)) {
461 void HexagonPacketizerList::useCalleesSP(MachineInstr &MI) {
462 unsigned Opc = MI.getOpcode();
464 case Hexagon::S2_storerd_io:
465 case Hexagon::S2_storeri_io:
466 case Hexagon::S2_storerh_io:
467 case Hexagon::S2_storerb_io:
470 llvm_unreachable("Unexpected instruction");
472 unsigned FrameSize = MF.getFrameInfo().getStackSize();
473 MachineOperand &Off = MI.getOperand(1);
474 Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
483 /// Returns true if an instruction is predicated on p0 and false if it's
484 /// predicated on !p0.
485 static PredicateKind getPredicateSense(const MachineInstr &MI,
486 const HexagonInstrInfo *HII) {
487 if (!HII->isPredicated(MI))
489 if (HII->isPredicatedTrue(MI))
494 static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
495 const HexagonInstrInfo *HII) {
496 assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
498 // Post Increment means duplicates. Use dense map to find duplicates in the
499 // list. Caution: Densemap initializes with the minimum of 64 buckets,
500 // whereas there are at most 5 operands in the post increment.
501 DenseSet<unsigned> DefRegsSet;
502 for (auto &MO : MI.operands())
503 if (MO.isReg() && MO.isDef())
504 DefRegsSet.insert(MO.getReg());
506 for (auto &MO : MI.operands())
507 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
511 const MachineOperand &Op1 = MI.getOperand(1);
512 // The 2nd operand is always the post increment operand in load.
513 assert(Op1.isReg() && "Post increment operand has be to a register.");
516 if (MI.getDesc().mayStore()) {
517 const MachineOperand &Op0 = MI.getOperand(0);
518 // The 1st operand is always the post increment operand in store.
519 assert(Op0.isReg() && "Post increment operand has be to a register.");
523 // we should never come here.
524 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
527 // Get the value being stored.
528 static const MachineOperand& getStoreValueOperand(const MachineInstr &MI) {
529 // value being stored is always the last operand.
530 return MI.getOperand(MI.getNumOperands()-1);
533 static bool isLoadAbsSet(const MachineInstr &MI) {
534 unsigned Opc = MI.getOpcode();
536 case Hexagon::L4_loadrd_ap:
537 case Hexagon::L4_loadrb_ap:
538 case Hexagon::L4_loadrh_ap:
539 case Hexagon::L4_loadrub_ap:
540 case Hexagon::L4_loadruh_ap:
541 case Hexagon::L4_loadri_ap:
547 static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
548 assert(isLoadAbsSet(MI));
549 return MI.getOperand(1);
553 // Can be new value store?
554 // Following restrictions are to be respected in convert a store into
555 // a new value store.
556 // 1. If an instruction uses auto-increment, its address register cannot
557 // be a new-value register. Arch Spec 5.4.2.1
558 // 2. If an instruction uses absolute-set addressing mode, its address
559 // register cannot be a new-value register. Arch Spec 5.4.2.1.
560 // 3. If an instruction produces a 64-bit result, its registers cannot be used
561 // as new-value registers. Arch Spec 5.4.2.2.
562 // 4. If the instruction that sets the new-value register is conditional, then
563 // the instruction that uses the new-value register must also be conditional,
564 // and both must always have their predicates evaluate identically.
565 // Arch Spec 5.4.2.3.
566 // 5. There is an implied restriction that a packet cannot have another store,
567 // if there is a new value store in the packet. Corollary: if there is
568 // already a store in a packet, there can not be a new value store.
569 // Arch Spec: 3.4.4.2
570 bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
571 const MachineInstr &PacketMI, unsigned DepReg) {
572 // Make sure we are looking at the store, that can be promoted.
573 if (!HII->mayBeNewStore(MI))
576 // Make sure there is dependency and can be new value'd.
577 const MachineOperand &Val = getStoreValueOperand(MI);
578 if (Val.isReg() && Val.getReg() != DepReg)
581 const MCInstrDesc& MCID = PacketMI.getDesc();
583 // First operand is always the result.
584 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
585 // Double regs can not feed into new value store: PRM section: 5.4.2.2.
586 if (PacketRC == &Hexagon::DoubleRegsRegClass)
589 // New-value stores are of class NV (slot 0), dual stores require class ST
590 // in slot 0 (PRM 5.5).
591 for (auto I : CurrentPacketMIs) {
592 SUnit *PacketSU = MIToSUnit.find(I)->second;
593 if (PacketSU->getInstr()->mayStore())
597 // Make sure it's NOT the post increment register that we are going to
599 if (HII->isPostIncrement(MI) &&
600 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
604 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
605 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
606 // If source is post_inc, or absolute-set addressing, it can not feed
607 // into new value store
609 // memw(r30 + #-1404) = r2.new -> can not be new value store
610 // arch spec section: 5.4.2.1.
614 if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
617 // If the source that feeds the store is predicated, new value store must
618 // also be predicated.
619 if (HII->isPredicated(PacketMI)) {
620 if (!HII->isPredicated(MI))
623 // Check to make sure that they both will have their predicates
624 // evaluate identically.
625 unsigned predRegNumSrc = 0;
626 unsigned predRegNumDst = 0;
627 const TargetRegisterClass* predRegClass = nullptr;
629 // Get predicate register used in the source instruction.
630 for (auto &MO : PacketMI.operands()) {
633 predRegNumSrc = MO.getReg();
634 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
635 if (predRegClass == &Hexagon::PredRegsRegClass)
638 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
639 "predicate register not found in a predicated PacketMI instruction");
641 // Get predicate register used in new-value store instruction.
642 for (auto &MO : MI.operands()) {
645 predRegNumDst = MO.getReg();
646 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
647 if (predRegClass == &Hexagon::PredRegsRegClass)
650 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
651 "predicate register not found in a predicated MI instruction");
653 // New-value register producer and user (store) need to satisfy these
655 // 1) Both instructions should be predicated on the same register.
656 // 2) If producer of the new-value register is .new predicated then store
657 // should also be .new predicated and if producer is not .new predicated
658 // then store should not be .new predicated.
659 // 3) Both new-value register producer and user should have same predicate
660 // sense, i.e, either both should be negated or both should be non-negated.
661 if (predRegNumDst != predRegNumSrc ||
662 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
663 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
667 // Make sure that other than the new-value register no other store instruction
668 // register has been modified in the same packet. Predicate registers can be
669 // modified by they should not be modified between the producer and the store
670 // instruction as it will make them both conditional on different values.
671 // We already know this to be true for all the instructions before and
672 // including PacketMI. Howerver, we need to perform the check for the
673 // remaining instructions in the packet.
675 unsigned StartCheck = 0;
677 for (auto I : CurrentPacketMIs) {
678 SUnit *TempSU = MIToSUnit.find(I)->second;
679 MachineInstr &TempMI = *TempSU->getInstr();
681 // Following condition is true for all the instructions until PacketMI is
682 // reached (StartCheck is set to 0 before the for loop).
683 // StartCheck flag is 1 for all the instructions after PacketMI.
684 if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
685 continue; // encountering PacketMI.
688 if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
691 for (auto &MO : MI.operands())
692 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
696 // Make sure that for non-POST_INC stores:
697 // 1. The only use of reg is DepReg and no other registers.
698 // This handles V4 base+index registers.
699 // The following store can not be dot new.
700 // Eg. r0 = add(r0, #3)
701 // memw(r1+r0<<#2) = r0
702 if (!HII->isPostIncrement(MI)) {
703 for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
704 const MachineOperand &MO = MI.getOperand(opNum);
705 if (MO.isReg() && MO.getReg() == DepReg)
710 // If data definition is because of implicit definition of the register,
711 // do not newify the store. Eg.
712 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
713 // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
714 for (auto &MO : PacketMI.operands()) {
715 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
717 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
719 unsigned R = MO.getReg();
720 if (R == DepReg || HRI->isSuperRegister(DepReg, R))
724 // Handle imp-use of super reg case. There is a target independent side
725 // change that should prevent this situation but I am handling it for
726 // just-in-case. For example, we cannot newify R2 in the following case:
727 // %R3<def> = A2_tfrsi 0;
728 // S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
729 for (auto &MO : MI.operands()) {
730 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
734 // Can be dot new store.
738 // Can this MI to promoted to either new value store or new value jump.
739 bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr &MI,
740 const SUnit *PacketSU, unsigned DepReg,
741 MachineBasicBlock::iterator &MII) {
742 if (!HII->mayBeNewStore(MI))
745 // Check to see the store can be new value'ed.
746 MachineInstr &PacketMI = *PacketSU->getInstr();
747 if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
750 // Check to see the compare/jump can be new value'ed.
751 // This is done as a pass on its own. Don't need to check it here.
755 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
757 for (auto &MO : I.operands()) {
758 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
760 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
762 if (CheckDef == MO.isDef())
768 // Check to see if an instruction can be dot new
769 // There are three kinds.
770 // 1. dot new on predicate - V2/V3/V4
771 // 2. dot new on stores NV/ST - V4
772 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
773 bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
774 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
775 const TargetRegisterClass* RC) {
776 // Already a dot new instruction.
777 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
780 if (!isNewifiable(MI, RC))
783 const MachineInstr &PI = *PacketSU->getInstr();
785 // The "new value" cannot come from inline asm.
786 if (PI.isInlineAsm())
789 // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
791 if (PI.isImplicitDef())
794 // If dependency is trough an implicitly defined register, we should not
796 if (isImplicitDependency(PI, true, DepReg) ||
797 isImplicitDependency(MI, false, DepReg))
800 const MCInstrDesc& MCID = PI.getDesc();
801 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
802 if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass)
806 if (RC == &Hexagon::PredRegsRegClass)
807 return HII->predCanBeUsedAsDotNew(PI, DepReg);
809 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
812 // Create a dot new machine instruction to see if resources can be
813 // allocated. If not, bail out now.
814 int NewOpcode = HII->getDotNewOp(MI);
815 const MCInstrDesc &D = HII->get(NewOpcode);
816 MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
817 bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
818 MF.DeleteMachineInstr(NewMI);
819 if (!ResourcesAvailable)
822 // New Value Store only. New Value Jump generated as a separate pass.
823 if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
829 // Go through the packet instructions and search for an anti dependency between
830 // them and DepReg from MI. Consider this case:
832 // a) %R1<def> = TFRI_cdNotPt %P3, 2
835 // b) %P0<def> = C2_or %P3<kill>, %P0<kill>
836 // c) %P3<def> = C2_tfrrp %R23
837 // d) %R1<def> = C2_cmovenewit %P3, 4
839 // The P3 from a) and d) will be complements after
840 // a)'s P3 is converted to .new form
841 // Anti-dep between c) and b) is irrelevant for this case
842 bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
844 SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
846 for (auto I : CurrentPacketMIs) {
847 // We only care for dependencies to predicated instructions
848 if (!HII->isPredicated(*I))
851 // Scheduling Unit for current insn in the packet
852 SUnit *PacketSU = MIToSUnit.find(I)->second;
854 // Look at dependencies between current members of the packet and
855 // predicate defining instruction MI. Make sure that dependency is
856 // on the exact register we care about.
857 if (PacketSU->isSucc(PacketSUDep)) {
858 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
859 auto &Dep = PacketSU->Succs[i];
860 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
861 Dep.getReg() == DepReg)
871 /// Gets the predicate register of a predicated instruction.
872 static unsigned getPredicatedRegister(MachineInstr &MI,
873 const HexagonInstrInfo *QII) {
874 /// We use the following rule: The first predicate register that is a use is
875 /// the predicate register of a predicated instruction.
876 assert(QII->isPredicated(MI) && "Must be predicated instruction");
878 for (auto &Op : MI.operands()) {
879 if (Op.isReg() && Op.getReg() && Op.isUse() &&
880 Hexagon::PredRegsRegClass.contains(Op.getReg()))
884 llvm_unreachable("Unknown instruction operand layout");
888 // Given two predicated instructions, this function detects whether
889 // the predicates are complements.
890 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
892 // If we don't know the predicate sense of the instructions bail out early, we
894 if (getPredicateSense(MI1, HII) == PK_Unknown ||
895 getPredicateSense(MI2, HII) == PK_Unknown)
898 // Scheduling unit for candidate.
899 SUnit *SU = MIToSUnit[&MI1];
901 // One corner case deals with the following scenario:
903 // a) %R24<def> = A2_tfrt %P0, %R25
906 // b) %R25<def> = A2_tfrf %P0, %R24
907 // c) %P0<def> = C2_cmpeqi %R26, 1
910 // On general check a) and b) are complements, but presence of c) will
911 // convert a) to .new form, and then it is not a complement.
912 // We attempt to detect it by analyzing existing dependencies in the packet.
914 // Analyze relationships between all existing members of the packet.
915 // Look for Anti dependecy on the same predicate reg as used in the
917 for (auto I : CurrentPacketMIs) {
918 // Scheduling Unit for current insn in the packet.
919 SUnit *PacketSU = MIToSUnit.find(I)->second;
921 // If this instruction in the packet is succeeded by the candidate...
922 if (PacketSU->isSucc(SU)) {
923 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
924 auto Dep = PacketSU->Succs[i];
925 // The corner case exist when there is true data dependency between
926 // candidate and one of current packet members, this dep is on
927 // predicate reg, and there already exist anti dep on the same pred in
929 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
930 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
931 // Here I know that I is predicate setting instruction with true
932 // data dep to candidate on the register we care about - c) in the
933 // above example. Now I need to see if there is an anti dependency
934 // from c) to any other instruction in the same packet on the pred
936 if (restrictingDepExistInPacket(*I, Dep.getReg()))
943 // If the above case does not apply, check regular complement condition.
944 // Check that the predicate register is the same and that the predicate
945 // sense is different We also need to differentiate .old vs. .new: !p0
946 // is not complementary to p0.new.
947 unsigned PReg1 = getPredicatedRegister(MI1, HII);
948 unsigned PReg2 = getPredicatedRegister(MI2, HII);
949 return PReg1 == PReg2 &&
950 Hexagon::PredRegsRegClass.contains(PReg1) &&
951 Hexagon::PredRegsRegClass.contains(PReg2) &&
952 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
953 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
956 // Initialize packetizer flags.
957 void HexagonPacketizerList::initPacketizerState() {
959 PromotedToDotNew = false;
960 GlueToNewValueJump = false;
961 GlueAllocframeStore = false;
962 FoundSequentialDependence = false;
965 // Ignore bundling of pseudo instructions.
966 bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
967 const MachineBasicBlock *) {
968 if (MI.isDebugValue())
971 if (MI.isCFIInstruction())
974 // We must print out inline assembly.
975 if (MI.isInlineAsm())
978 if (MI.isImplicitDef())
981 // We check if MI has any functional units mapped to it. If it doesn't,
982 // we ignore the instruction.
983 const MCInstrDesc& TID = MI.getDesc();
984 auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
985 unsigned FuncUnits = IS->getUnits();
989 bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) {
990 if (MI.isEHLabel() || MI.isCFIInstruction())
993 // Consider inline asm to not be a solo instruction by default.
994 // Inline asm will be put in a packet temporarily, but then it will be
995 // removed, and placed outside of the packet (before or after, depending
996 // on dependencies). This is to reduce the impact of inline asm as a
997 // "packet splitting" instruction.
998 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1001 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1002 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
1003 // They must not be grouped with other instructions in a packet.
1004 if (isSchedBarrier(MI))
1007 if (HII->isSolo(MI))
1010 if (MI.getOpcode() == Hexagon::A2_nop)
1017 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1018 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1019 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1020 // For full test call this function twice:
1021 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1022 // Doing the test only one way saves the amount of code in this function,
1023 // since every test would need to be repeated with the MI and MJ reversed.
1024 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1025 const HexagonInstrInfo &HII) {
1026 const MachineFunction *MF = MI.getParent()->getParent();
1027 if (MF->getSubtarget<HexagonSubtarget>().hasV60TOpsOnly() &&
1028 HII.isHVXMemWithAIndirect(MI, MJ))
1031 // An inline asm cannot be together with a branch, because we may not be
1032 // able to remove the asm out after packetizing (i.e. if the asm must be
1033 // moved past the bundle). Similarly, two asms cannot be together to avoid
1034 // complications when determining their relative order outside of a bundle.
1035 if (MI.isInlineAsm())
1036 return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1037 MJ.isCall() || MJ.isTerminator();
1039 switch (MI.getOpcode()) {
1040 case (Hexagon::S2_storew_locked):
1041 case (Hexagon::S4_stored_locked):
1042 case (Hexagon::L2_loadw_locked):
1043 case (Hexagon::L4_loadd_locked):
1044 case (Hexagon::Y4_l2fetch): {
1045 // These instructions can only be grouped with ALU32 or non-floating-point
1046 // XTYPE instructions. Since there is no convenient way of identifying fp
1047 // XTYPE instructions, only allow grouping with ALU32 for now.
1048 unsigned TJ = HII.getType(MJ);
1049 if (TJ != HexagonII::TypeALU32_2op &&
1050 TJ != HexagonII::TypeALU32_3op &&
1051 TJ != HexagonII::TypeALU32_ADDI)
1059 // "False" really means that the quick check failed to determine if
1060 // I and J cannot coexist.
1065 // Full, symmetric check.
1066 bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI,
1067 const MachineInstr &MJ) {
1068 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1071 void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) {
1072 for (auto &B : MF) {
1073 MachineBasicBlock::iterator BundleIt;
1074 MachineBasicBlock::instr_iterator NextI;
1075 for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1076 NextI = std::next(I);
1077 MachineInstr &MI = *I;
1080 if (!MI.isInsideBundle())
1083 // Decide on where to insert the instruction that we are pulling out.
1084 // Debug instructions always go before the bundle, but the placement of
1085 // INLINE_ASM depends on potential dependencies. By default, try to
1086 // put it before the bundle, but if the asm writes to a register that
1087 // other instructions in the bundle read, then we need to place it
1088 // after the bundle (to preserve the bundle semantics).
1089 bool InsertBeforeBundle;
1090 if (MI.isInlineAsm())
1091 InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1092 else if (MI.isDebugValue())
1093 InsertBeforeBundle = true;
1097 BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1102 // Check if a given instruction is of class "system".
1103 static bool isSystemInstr(const MachineInstr &MI) {
1104 unsigned Opc = MI.getOpcode();
1106 case Hexagon::Y2_barrier:
1107 case Hexagon::Y2_dcfetchbo:
1113 bool HexagonPacketizerList::hasDeadDependence(const MachineInstr &I,
1114 const MachineInstr &J) {
1115 // The dependence graph may not include edges between dead definitions,
1116 // so without extra checks, we could end up packetizing two instruction
1117 // defining the same (dead) register.
1118 if (I.isCall() || J.isCall())
1120 if (HII->isPredicated(I) || HII->isPredicated(J))
1123 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1124 for (auto &MO : I.operands()) {
1125 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1127 DeadDefs[MO.getReg()] = true;
1130 for (auto &MO : J.operands()) {
1131 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1133 unsigned R = MO.getReg();
1134 if (R != Hexagon::USR_OVF && DeadDefs[R])
1140 bool HexagonPacketizerList::hasControlDependence(const MachineInstr &I,
1141 const MachineInstr &J) {
1142 // A save callee-save register function call can only be in a packet
1143 // with instructions that don't write to the callee-save registers.
1144 if ((HII->isSaveCalleeSavedRegsCall(I) &&
1145 doesModifyCalleeSavedReg(J, HRI)) ||
1146 (HII->isSaveCalleeSavedRegsCall(J) &&
1147 doesModifyCalleeSavedReg(I, HRI)))
1150 // Two control flow instructions cannot go in the same packet.
1151 if (isControlFlow(I) && isControlFlow(J))
1154 // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1155 // contain a speculative indirect jump,
1156 // a new-value compare jump or a dealloc_return.
1157 auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1158 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1160 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1165 if (HII->isLoopN(I) && isBadForLoopN(J))
1167 if (HII->isLoopN(J) && isBadForLoopN(I))
1170 // dealloc_return cannot appear in the same packet as a conditional or
1171 // unconditional jump.
1172 return HII->isDeallocRet(I) &&
1173 (J.isBranch() || J.isCall() || J.isBarrier());
1176 bool HexagonPacketizerList::hasRegMaskDependence(const MachineInstr &I,
1177 const MachineInstr &J) {
1178 // Adding I to a packet that has J.
1180 // Regmasks are not reflected in the scheduling dependency graph, so
1181 // we need to check them manually. This code assumes that regmasks only
1182 // occur on calls, and the problematic case is when we add an instruction
1183 // defining a register R to a packet that has a call that clobbers R via
1184 // a regmask. Those cannot be packetized together, because the call will
1185 // be executed last. That's also a reson why it is ok to add a call
1186 // clobbering R to a packet that defines R.
1188 // Look for regmasks in J.
1189 for (const MachineOperand &OpJ : J.operands()) {
1190 if (!OpJ.isRegMask())
1192 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1193 for (const MachineOperand &OpI : I.operands()) {
1195 if (OpJ.clobbersPhysReg(OpI.getReg()))
1197 } else if (OpI.isRegMask()) {
1198 // Both are regmasks. Assume that they intersect.
1206 bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I,
1207 const MachineInstr &J) {
1208 bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1209 bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1210 if ((SysI && StoreJ) || (SysJ && StoreI))
1213 if (StoreI && StoreJ) {
1214 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1217 // A memop cannot be in the same packet with another memop or a store.
1218 // Two stores can be together, but here I and J cannot both be stores.
1219 bool MopStI = HII->isMemOp(I) || StoreI;
1220 bool MopStJ = HII->isMemOp(J) || StoreJ;
1221 if (MopStI && MopStJ)
1225 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1228 // SUI is the current instruction that is out side of the current packet.
1229 // SUJ is the current instruction inside the current packet against which that
1230 // SUI will be packetized.
1231 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
1232 assert(SUI->getInstr() && SUJ->getInstr());
1233 MachineInstr &I = *SUI->getInstr();
1234 MachineInstr &J = *SUJ->getInstr();
1236 // Clear IgnoreDepMIs when Packet starts.
1237 if (CurrentPacketMIs.size() == 1)
1238 IgnoreDepMIs.clear();
1240 MachineBasicBlock::iterator II = I.getIterator();
1242 // Solo instructions cannot go in the packet.
1243 assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1245 if (cannotCoexist(I, J))
1248 Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
1252 // Regmasks are not accounted for in the scheduling graph, so we need
1253 // to explicitly check for dependencies caused by them. They should only
1254 // appear on calls, so it's not too pessimistic to reject all regmask
1256 Dependence = hasRegMaskDependence(I, J);
1260 // V4 allows dual stores. It does not allow second store, if the first
1261 // store is not in SLOT0. New value store, new value jump, dealloc_return
1262 // and memop always take SLOT0. Arch spec 3.4.4.2.
1263 Dependence = hasV4SpecificDependence(I, J);
1267 // If an instruction feeds new value jump, glue it.
1268 MachineBasicBlock::iterator NextMII = I.getIterator();
1270 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1271 MachineInstr &NextMI = *NextMII;
1273 bool secondRegMatch = false;
1274 const MachineOperand &NOp0 = NextMI.getOperand(0);
1275 const MachineOperand &NOp1 = NextMI.getOperand(1);
1277 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1278 secondRegMatch = true;
1280 for (auto T : CurrentPacketMIs) {
1281 SUnit *PacketSU = MIToSUnit.find(T)->second;
1282 MachineInstr &PI = *PacketSU->getInstr();
1283 // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1289 // 1. Packet does not have a store in it.
1290 // 2. If the first operand of the nvj is newified, and the second
1291 // operand is also a reg, it (second reg) is not defined in
1293 // 3. If the second operand of the nvj is newified, (which means
1294 // first operand is also a reg), first reg is not defined in
1296 if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
1302 const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1303 if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
1311 GlueToNewValueJump = true;
1314 // There no dependency between a prolog instruction and its successor.
1315 if (!SUJ->isSucc(SUI))
1318 for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1319 if (FoundSequentialDependence)
1322 if (SUJ->Succs[i].getSUnit() != SUI)
1325 SDep::Kind DepType = SUJ->Succs[i].getKind();
1326 // For direct calls:
1327 // Ignore register dependences for call instructions for packetization
1328 // purposes except for those due to r31 and predicate registers.
1330 // For indirect calls:
1331 // Same as direct calls + check for true dependences to the register
1332 // used in the indirect call.
1334 // We completely ignore Order dependences for call instructions.
1337 // Ignore register dependences for return instructions like jumpr,
1338 // dealloc return unless we have dependencies on the explicit uses
1339 // of the registers used by jumpr (like r31) or dealloc return
1340 // (like r29 or r30).
1341 unsigned DepReg = 0;
1342 const TargetRegisterClass *RC = nullptr;
1343 if (DepType == SDep::Data) {
1344 DepReg = SUJ->Succs[i].getReg();
1345 RC = HRI->getMinimalPhysRegClass(DepReg);
1348 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1349 if (!isRegDependence(DepType))
1351 if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1355 if (DepType == SDep::Data) {
1356 if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1357 if (promoteToDotCur(J, DepType, II, RC))
1361 // Data dpendence ok if we have load.cur.
1362 if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1363 if (HII->isHVXVec(I))
1367 // For instructions that can be promoted to dot-new, try to promote.
1368 if (DepType == SDep::Data) {
1369 if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1370 if (promoteToDotNew(I, DepType, II, RC)) {
1371 PromotedToDotNew = true;
1372 if (cannotCoexist(I, J))
1373 FoundSequentialDependence = true;
1377 if (HII->isNewValueJump(I))
1381 // For predicated instructions, if the predicates are complements then
1382 // there can be no dependence.
1383 if (HII->isPredicated(I) && HII->isPredicated(J) &&
1384 arePredicatesComplements(I, J)) {
1385 // Not always safe to do this translation.
1386 // DAG Builder attempts to reduce dependence edges using transitive
1387 // nature of dependencies. Here is an example:
1389 // r0 = tfr_pt ... (1)
1390 // r0 = tfr_pf ... (2)
1391 // r0 = tfr_pt ... (3)
1393 // There will be an output dependence between (1)->(2) and (2)->(3).
1394 // However, there is no dependence edge between (1)->(3). This results
1395 // in all 3 instructions going in the same packet. We ignore dependce
1396 // only once to avoid this situation.
1397 auto Itr = find(IgnoreDepMIs, &J);
1398 if (Itr != IgnoreDepMIs.end()) {
1402 IgnoreDepMIs.push_back(&I);
1406 // Ignore Order dependences between unconditional direct branches
1407 // and non-control-flow instructions.
1408 if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1409 DepType == SDep::Order)
1412 // Ignore all dependences for jumps except for true and output
1414 if (I.isConditionalBranch() && DepType != SDep::Data &&
1415 DepType != SDep::Output)
1418 if (DepType == SDep::Output) {
1419 FoundSequentialDependence = true;
1423 // For Order dependences:
1424 // 1. On V4 or later, volatile loads/stores can be packetized together,
1425 // unless other rules prevent is.
1426 // 2. Store followed by a load is not allowed.
1427 // 3. Store followed by a store is only valid on V4 or later.
1428 // 4. Load followed by any memory operation is allowed.
1429 if (DepType == SDep::Order) {
1430 if (!PacketizeVolatiles) {
1431 bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1433 FoundSequentialDependence = true;
1437 // J is first, I is second.
1438 bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1439 bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1441 // Two stores are only allowed on V4+. Load following store is never
1444 FoundSequentialDependence = true;
1447 } else if (!LoadJ || (!LoadI && !StoreI)) {
1448 // If J is neither load nor store, assume a dependency.
1449 // If J is a load, but I is neither, also assume a dependency.
1450 FoundSequentialDependence = true;
1453 // Store followed by store: not OK on V2.
1454 // Store followed by load: not OK on all.
1455 // Load followed by store: OK on all.
1456 // Load followed by load: OK on all.
1460 // For V4, special case ALLOCFRAME. Even though there is dependency
1461 // between ALLOCFRAME and subsequent store, allow it to be packetized
1462 // in a same packet. This implies that the store is using the caller's
1463 // SP. Hence, offset needs to be updated accordingly.
1464 if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1465 unsigned Opc = I.getOpcode();
1467 case Hexagon::S2_storerd_io:
1468 case Hexagon::S2_storeri_io:
1469 case Hexagon::S2_storerh_io:
1470 case Hexagon::S2_storerb_io:
1471 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1472 // Since this store is to be glued with allocframe in the same
1473 // packet, it will use SP of the previous stack frame, i.e.
1474 // caller's SP. Therefore, we need to recalculate offset
1475 // according to this change.
1476 GlueAllocframeStore = useCallersSP(I);
1477 if (GlueAllocframeStore)
1485 // There are certain anti-dependencies that cannot be ignored.
1487 // J2_call ... %R0<imp-def> ; SUJ
1489 // Those cannot be packetized together, since the call will observe
1490 // the effect of the assignment to R0.
1491 if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1492 // Check if I defines any volatile register. We should also check
1493 // registers that the call may read, but these happen to be a
1494 // subset of the volatile register set.
1495 for (const MachineOperand &Op : I.operands()) {
1496 if (Op.isReg() && Op.isDef()) {
1497 unsigned R = Op.getReg();
1498 if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1500 } else if (!Op.isRegMask()) {
1501 // If I has a regmask assume dependency.
1504 FoundSequentialDependence = true;
1509 // Skip over remaining anti-dependences. Two instructions that are
1510 // anti-dependent can share a packet, since in most such cases all
1511 // operands are read before any modifications take place.
1512 // The exceptions are branch and call instructions, since they are
1513 // executed after all other instructions have completed (at least
1515 if (DepType != SDep::Anti) {
1516 FoundSequentialDependence = true;
1521 if (FoundSequentialDependence) {
1529 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1530 assert(SUI->getInstr() && SUJ->getInstr());
1531 MachineInstr &I = *SUI->getInstr();
1532 MachineInstr &J = *SUJ->getInstr();
1534 bool Coexist = !cannotCoexist(I, J);
1536 if (Coexist && !Dependence)
1539 // Check if the instruction was promoted to a dot-new. If so, demote it
1540 // back into a dot-old.
1541 if (PromotedToDotNew)
1545 // Check if the instruction (must be a store) was glued with an allocframe
1546 // instruction. If so, restore its offset to its original value, i.e. use
1547 // current SP instead of caller's SP.
1548 if (GlueAllocframeStore) {
1550 GlueAllocframeStore = false;
1555 MachineBasicBlock::iterator
1556 HexagonPacketizerList::addToPacket(MachineInstr &MI) {
1557 MachineBasicBlock::iterator MII = MI.getIterator();
1558 MachineBasicBlock *MBB = MI.getParent();
1560 if (CurrentPacketMIs.size() == 0)
1561 PacketStalls = false;
1562 PacketStalls |= producesStall(MI);
1564 if (MI.isImplicitDef())
1566 assert(ResourceTracker->canReserveResources(MI));
1568 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1571 if (GlueToNewValueJump) {
1572 MachineInstr &NvjMI = *++MII;
1573 // We need to put both instructions in the same packet: MI and NvjMI.
1574 // Either of them can require a constant extender. Try to add both to
1575 // the current packet, and if that fails, end the packet and start a
1577 ResourceTracker->reserveResources(MI);
1579 Good = tryAllocateResourcesForConstExt(true);
1581 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1583 if (ResourceTracker->canReserveResources(NvjMI))
1584 ResourceTracker->reserveResources(NvjMI);
1588 if (Good && ExtNvjMI)
1589 Good = tryAllocateResourcesForConstExt(true);
1593 assert(ResourceTracker->canReserveResources(MI));
1594 ResourceTracker->reserveResources(MI);
1596 assert(canReserveResourcesForConstExt());
1597 tryAllocateResourcesForConstExt(true);
1599 assert(ResourceTracker->canReserveResources(NvjMI));
1600 ResourceTracker->reserveResources(NvjMI);
1602 assert(canReserveResourcesForConstExt());
1603 reserveResourcesForConstExt();
1606 CurrentPacketMIs.push_back(&MI);
1607 CurrentPacketMIs.push_back(&NvjMI);
1611 ResourceTracker->reserveResources(MI);
1612 if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1614 if (PromotedToDotNew)
1616 if (GlueAllocframeStore) {
1618 GlueAllocframeStore = false;
1620 ResourceTracker->reserveResources(MI);
1621 reserveResourcesForConstExt();
1624 CurrentPacketMIs.push_back(&MI);
1628 void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB,
1629 MachineBasicBlock::iterator MI) {
1630 OldPacketMIs = CurrentPacketMIs;
1631 VLIWPacketizerList::endPacket(MBB, MI);
1634 bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
1635 return !producesStall(MI);
1639 // V60 forward scheduling.
1640 bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
1641 // If the packet already stalls, then ignore the stall from a subsequent
1642 // instruction in the same packet.
1646 // Check whether the previous packet is in a different loop. If this is the
1647 // case, there is little point in trying to avoid a stall because that would
1648 // favor the rare case (loop entry) over the common case (loop iteration).
1650 // TODO: We should really be able to check all the incoming edges if this is
1651 // the first packet in a basic block, so we can avoid stalls from the loop
1653 if (!OldPacketMIs.empty()) {
1654 auto *OldBB = OldPacketMIs.front()->getParent();
1655 auto *ThisBB = I.getParent();
1656 if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1660 SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1662 // Check if the latency is 0 between this instruction and any instruction
1663 // in the current packet. If so, we disregard any potential stalls due to
1664 // the instructions in the previous packet. Most of the instruction pairs
1665 // that can go together in the same packet have 0 latency between them.
1666 // Only exceptions are newValueJumps as they're generated much later and
1667 // the latencies can't be changed at that point. Another is .cur
1668 // instructions if its consumer has a 0 latency successor (such as .new).
1669 // In this case, the latency between .cur and the consumer stays non-zero
1670 // even though we can have both .cur and .new in the same packet. Changing
1671 // the latency to 0 is not an option as it causes software pipeliner to
1672 // not pipeline in some cases.
1676 // I1: v6.cur = vmem(r0++#1)
1677 // I2: v7 = valign(v6,v4,r2)
1678 // I3: vmem(r5++#1) = v7.new
1680 // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1682 for (auto J : CurrentPacketMIs) {
1683 SUnit *SUJ = MIToSUnit[J];
1684 for (auto &Pred : SUI->Preds)
1685 if (Pred.getSUnit() == SUJ &&
1686 (Pred.getLatency() == 0 || HII->isNewValueJump(I) ||
1687 HII->isToBeScheduledASAP(*J, I)))
1691 // Check if the latency is greater than one between this instruction and any
1692 // instruction in the previous packet.
1693 for (auto J : OldPacketMIs) {
1694 SUnit *SUJ = MIToSUnit[J];
1695 for (auto &Pred : SUI->Preds)
1696 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1700 // Check if the latency is greater than one between this instruction and any
1701 // instruction in the previous packet.
1702 for (auto J : OldPacketMIs) {
1703 SUnit *SUJ = MIToSUnit[J];
1704 for (auto &Pred : SUI->Preds)
1705 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1712 //===----------------------------------------------------------------------===//
1713 // Public Constructor Functions
1714 //===----------------------------------------------------------------------===//
1716 FunctionPass *llvm::createHexagonPacketizer() {
1717 return new HexagonPacketizer();