1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
13 #include "llvm/CodeGen/DFAPacketizer.h"
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/CodeGen/ScheduleDAG.h"
20 class HexagonInstrInfo;
21 class HexagonRegisterInfo;
22 class MachineBranchProbabilityInfo;
23 class MachineFunction;
25 class MachineLoopInfo;
26 class TargetRegisterClass;
28 class HexagonPacketizerList : public VLIWPacketizerList {
29 // Vector of instructions assigned to the packet that has just been created.
30 std::vector<MachineInstr *> OldPacketMIs;
32 // Has the instruction been promoted to a dot-new instruction.
33 bool PromotedToDotNew;
35 // Has the instruction been glued to allocframe.
36 bool GlueAllocframeStore;
38 // Has the feeder instruction been glued to new value jump.
39 bool GlueToNewValueJump;
41 // This holds the offset value, when pruning the dependences.
42 int64_t ChangedOffset;
44 // Check if there is a dependence between some instruction already in this
45 // packet and this instruction.
48 // Only check for dependence if there are resources available to
49 // schedule this instruction.
50 bool FoundSequentialDependence;
52 bool MemShufDisabled = false;
54 // Track MIs with ignored dependence.
55 std::vector<MachineInstr*> IgnoreDepMIs;
57 // Set to true if the packet contains an instruction that stalls with an
58 // instruction from the previous packet.
59 bool PacketStalls = false;
62 /// A handle to the branch probability pass.
63 const MachineBranchProbabilityInfo *MBPI;
64 const MachineLoopInfo *MLI;
67 const HexagonInstrInfo *HII;
68 const HexagonRegisterInfo *HRI;
72 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
74 const MachineBranchProbabilityInfo *MBPI,
77 // initPacketizerState - initialize some internal flags.
78 void initPacketizerState() override;
80 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
81 bool ignorePseudoInstruction(const MachineInstr &MI,
82 const MachineBasicBlock *MBB) override;
84 // isSoloInstruction - return true if instruction MI can not be packetized
85 // with any other instruction, which means that MI itself is a packet.
86 bool isSoloInstruction(const MachineInstr &MI) override;
88 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
90 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
92 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
94 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
96 bool foundLSInPacket();
97 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
98 void endPacket(MachineBasicBlock *MBB,
99 MachineBasicBlock::iterator MI) override;
100 bool shouldAddToPacket(const MachineInstr &MI) override;
102 void unpacketizeSoloInstrs(MachineFunction &MF);
105 bool getmemShufDisabled() {
106 return MemShufDisabled;
108 void setmemShufDisabled(bool val) {
109 MemShufDisabled = val;
111 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
113 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
114 MachineBasicBlock::iterator &MII,
115 const TargetRegisterClass *RC);
116 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
117 unsigned DepReg, MachineBasicBlock::iterator &MII,
118 const TargetRegisterClass *RC);
119 void cleanUpDotCur();
121 bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
122 MachineBasicBlock::iterator &MII,
123 const TargetRegisterClass *RC);
124 bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
125 unsigned DepReg, MachineBasicBlock::iterator &MII,
126 const TargetRegisterClass *RC);
127 bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
128 unsigned DepReg, MachineBasicBlock::iterator &MII);
129 bool canPromoteToNewValueStore(const MachineInstr &MI,
130 const MachineInstr &PacketMI, unsigned DepReg);
131 bool demoteToDotOld(MachineInstr &MI);
132 bool useCallersSP(MachineInstr &MI);
133 void useCalleesSP(MachineInstr &MI);
134 bool updateOffset(SUnit *SUI, SUnit *SUJ);
135 void undoChangedOffset(MachineInstr &MI);
136 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
137 bool restrictingDepExistInPacket(MachineInstr&, unsigned);
138 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
139 bool isCurifiable(MachineInstr &MI);
140 bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
142 bool isPromotedToDotNew() const {
143 return PromotedToDotNew;
146 bool tryAllocateResourcesForConstExt(bool Reserve);
147 bool canReserveResourcesForConstExt();
148 void reserveResourcesForConstExt();
149 bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
150 bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
151 bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
152 bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
153 bool producesStall(const MachineInstr &MI);
156 } // end namespace llvm
158 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H