1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "HexagonFixupKinds.h"
12 #include "MCTargetDesc/HexagonBaseInfo.h"
13 #include "MCTargetDesc/HexagonMCChecker.h"
14 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "MCTargetDesc/HexagonMCInstrInfo.h"
17 #include "MCTargetDesc/HexagonMCShuffler.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAsmLayout.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/TargetRegistry.h"
32 using namespace Hexagon;
34 #define DEBUG_TYPE "hexagon-asm-backend"
36 static cl::opt<bool> DisableFixup
37 ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
41 class HexagonAsmBackend : public MCAsmBackend {
44 mutable uint64_t relaxedCnt;
45 std::unique_ptr <MCInstrInfo> MCII;
46 std::unique_ptr <MCInst *> RelaxTarget;
49 void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
51 SmallVector<MCFixup, 4> Fixups;
52 SmallString<256> Code;
53 raw_svector_ostream VecOS(Code);
54 E.encodeInstruction(HMB, VecOS, Fixups, RF.getSubtargetInfo());
56 // Update the fragment.
58 RF.getContents() = Code;
59 RF.getFixups() = Fixups;
63 HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
65 OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()),
66 RelaxTarget(new MCInst *), Extender(nullptr) {}
68 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
69 return createHexagonELFObjectWriter(OS, OSABI, CPU);
72 void setExtender(MCContext &Context) const {
73 if (Extender == nullptr)
74 const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
77 MCInst *takeExtender() const {
78 assert(Extender != nullptr);
79 MCInst * Result = Extender;
80 const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
84 unsigned getNumFixupKinds() const override {
85 return Hexagon::NumTargetFixupKinds;
88 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
89 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
90 // This table *must* be in same the order of fixup_* kinds in
91 // HexagonFixupKinds.h.
93 // namei offset bits flags
94 { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
95 { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
96 { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_Hexagon_LO16", 0, 32, 0 },
98 { "fixup_Hexagon_HI16", 0, 32, 0 },
99 { "fixup_Hexagon_32", 0, 32, 0 },
100 { "fixup_Hexagon_16", 0, 32, 0 },
101 { "fixup_Hexagon_8", 0, 32, 0 },
102 { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
103 { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
104 { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
105 { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
106 { "fixup_Hexagon_HL16", 0, 32, 0 },
107 { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
108 { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
109 { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110 { "fixup_Hexagon_32_6_X", 0, 32, 0 },
111 { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112 { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113 { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_Hexagon_16_X", 0, 32, 0 },
117 { "fixup_Hexagon_12_X", 0, 32, 0 },
118 { "fixup_Hexagon_11_X", 0, 32, 0 },
119 { "fixup_Hexagon_10_X", 0, 32, 0 },
120 { "fixup_Hexagon_9_X", 0, 32, 0 },
121 { "fixup_Hexagon_8_X", 0, 32, 0 },
122 { "fixup_Hexagon_7_X", 0, 32, 0 },
123 { "fixup_Hexagon_6_X", 0, 32, 0 },
124 { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
125 { "fixup_Hexagon_COPY", 0, 32, 0 },
126 { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
127 { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
128 { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
129 { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
130 { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
131 { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
132 { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
133 { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
134 { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
135 { "fixup_Hexagon_GOT_32", 0, 32, 0 },
136 { "fixup_Hexagon_GOT_16", 0, 32, 0 },
137 { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
138 { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
139 { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
140 { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
141 { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
142 { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
143 { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
144 { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
145 { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
146 { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
147 { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
148 { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
149 { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
150 { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
151 { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
152 { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
153 { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
154 { "fixup_Hexagon_IE_32", 0, 32, 0 },
155 { "fixup_Hexagon_IE_16", 0, 32, 0 },
156 { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
157 { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
158 { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
159 { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
160 { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
161 { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
162 { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
163 { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
164 { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
165 { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
166 { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
167 { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
168 { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
169 { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
170 { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
171 { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
172 { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
173 { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
174 { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
175 { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
176 { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
177 { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
178 { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
179 { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
180 { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
181 { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
182 { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
183 { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
184 { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
185 { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
186 { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
187 { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
188 { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
189 { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
190 { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
191 { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
194 if (Kind < FirstTargetFixupKind)
195 return MCAsmBackend::getFixupKindInfo(Kind);
197 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
199 return Infos[Kind - FirstTargetFixupKind];
202 /// processFixupValue - Target hook to adjust the literal value of a fixup
203 /// if necessary. IsResolved signals whether the caller believes a relocation
204 /// is needed; the target can modify the value. The default does nothing.
205 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
206 const MCFixup &Fixup, const MCFragment *DF,
207 const MCValue &Target, uint64_t &Value,
208 bool &IsResolved) override {
209 MCFixupKind Kind = Fixup.getKind();
211 switch((unsigned)Kind) {
213 llvm_unreachable("Unknown Fixup Kind!");
215 case fixup_Hexagon_LO16:
216 case fixup_Hexagon_HI16:
217 case fixup_Hexagon_16:
218 case fixup_Hexagon_8:
219 case fixup_Hexagon_GPREL16_0:
220 case fixup_Hexagon_GPREL16_1:
221 case fixup_Hexagon_GPREL16_2:
222 case fixup_Hexagon_GPREL16_3:
223 case fixup_Hexagon_HL16:
224 case fixup_Hexagon_32_6_X:
225 case fixup_Hexagon_16_X:
226 case fixup_Hexagon_12_X:
227 case fixup_Hexagon_11_X:
228 case fixup_Hexagon_10_X:
229 case fixup_Hexagon_9_X:
230 case fixup_Hexagon_8_X:
231 case fixup_Hexagon_7_X:
232 case fixup_Hexagon_6_X:
233 case fixup_Hexagon_COPY:
234 case fixup_Hexagon_GLOB_DAT:
235 case fixup_Hexagon_JMP_SLOT:
236 case fixup_Hexagon_RELATIVE:
237 case fixup_Hexagon_PLT_B22_PCREL:
238 case fixup_Hexagon_GOTREL_LO16:
239 case fixup_Hexagon_GOTREL_HI16:
240 case fixup_Hexagon_GOTREL_32:
241 case fixup_Hexagon_GOT_LO16:
242 case fixup_Hexagon_GOT_HI16:
243 case fixup_Hexagon_GOT_32:
244 case fixup_Hexagon_GOT_16:
245 case fixup_Hexagon_DTPMOD_32:
246 case fixup_Hexagon_DTPREL_LO16:
247 case fixup_Hexagon_DTPREL_HI16:
248 case fixup_Hexagon_DTPREL_32:
249 case fixup_Hexagon_DTPREL_16:
250 case fixup_Hexagon_GD_PLT_B22_PCREL:
251 case fixup_Hexagon_LD_PLT_B22_PCREL:
252 case fixup_Hexagon_GD_GOT_LO16:
253 case fixup_Hexagon_GD_GOT_HI16:
254 case fixup_Hexagon_GD_GOT_32:
255 case fixup_Hexagon_GD_GOT_16:
256 case fixup_Hexagon_LD_GOT_LO16:
257 case fixup_Hexagon_LD_GOT_HI16:
258 case fixup_Hexagon_LD_GOT_32:
259 case fixup_Hexagon_LD_GOT_16:
260 case fixup_Hexagon_IE_LO16:
261 case fixup_Hexagon_IE_HI16:
262 case fixup_Hexagon_IE_32:
263 case fixup_Hexagon_IE_16:
264 case fixup_Hexagon_IE_GOT_LO16:
265 case fixup_Hexagon_IE_GOT_HI16:
266 case fixup_Hexagon_IE_GOT_32:
267 case fixup_Hexagon_IE_GOT_16:
268 case fixup_Hexagon_TPREL_LO16:
269 case fixup_Hexagon_TPREL_HI16:
270 case fixup_Hexagon_TPREL_32:
271 case fixup_Hexagon_TPREL_16:
272 case fixup_Hexagon_GOTREL_32_6_X:
273 case fixup_Hexagon_GOTREL_16_X:
274 case fixup_Hexagon_GOTREL_11_X:
275 case fixup_Hexagon_GOT_32_6_X:
276 case fixup_Hexagon_GOT_16_X:
277 case fixup_Hexagon_GOT_11_X:
278 case fixup_Hexagon_DTPREL_32_6_X:
279 case fixup_Hexagon_DTPREL_16_X:
280 case fixup_Hexagon_DTPREL_11_X:
281 case fixup_Hexagon_GD_GOT_32_6_X:
282 case fixup_Hexagon_GD_GOT_16_X:
283 case fixup_Hexagon_GD_GOT_11_X:
284 case fixup_Hexagon_LD_GOT_32_6_X:
285 case fixup_Hexagon_LD_GOT_16_X:
286 case fixup_Hexagon_LD_GOT_11_X:
287 case fixup_Hexagon_IE_32_6_X:
288 case fixup_Hexagon_IE_16_X:
289 case fixup_Hexagon_IE_GOT_32_6_X:
290 case fixup_Hexagon_IE_GOT_16_X:
291 case fixup_Hexagon_IE_GOT_11_X:
292 case fixup_Hexagon_TPREL_32_6_X:
293 case fixup_Hexagon_TPREL_16_X:
294 case fixup_Hexagon_TPREL_11_X:
295 case fixup_Hexagon_32_PCREL:
296 case fixup_Hexagon_6_PCREL_X:
297 case fixup_Hexagon_23_REG:
298 case fixup_Hexagon_27_REG:
299 case fixup_Hexagon_GD_PLT_B22_PCREL_X:
300 case fixup_Hexagon_GD_PLT_B32_PCREL_X:
301 case fixup_Hexagon_LD_PLT_B22_PCREL_X:
302 case fixup_Hexagon_LD_PLT_B32_PCREL_X:
303 // These relocations should always have a relocation recorded
307 case fixup_Hexagon_B22_PCREL:
308 //IsResolved = false;
311 case fixup_Hexagon_B13_PCREL:
312 case fixup_Hexagon_B13_PCREL_X:
313 case fixup_Hexagon_B32_PCREL_X:
314 case fixup_Hexagon_B22_PCREL_X:
315 case fixup_Hexagon_B15_PCREL:
316 case fixup_Hexagon_B15_PCREL_X:
317 case fixup_Hexagon_B9_PCREL:
318 case fixup_Hexagon_B9_PCREL_X:
319 case fixup_Hexagon_B7_PCREL:
320 case fixup_Hexagon_B7_PCREL_X:
329 case fixup_Hexagon_32:
330 // Leave these relocations alone as they are used for EH.
335 /// getFixupKindNumBytes - The number of bytes the fixup may change.
336 static unsigned getFixupKindNumBytes(unsigned Kind) {
345 case FK_Data_4: // this later gets mapped to R_HEX_32
346 case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
347 case fixup_Hexagon_32:
348 case fixup_Hexagon_B32_PCREL_X:
349 case fixup_Hexagon_B22_PCREL:
350 case fixup_Hexagon_B22_PCREL_X:
351 case fixup_Hexagon_B15_PCREL:
352 case fixup_Hexagon_B15_PCREL_X:
353 case fixup_Hexagon_B13_PCREL:
354 case fixup_Hexagon_B13_PCREL_X:
355 case fixup_Hexagon_B9_PCREL:
356 case fixup_Hexagon_B9_PCREL_X:
357 case fixup_Hexagon_B7_PCREL:
358 case fixup_Hexagon_B7_PCREL_X:
359 case fixup_Hexagon_GD_PLT_B32_PCREL_X:
360 case fixup_Hexagon_LD_PLT_B32_PCREL_X:
365 // Make up for left shift when encoding the operand.
366 static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
367 switch((unsigned)Kind) {
371 case fixup_Hexagon_B7_PCREL:
372 case fixup_Hexagon_B9_PCREL:
373 case fixup_Hexagon_B13_PCREL:
374 case fixup_Hexagon_B15_PCREL:
375 case fixup_Hexagon_B22_PCREL:
379 case fixup_Hexagon_B7_PCREL_X:
380 case fixup_Hexagon_B9_PCREL_X:
381 case fixup_Hexagon_B13_PCREL_X:
382 case fixup_Hexagon_B15_PCREL_X:
383 case fixup_Hexagon_B22_PCREL_X:
387 case fixup_Hexagon_B32_PCREL_X:
388 case fixup_Hexagon_GD_PLT_B32_PCREL_X:
389 case fixup_Hexagon_LD_PLT_B32_PCREL_X:
396 void HandleFixupError(const int bits, const int align_bits,
397 const int64_t FixupValue, const char *fixupStr) const {
398 // Error: value 1124 out of range: -1024-1023 when resolving
399 // symbol in file xprtsock.S
400 const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
401 const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
402 std::stringstream errStr;
403 errStr << "\nError: value " <<
406 IntMin.getSExtValue() <<
408 IntMax.getSExtValue() <<
409 " when resolving " <<
412 llvm_unreachable(errStr.str().c_str());
415 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
416 /// data fragment, at the offset specified by the fixup and following the
417 /// fixup kind as appropriate.
418 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
419 uint64_t FixupValue, bool IsPCRel,
420 MCContext &Ctx) const override {
422 // When FixupValue is 0 the relocation is external and there
423 // is nothing for us to do.
424 if (!FixupValue) return;
426 MCFixupKind Kind = Fixup.getKind();
431 // LLVM gives us an encoded value, we have to convert it back
432 // to a real offset before we can use it.
433 uint32_t Offset = Fixup.getOffset();
434 unsigned NumBytes = getFixupKindNumBytes(Kind);
435 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
436 char *InstAddr = Data + Offset;
438 Value = adjustFixupValue(Kind, FixupValue);
441 int sValue = (int)Value;
443 switch((unsigned)Kind) {
447 case fixup_Hexagon_B7_PCREL:
448 if (!(isIntN(7, sValue)))
449 HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
450 case fixup_Hexagon_B7_PCREL_X:
451 InstMask = 0x00001f18; // Word32_B7
452 Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
453 ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
456 case fixup_Hexagon_B9_PCREL:
457 if (!(isIntN(9, sValue)))
458 HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
459 case fixup_Hexagon_B9_PCREL_X:
460 InstMask = 0x003000fe; // Word32_B9
461 Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
462 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
465 // Since the existing branches that use this relocation cannot be
466 // extended, they should only be fixed up if the target is within range.
467 case fixup_Hexagon_B13_PCREL:
468 if (!(isIntN(13, sValue)))
469 HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
470 case fixup_Hexagon_B13_PCREL_X:
471 InstMask = 0x00202ffe; // Word32_B13
472 Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
473 (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
474 ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
477 case fixup_Hexagon_B15_PCREL:
478 if (!(isIntN(15, sValue)))
479 HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
480 case fixup_Hexagon_B15_PCREL_X:
481 InstMask = 0x00df20fe; // Word32_B15
482 Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
483 (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
484 (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
485 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
488 case fixup_Hexagon_B22_PCREL:
489 if (!(isIntN(22, sValue)))
490 HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
491 case fixup_Hexagon_B22_PCREL_X:
492 InstMask = 0x01ff3ffe; // Word32_B22
493 Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
494 ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
497 case fixup_Hexagon_B32_PCREL_X:
498 InstMask = 0x0fff3fff; // Word32_X26
499 Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
500 (Value & 0x3fff); // Value 13-0 = Target 13-0
506 case fixup_Hexagon_32:
507 InstMask = 0xffffffff; // Word32
512 DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" <<
513 (unsigned)Kind << ")\n");
514 DEBUG(uint32_t OldData = 0;
515 for (unsigned i = 0; i < NumBytes; i++)
516 OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
517 dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) <<
518 ": AValue=0x"; dbgs().write_hex(FixupValue) <<
519 ": Offset=" << Offset <<
520 ": Size=" << DataSize <<
521 ": OInst=0x"; dbgs().write_hex(OldData) <<
522 ": Reloc=0x"; dbgs().write_hex(Reloc););
524 // For each byte of the fragment that the fixup touches, mask in the
525 // bits from the fixup value. The Value has been "split up" into the
526 // appropriate bitfields above.
527 for (unsigned i = 0; i < NumBytes; i++){
528 InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
529 InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
532 DEBUG(uint32_t NewData = 0;
533 for (unsigned i = 0; i < NumBytes; i++)
534 NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
535 dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
538 bool isInstRelaxable(MCInst const &HMI) const {
539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
540 bool Relaxable = false;
541 // Branches and loop-setup insns are handled as necessary by relaxation.
542 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
543 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
545 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ &&
547 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
548 HMI.getOpcode() != Hexagon::C4_addipc))
549 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
551 MCOperand const &Operand =
552 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
553 if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr()))
560 /// MayNeedRelaxation - Check whether the given instruction may need
563 /// \param Inst - The instruction to test.
564 bool mayNeedRelaxation(MCInst const &Inst) const override {
568 /// fixupNeedsRelaxation - Target specific predicate for whether a given
569 /// fixup requires the associated instruction to be relaxed.
570 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
572 const MCRelaxableFragment *DF,
573 const MCAsmLayout &Layout) const override {
574 MCInst const &MCB = DF->getInst();
575 assert(HexagonMCInstrInfo::isBundle(MCB));
577 *RelaxTarget = nullptr;
578 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
579 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
580 bool Relaxable = isInstRelaxable(MCI);
581 if (Relaxable == false)
583 // If we cannot resolve the fixup value, it requires relaxation.
585 switch ((unsigned)Fixup.getKind()) {
586 case fixup_Hexagon_B22_PCREL:
587 // GetFixupCount assumes B22 won't relax
592 case fixup_Hexagon_B13_PCREL:
593 case fixup_Hexagon_B15_PCREL:
594 case fixup_Hexagon_B9_PCREL:
595 case fixup_Hexagon_B7_PCREL: {
596 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
599 setExtender(Layout.getAssembler().getContext());
609 MCFixupKind Kind = Fixup.getKind();
610 int64_t sValue = Value;
613 switch ((unsigned)Kind) {
614 case fixup_Hexagon_B7_PCREL:
617 case fixup_Hexagon_B9_PCREL:
620 case fixup_Hexagon_B15_PCREL:
623 case fixup_Hexagon_B22_PCREL:
627 maxValue = INT64_MAX;
631 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
634 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
637 setExtender(Layout.getAssembler().getContext());
645 /// Simple predicate for targets where !Resolved implies requiring relaxation
646 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
647 const MCRelaxableFragment *DF,
648 const MCAsmLayout &Layout) const override {
649 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
652 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
653 MCInst &Res) const override {
654 assert(HexagonMCInstrInfo::isBundle(Inst) &&
655 "Hexagon relaxInstruction only works on bundles");
657 Res = HexagonMCInstrInfo::createBundle();
658 // Copy the results into the bundle.
660 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
661 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
663 // if immediate extender needed, add it in
664 if (*RelaxTarget == &CrntHMI) {
666 assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) &&
667 "No room to insert extender for relaxation");
669 MCInst *HMIx = takeExtender();
670 *HMIx = HexagonMCInstrInfo::deriveExtender(
672 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI));
673 Res.addOperand(MCOperand::createInst(HMIx));
674 *RelaxTarget = nullptr;
676 // now copy over the original instruction(the one we may have extended)
677 Res.addOperand(MCOperand::createInst(I.getInst()));
680 assert(Update && "Didn't find relaxation target");
683 bool writeNopData(uint64_t Count,
684 MCObjectWriter * OW) const override {
685 static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
686 ParseIn = 0x00004000, // In packet parse-bits.
687 ParseEnd = 0x0000c000; // End of packet parse-bits.
689 while(Count % HEXAGON_INSTR_SIZE) {
690 DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" <<
691 Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n");
697 Count -= HEXAGON_INSTR_SIZE;
698 // Close the packet whenever a multiple of the maximum packet size remains
699 uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
701 OW->write32(Nopcode | ParseBits);
706 void finishLayout(MCAssembler const &Asm,
707 MCAsmLayout &Layout) const override {
708 for (auto I : Layout.getSectionOrder()) {
709 auto &Fragments = I->getFragmentList();
710 for (auto &J : Fragments) {
711 switch (J.getKind()) {
714 case MCFragment::FT_Align: {
715 auto Size = Asm.computeFragmentSize(Layout, J);
716 for (auto K = J.getIterator();
717 K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
719 switch (K->getKind()) {
722 case MCFragment::FT_Align: {
723 // Don't pad before other alignments
727 case MCFragment::FT_Relaxable: {
728 MCContext &Context = Asm.getContext();
729 auto &RF = cast<MCRelaxableFragment>(*K);
730 auto &Inst = const_cast<MCInst &>(RF.getInst());
731 while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) {
732 MCInst *Nop = new (Context) MCInst;
733 Nop->setOpcode(Hexagon::A2_nop);
734 Inst.addOperand(MCOperand::createInst(Nop));
736 if (!HexagonMCChecker(
737 Context, *MCII, RF.getSubtargetInfo(), Inst,
738 *Context.getRegisterInfo(), false)
740 Inst.erase(Inst.end() - 1);
744 bool Error = HexagonMCShuffle(Context, true, *MCII,
745 RF.getSubtargetInfo(), Inst);
748 ReplaceInstruction(Asm.getEmitter(), RF, Inst);
749 Layout.invalidateFragmentsFrom(&RF);
750 Size = 0; // Only look back one instruction
760 }; // class HexagonAsmBackend
765 MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
766 MCRegisterInfo const & /*MRI*/,
767 const Triple &TT, StringRef CPU,
768 const MCTargetOptions &Options) {
769 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
771 StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU);
772 return new HexagonAsmBackend(T, TT, OSABI, CPUString);