1 //===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the checking of insns inside a bundle according to the
11 // packet constraint rules of the Hexagon ISA.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonMCChecker.h"
17 #include "HexagonBaseInfo.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
27 static cl::opt<bool> RelaxNVChecks("relax-nv-checks", cl::init(false),
28 cl::ZeroOrMore, cl::Hidden, cl::desc("Relax checks of new-value validity"));
30 const HexagonMCChecker::PredSense
31 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
33 void HexagonMCChecker::init() {
34 // Initialize read-only registers set.
35 ReadOnly.insert(Hexagon::PC);
37 // Figure out the loop-registers definitions.
38 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
39 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
40 Defs[Hexagon::LC0].insert(Unconditional);
42 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
43 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
44 Defs[Hexagon::LC1].insert(Unconditional);
47 if (HexagonMCInstrInfo::isBundle(MCB))
49 for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
56 void HexagonMCChecker::init(MCInst const& MCI) {
57 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
58 unsigned PredReg = Hexagon::NoRegister;
61 // Get used registers.
62 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
63 if (MCI.getOperand(i).isReg()) {
64 unsigned R = MCI.getOperand(i).getReg();
66 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
67 // Note an used predicate register.
69 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
71 // Note use of new predicate register.
72 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
73 NewPreds.insert(PredReg);
76 // Note register use. Super-registers are not tracked directly,
77 // but their components.
78 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
81 if (!MCSubRegIterator(*SRI, &RI).isValid())
82 // Skip super-registers used indirectly.
86 // Get implicit register definitions.
87 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
88 for (; *ImpDef; ++ImpDef) {
91 if (Hexagon::R31 != R && MCID.isCall())
92 // Any register other than the LR and the PC are actually volatile ones
93 // as defined by the ABI, not modified implicitly by the call insn.
96 // Branches are the only insns that can change the PC,
97 // otherwise a read-only register.
100 if (Hexagon::USR_OVF == R)
101 // Many insns change the USR implicitly, but only one or another flag.
102 // The instruction table models the USR.OVF flag, which can be implicitly
103 // modified more than once, but cannot be modified in the same packet
104 // with an instruction that modifies is explicitly. Deal with such situ-
105 // ations individually.
107 else if (isPredicateRegister(R) &&
108 HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
109 // Include implicit late predicates.
112 Defs[R].insert(PredSense(PredReg, isTrue));
115 // Figure out explicit register definitions.
116 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
117 unsigned R = MCI.getOperand(i).getReg(),
118 S = Hexagon::NoRegister;
119 // USR has subregisters (while C8 does not for technical reasons), so
120 // reset R to USR, since we know how to handle multiple defs of USR,
121 // taking into account its subregisters.
122 if (R == Hexagon::C8)
125 // Note register definitions, direct ones as well as indirect side-effects.
126 // Super-registers are not tracked directly, but their components.
127 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
130 if (MCSubRegIterator(*SRI, &RI).isValid())
131 // Skip super-registers defined indirectly.
136 // Avoid scoring the defined register multiple times.
139 // Note that the defined register has already been scored.
143 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
144 // P3:0 is a special case, since multiple predicate register definitions
145 // in a packet is allowed as the equivalent of their logical "and".
146 // Only an explicit definition of P3:0 is noted as such; if a
147 // side-effect, then note as a soft definition.
148 SoftDefs.insert(*SRI);
149 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI))
150 // Some insns produce predicates too late to be used in the same packet.
151 LatePreds.insert(*SRI);
152 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD)
153 // Current loads should be used in the same packet.
154 // TODO: relies on the impossibility of a current and a temporary loads
155 // in the same packet.
156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));
157 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD)
158 // Temporary loads should be used in the same packet, but don't commit
159 // results, so it should be disregarded if another insn changes the same
161 // TODO: relies on the impossibility of a current and a temporary loads
162 // in the same packet.
163 TmpDefs.insert(*SRI);
164 else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) )
165 // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
166 // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
169 Defs[*SRI].insert(PredSense(PredReg, isTrue));
173 // Figure out register definitions that produce new values.
174 if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) {
175 unsigned R = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
177 if (HexagonMCInstrInfo::isCompound(MCII, MCI))
178 compoundRegisterMap(R); // Compound insns have a limited register range.
180 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
183 if (!MCSubRegIterator(*SRI, &RI).isValid())
184 // No super-registers defined indirectly.
185 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
186 HexagonMCInstrInfo::isFloat(MCII, MCI)));
188 // For fairly unique 2-dot-new producers, example:
189 // vdeal(V1, V9, R0) V1.new and V9.new can be used by consumers.
190 if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) {
191 unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg();
193 for(MCRegAliasIterator SRI(R2, &RI, !MCSubRegIterator(R2, &RI).isValid());
196 if (!MCSubRegIterator(*SRI, &RI).isValid())
197 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
198 HexagonMCInstrInfo::isFloat(MCII, MCI)));
202 // Figure out definitions of new predicate registers.
203 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
204 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
205 if (MCI.getOperand(i).isReg()) {
206 unsigned P = MCI.getOperand(i).getReg();
208 if (isPredicateRegister(P))
212 // Figure out uses of new values.
213 if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) {
214 unsigned N = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg();
216 if (!MCSubRegIterator(N, &RI).isValid()) {
217 // Super-registers cannot use new values.
219 NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV);
221 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
226 HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx,
227 MCRegisterInfo const &ri)
228 : MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),
229 bLoadErrInfo(false) {
233 bool HexagonMCChecker::check() {
234 bool chkB = checkBranches();
235 bool chkP = checkPredicates();
236 bool chkNV = checkNewValues();
237 bool chkR = checkRegisters();
238 bool chkS = checkSolo();
239 bool chkSh = checkShuffle();
240 bool chkSl = checkSlots();
241 bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;
246 bool HexagonMCChecker::checkSlots()
249 unsigned slotsUsed = 0;
250 for (auto HMI: HexagonMCInstrInfo::bundleInstructions(MCBDX)) {
251 MCInst const& MCI = *HMI.getInst();
252 if (HexagonMCInstrInfo::isImmext(MCI))
254 if (HexagonMCInstrInfo::isDuplex(MCII, MCI))
260 if (slotsUsed > HEXAGON_PACKET_SIZE) {
261 HexagonMCErrInfo errInfo;
262 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NOSLOTS);
269 // Check legal use of branches.
270 bool HexagonMCChecker::checkBranches() {
271 HexagonMCErrInfo errInfo;
272 if (HexagonMCInstrInfo::isBundle(MCB)) {
273 bool hasConditional = false;
274 unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0,
275 NewValueBranches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE,
276 Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE;
278 for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset;
279 i < MCB.size(); ++i) {
280 MCInst const &MCI = *MCB.begin()[i].getInst();
282 if (HexagonMCInstrInfo::isImmext(MCI))
284 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() ||
285 HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) {
287 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() &&
288 HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
289 ++NewIndirectBranches;
290 if (HexagonMCInstrInfo::isNewValue(MCII, MCI))
293 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) ||
294 HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) {
295 hasConditional = true;
296 Conditional = i; // Record the position of the conditional branch.
298 Unconditional = i; // Record the position of the unconditional branch.
301 if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() &&
302 HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad())
306 if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too?
307 if (HexagonMCInstrInfo::isInnerLoop(MCB) ||
308 HexagonMCInstrInfo::isOuterLoop(MCB)) {
309 // Error out if there's any branch in a loop-end packet.
310 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_ENDLOOP, Hexagon::PC);
315 if (!hasConditional || Conditional > Unconditional) {
316 // Error out if more than one unconditional branch or
317 // the conditional branch appears after the unconditional one.
318 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_BRANCHES);
327 // Check legal use of predicate registers.
328 bool HexagonMCChecker::checkPredicates() {
329 HexagonMCErrInfo errInfo;
330 // Check for proper use of new predicate registers.
331 for (const auto& I : NewPreds) {
334 if (!Defs.count(P) || LatePreds.count(P)) {
335 // Error out if the new predicate register is not defined,
337 // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
338 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWP, P);
344 // Check for proper use of auto-anded of predicate registers.
345 for (const auto& I : LatePreds) {
348 if (LatePreds.count(P) > 1 || Defs.count(P)) {
349 // Error out if predicate register defined "late" multiple times or
350 // defined late and regularly defined
351 // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
352 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, P);
361 // Check legal use of new values.
362 bool HexagonMCChecker::checkNewValues() {
363 HexagonMCErrInfo errInfo;
364 memset(&errInfo, 0, sizeof(errInfo));
365 for (auto& I : NewUses) {
366 unsigned R = I.first;
367 NewSense &US = I.second;
369 if (!hasValidNewValueDef(US, NewDefs[R])) {
370 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_NEWV, R);
379 // Check for legal register uses and definitions.
380 bool HexagonMCChecker::checkRegisters() {
381 HexagonMCErrInfo errInfo;
382 // Check for proper register definitions.
383 for (const auto& I : Defs) {
384 unsigned R = I.first;
386 if (ReadOnly.count(R)) {
387 // Error out for definitions of read-only registers.
388 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_READONLY, R);
392 if (isLoopRegister(R) && Defs.count(R) > 1 &&
393 (HexagonMCInstrInfo::isInnerLoop(MCB) ||
394 HexagonMCInstrInfo::isOuterLoop(MCB))) {
395 // Error out for definitions of loop registers at the end of a loop.
396 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_LOOP, R);
400 if (SoftDefs.count(R)) {
401 // Error out for explicit changes to registers also weakly defined
402 // (e.g., "{ usr = r0; r0 = sfadd(...) }").
403 unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
404 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
405 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);
409 if (!isPredicateRegister(R) && Defs[R].size() > 1) {
410 // Check for multiple register definitions.
411 PredSet &PM = Defs[R];
413 // Check for multiple unconditional register definitions.
414 if (PM.count(Unconditional)) {
415 // Error out on an unconditional change when there are any other
416 // changes, conditional or not.
417 unsigned UsrR = Hexagon::USR;
418 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
419 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, BadR);
423 // Check for multiple conditional register definitions.
424 for (const auto& J : PM) {
427 // Check for multiple uses of the same condition.
428 if (PM.count(P) > 1) {
429 // Error out on conditional changes based on the same predicate
430 // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
431 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);
435 // Check for the use of the complementary condition.
436 P.second = !P.second;
437 if (PM.count(P) && PM.size() > 2) {
438 // Error out on conditional changes based on the same predicate
440 // (e.g., "{ if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =... }").
441 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_REGISTERS, R);
449 // Check for use of current definitions.
450 for (const auto& I : CurDefs) {
453 if (!Uses.count(R)) {
454 // Warn on an unused current definition.
455 errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_CURRENT, R);
461 // Check for use of temporary definitions.
462 for (const auto& I : TmpDefs) {
465 if (!Uses.count(R)) {
466 // special case for vhist
467 bool vHistFound = false;
468 for (auto const&HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
469 if(llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) == HexagonII::TypeCVI_HIST) {
470 vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
474 // Warn on an unused temporary definition.
475 if (vHistFound == false) {
476 errInfo.setWarning(HexagonMCErrInfo::CHECK_WARN_TEMPORARY, R);
486 // Check for legal use of solo insns.
487 bool HexagonMCChecker::checkSolo() {
488 HexagonMCErrInfo errInfo;
489 if (HexagonMCInstrInfo::isBundle(MCB) &&
490 HexagonMCInstrInfo::bundleSize(MCB) > 1) {
491 for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
492 if (llvm::HexagonMCInstrInfo::isSolo(MCII, *I.getInst())) {
493 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SOLO);
503 bool HexagonMCChecker::checkShuffle() {
504 HexagonMCErrInfo errInfo;
505 // Branch info is lost when duplexing. The unduplexed insns must be
506 // checked and only branch errors matter for this case.
507 HexagonMCShuffler MCS(MCII, STI, MCB);
509 if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR_BRANCHES) {
510 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
511 errInfo.setShuffleError(MCS.getError());
516 HexagonMCShuffler MCSDX(MCII, STI, MCBDX);
517 if (!MCSDX.check()) {
518 errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
519 errInfo.setShuffleError(MCSDX.getError());
526 void HexagonMCChecker::compoundRegisterMap(unsigned& Register) {
531 Register = Hexagon::R23;
534 Register = Hexagon::R22;
537 Register = Hexagon::R21;
540 Register = Hexagon::R20;
543 Register = Hexagon::R19;
546 Register = Hexagon::R18;
549 Register = Hexagon::R17;
552 Register = Hexagon::R16;
557 bool HexagonMCChecker::hasValidNewValueDef(const NewSense &Use,
558 const NewSenseList &Defs) const {
559 bool Strict = !RelaxNVChecks;
561 for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
562 const NewSense &Def = Defs[i];
563 // NVJ cannot use a new FP value [7.6.1]
564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0))
566 // If the definition was not predicated, then it does not matter if
568 if (Def.PredReg == 0)
570 // With the strict checks, both the definition and the use must be
571 // predicated on the same register and condition.
573 if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond)
576 // With the relaxed checks, if the definition was predicated, the only
577 // detectable violation is if the use is predicated on the opposing
578 // condition, otherwise, it's ok.
579 if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond)