1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "MCTargetDesc/HexagonBaseInfo.h"
12 #include "MCTargetDesc/HexagonFixupKinds.h"
13 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/EndianStream.h"
26 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mccodeemitter"
31 using namespace Hexagon;
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38 Extended(new bool(false)), CurrentBundle(new MCInst const *),
39 CurrentIndex(new size_t(0)) {}
41 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last,
43 MCInst const &MCI) const {
44 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
45 if (*CurrentIndex == 0) {
46 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
48 assert(*CurrentIndex != Last);
49 return HexagonII::INST_PARSE_LOOP_END;
52 if (*CurrentIndex == 1) {
53 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
55 assert(*CurrentIndex != Last);
56 return HexagonII::INST_PARSE_LOOP_END;
60 assert(*CurrentIndex == Last);
61 return HexagonII::INST_PARSE_DUPLEX;
63 if(*CurrentIndex == Last)
64 return HexagonII::INST_PARSE_PACKET_END;
65 return HexagonII::INST_PARSE_NOT_END;
68 /// EncodeInstruction - Emit the bundle
69 void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const {
72 MCInst &HMB = const_cast<MCInst &>(MI);
74 assert(HexagonMCInstrInfo::isBundle(HMB));
75 DEBUG(dbgs() << "Encoding bundle\n";);
80 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
81 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
82 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
83 verifyInstructionPredicates(HMI,
84 computeAvailableFeatures(STI.getFeatureBits()));
86 EncodeSingleInstruction(HMI, OS, Fixups, STI,
87 parseBits(Last, HMB, HMI));
88 *Extended = HexagonMCInstrInfo::isImmext(HMI);
89 *Addend += HEXAGON_INSTR_SIZE;
95 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
97 if (Consumer == Producer)
99 if (Consumer == Producer2)
101 // Calculate if we're a single vector consumer referencing a double producer
102 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
103 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
104 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
108 /// EncodeSingleInstruction - Emit a single
109 void HexagonMCCodeEmitter::EncodeSingleInstruction(
110 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
111 const MCSubtargetInfo &STI, uint32_t Parse) const {
112 assert(!HexagonMCInstrInfo::isBundle(MI));
115 // Pseudo instructions don't get encoded and shouldn't be here
116 // in the first place!
117 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
118 "pseudo-instruction found");
119 DEBUG(dbgs() << "Encoding insn"
120 " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
123 Binary = getBinaryCodeForInstr(MI, Fixups, STI);
124 // Check for unimplemented instructions. Immediate extenders
125 // are encoded as zero, so they need to be accounted for.
127 MI.getOpcode() != DuplexIClass0 &&
128 MI.getOpcode() != A4_ext) {
129 DEBUG(dbgs() << "Unimplemented inst: "
130 " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
132 llvm_unreachable("Unimplemented Instruction");
136 // if we need to emit a duplexed instruction
137 if (MI.getOpcode() >= Hexagon::DuplexIClass0 &&
138 MI.getOpcode() <= Hexagon::DuplexIClassF) {
139 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
140 "Emitting duplex without duplex parse bits");
141 unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
142 // 29 is the bit position.
143 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
144 // Last bit is moved to bit position 13
145 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
147 const MCInst *subInst0 = MI.getOperand(0).getInst();
148 const MCInst *subInst1 = MI.getOperand(1).getInst();
150 // get subinstruction slot 0
151 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
152 // get subinstruction slot 1
153 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
155 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
157 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
162 void raise_relocation_error(unsigned bits, unsigned kind) {
165 llvm::raw_string_ostream Stream(Text);
166 Stream << "Unrecognized relocation combination bits: " << bits
167 << " kind: " << kind;
169 report_fatal_error(Text);
173 /// getFixupNoBits - Some insns are not extended and thus have no
174 /// bits. These cases require a more brute force method for determining
175 /// the correct relocation.
176 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
177 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
178 const MCSymbolRefExpr::VariantKind kind) const {
179 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
180 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
182 if (insnType == HexagonII::TypeEXTENDER) {
184 case MCSymbolRefExpr::VK_GOTREL:
185 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
186 case MCSymbolRefExpr::VK_GOT:
187 return Hexagon::fixup_Hexagon_GOT_32_6_X;
188 case MCSymbolRefExpr::VK_TPREL:
189 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
190 case MCSymbolRefExpr::VK_DTPREL:
191 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
192 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
193 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
194 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
195 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
196 case MCSymbolRefExpr::VK_Hexagon_IE:
197 return Hexagon::fixup_Hexagon_IE_32_6_X;
198 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
199 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
200 case MCSymbolRefExpr::VK_Hexagon_PCREL:
201 return Hexagon::fixup_Hexagon_B32_PCREL_X;
202 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
203 return Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X;
204 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
205 return Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X;
207 case MCSymbolRefExpr::VK_None: {
208 auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
209 for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) {
210 if (I->getInst() == &MI) {
211 const MCInst &NextI = *(I+1)->getInst();
212 const MCInstrDesc &D = HexagonMCInstrInfo::getDesc(MCII, NextI);
213 if (D.isBranch() || D.isCall() ||
214 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
215 return Hexagon::fixup_Hexagon_B32_PCREL_X;
216 return Hexagon::fixup_Hexagon_32_6_X;
219 raise_relocation_error(0, kind);
222 raise_relocation_error(0, kind);
224 } else if (MCID.isBranch())
225 return Hexagon::fixup_Hexagon_B13_PCREL;
227 switch (MCID.getOpcode()) {
229 case Hexagon::A2_tfrih:
231 case MCSymbolRefExpr::VK_GOT:
232 return Hexagon::fixup_Hexagon_GOT_HI16;
233 case MCSymbolRefExpr::VK_GOTREL:
234 return Hexagon::fixup_Hexagon_GOTREL_HI16;
235 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
236 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
237 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
238 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
239 case MCSymbolRefExpr::VK_Hexagon_IE:
240 return Hexagon::fixup_Hexagon_IE_HI16;
241 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
242 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
243 case MCSymbolRefExpr::VK_TPREL:
244 return Hexagon::fixup_Hexagon_TPREL_HI16;
245 case MCSymbolRefExpr::VK_DTPREL:
246 return Hexagon::fixup_Hexagon_DTPREL_HI16;
247 case MCSymbolRefExpr::VK_None:
248 return Hexagon::fixup_Hexagon_HI16;
250 raise_relocation_error(0, kind);
254 case Hexagon::A2_tfril:
256 case MCSymbolRefExpr::VK_GOT:
257 return Hexagon::fixup_Hexagon_GOT_LO16;
258 case MCSymbolRefExpr::VK_GOTREL:
259 return Hexagon::fixup_Hexagon_GOTREL_LO16;
260 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
261 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
262 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
263 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
264 case MCSymbolRefExpr::VK_Hexagon_IE:
265 return Hexagon::fixup_Hexagon_IE_LO16;
266 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
267 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
268 case MCSymbolRefExpr::VK_TPREL:
269 return Hexagon::fixup_Hexagon_TPREL_LO16;
270 case MCSymbolRefExpr::VK_DTPREL:
271 return Hexagon::fixup_Hexagon_DTPREL_LO16;
272 case MCSymbolRefExpr::VK_None:
273 return Hexagon::fixup_Hexagon_LO16;
275 raise_relocation_error(0, kind);
278 // The only relocs left should be GP relative:
280 if (MCID.mayStore() || MCID.mayLoad()) {
281 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
283 if (*ImpUses != Hexagon::GP)
285 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
286 case HexagonII::MemAccessSize::ByteAccess:
287 return fixup_Hexagon_GPREL16_0;
288 case HexagonII::MemAccessSize::HalfWordAccess:
289 return fixup_Hexagon_GPREL16_1;
290 case HexagonII::MemAccessSize::WordAccess:
291 return fixup_Hexagon_GPREL16_2;
292 case HexagonII::MemAccessSize::DoubleWordAccess:
293 return fixup_Hexagon_GPREL16_3;
295 raise_relocation_error(0, kind);
299 raise_relocation_error(0, kind);
301 llvm_unreachable("Relocation exit not taken");
305 extern const MCInstrDesc HexagonInsts[];
309 bool isPCRel (unsigned Kind) {
311 case fixup_Hexagon_B22_PCREL:
312 case fixup_Hexagon_B15_PCREL:
313 case fixup_Hexagon_B7_PCREL:
314 case fixup_Hexagon_B13_PCREL:
315 case fixup_Hexagon_B9_PCREL:
316 case fixup_Hexagon_B32_PCREL_X:
317 case fixup_Hexagon_B22_PCREL_X:
318 case fixup_Hexagon_B15_PCREL_X:
319 case fixup_Hexagon_B13_PCREL_X:
320 case fixup_Hexagon_B9_PCREL_X:
321 case fixup_Hexagon_B7_PCREL_X:
322 case fixup_Hexagon_32_PCREL:
323 case fixup_Hexagon_PLT_B22_PCREL:
324 case fixup_Hexagon_GD_PLT_B22_PCREL:
325 case fixup_Hexagon_LD_PLT_B22_PCREL:
326 case fixup_Hexagon_GD_PLT_B22_PCREL_X:
327 case fixup_Hexagon_LD_PLT_B22_PCREL_X:
328 case fixup_Hexagon_6_PCREL_X:
336 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI) const
343 if (isa<HexagonMCExpr>(ME))
344 ME = &HexagonMCInstrInfo::getExpr(*ME);
346 if (ME->evaluateAsAbsolute(Value))
348 assert(ME->getKind() == MCExpr::SymbolRef ||
349 ME->getKind() == MCExpr::Binary);
350 if (ME->getKind() == MCExpr::Binary) {
351 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
352 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
353 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
356 Hexagon::Fixups FixupKind =
357 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
358 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
359 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
360 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
361 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
362 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
364 DEBUG(dbgs() << "----------------------------------------\n");
365 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
367 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
368 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
369 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
370 DEBUG(dbgs() << "----------------------------------------\n");
374 raise_relocation_error(bits, kind);
377 case MCSymbolRefExpr::VK_DTPREL:
378 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
379 : Hexagon::fixup_Hexagon_DTPREL_32;
381 case MCSymbolRefExpr::VK_GOT:
382 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
383 : Hexagon::fixup_Hexagon_GOT_32;
385 case MCSymbolRefExpr::VK_GOTREL:
386 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
387 : Hexagon::fixup_Hexagon_GOTREL_32;
389 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
390 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
391 : Hexagon::fixup_Hexagon_GD_GOT_32;
393 case MCSymbolRefExpr::VK_Hexagon_IE:
394 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
395 : Hexagon::fixup_Hexagon_IE_32;
397 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
398 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
399 : Hexagon::fixup_Hexagon_IE_GOT_32;
401 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
402 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
403 : Hexagon::fixup_Hexagon_LD_GOT_32;
405 case MCSymbolRefExpr::VK_Hexagon_PCREL:
406 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
408 case MCSymbolRefExpr::VK_None:
410 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
412 case MCSymbolRefExpr::VK_TPREL:
413 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
414 : Hexagon::fixup_Hexagon_TPREL_32;
417 raise_relocation_error(bits, kind);
423 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
424 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
425 : Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
427 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
428 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
429 : Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
431 case MCSymbolRefExpr::VK_None:
432 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
433 : Hexagon::fixup_Hexagon_B22_PCREL;
435 case MCSymbolRefExpr::VK_PLT:
436 FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL;
439 raise_relocation_error(bits, kind);
446 case MCSymbolRefExpr::VK_DTPREL:
447 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
449 case MCSymbolRefExpr::VK_GOT:
450 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
452 case MCSymbolRefExpr::VK_GOTREL:
453 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
455 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
456 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
458 case MCSymbolRefExpr::VK_Hexagon_IE:
459 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
461 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
462 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
464 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
465 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
467 case MCSymbolRefExpr::VK_None:
468 FixupKind = Hexagon::fixup_Hexagon_16_X;
470 case MCSymbolRefExpr::VK_TPREL:
471 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
474 raise_relocation_error(bits, kind);
478 case MCSymbolRefExpr::VK_None: {
479 if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr()))
480 FixupKind = Hexagon::fixup_Hexagon_27_REG;
482 if (MCID.mayStore() || MCID.mayLoad()) {
483 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
485 if (*ImpUses != Hexagon::GP)
487 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
488 case HexagonII::MemAccessSize::ByteAccess:
489 FixupKind = fixup_Hexagon_GPREL16_0;
491 case HexagonII::MemAccessSize::HalfWordAccess:
492 FixupKind = fixup_Hexagon_GPREL16_1;
494 case HexagonII::MemAccessSize::WordAccess:
495 FixupKind = fixup_Hexagon_GPREL16_2;
497 case HexagonII::MemAccessSize::DoubleWordAccess:
498 FixupKind = fixup_Hexagon_GPREL16_3;
501 raise_relocation_error(bits, kind);
505 raise_relocation_error(bits, kind);
508 case MCSymbolRefExpr::VK_DTPREL:
509 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
511 case MCSymbolRefExpr::VK_GOTREL:
512 if (MCID.getOpcode() == Hexagon::HI)
513 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
515 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
517 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
518 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
520 case MCSymbolRefExpr::VK_Hexagon_GPREL:
521 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
523 case MCSymbolRefExpr::VK_Hexagon_HI16:
524 FixupKind = Hexagon::fixup_Hexagon_HI16;
526 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
527 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
529 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
530 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
532 case MCSymbolRefExpr::VK_Hexagon_LO16:
533 FixupKind = Hexagon::fixup_Hexagon_LO16;
535 case MCSymbolRefExpr::VK_TPREL:
536 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
539 raise_relocation_error(bits, kind);
545 case MCSymbolRefExpr::VK_None:
546 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
547 : Hexagon::fixup_Hexagon_B15_PCREL;
550 raise_relocation_error(bits, kind);
556 case MCSymbolRefExpr::VK_None:
557 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
560 raise_relocation_error(bits, kind);
567 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
568 case MCSymbolRefExpr::VK_GOT:
569 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
571 case MCSymbolRefExpr::VK_GOTREL:
572 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
574 case MCSymbolRefExpr::VK_None:
575 FixupKind = Hexagon::fixup_Hexagon_12_X;
578 raise_relocation_error(bits, kind);
581 raise_relocation_error(bits, kind);
587 case MCSymbolRefExpr::VK_DTPREL:
588 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
590 case MCSymbolRefExpr::VK_GOT:
591 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
593 case MCSymbolRefExpr::VK_GOTREL:
594 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
596 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
597 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
599 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
600 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
602 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
603 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
605 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
606 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X;
608 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
609 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X;
611 case MCSymbolRefExpr::VK_None:
612 FixupKind = Hexagon::fixup_Hexagon_11_X;
614 case MCSymbolRefExpr::VK_TPREL:
615 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
618 raise_relocation_error(bits, kind);
622 case MCSymbolRefExpr::VK_TPREL:
623 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
626 raise_relocation_error(bits, kind);
634 case MCSymbolRefExpr::VK_None:
635 FixupKind = Hexagon::fixup_Hexagon_10_X;
638 raise_relocation_error(bits, kind);
641 raise_relocation_error(bits, kind);
645 if (MCID.isBranch() ||
646 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
647 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
648 : Hexagon::fixup_Hexagon_B9_PCREL;
650 FixupKind = Hexagon::fixup_Hexagon_9_X;
652 raise_relocation_error(bits, kind);
657 FixupKind = Hexagon::fixup_Hexagon_8_X;
659 raise_relocation_error(bits, kind);
663 if (MCID.isBranch() ||
664 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
665 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
666 : Hexagon::fixup_Hexagon_B7_PCREL;
668 FixupKind = Hexagon::fixup_Hexagon_7_X;
670 raise_relocation_error(bits, kind);
676 case MCSymbolRefExpr::VK_DTPREL:
677 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
679 // This is part of an extender, GOT_11 is a
680 // Word32_U6 unsigned/truncated reloc.
681 case MCSymbolRefExpr::VK_GOT:
682 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
684 case MCSymbolRefExpr::VK_GOTREL:
685 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
687 case MCSymbolRefExpr::VK_Hexagon_PCREL:
688 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
690 case MCSymbolRefExpr::VK_TPREL:
691 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
693 case MCSymbolRefExpr::VK_None:
694 FixupKind = Hexagon::fixup_Hexagon_6_X;
697 raise_relocation_error(bits, kind);
700 raise_relocation_error(bits, kind);
704 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
708 MCExpr const *FixupExpression =
709 (*Addend > 0 && isPCRel(FixupKind))
710 ? MCBinaryExpr::createAdd(MO.getExpr(),
711 MCConstantExpr::create(*Addend, MCT), MCT)
714 MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
715 MCFixupKind(FixupKind), MI.getLoc());
716 Fixups.push_back(fixup);
717 // All of the information is in the fixup.
722 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
723 SmallVectorImpl<MCFixup> &Fixups,
724 MCSubtargetInfo const &STI) const {
726 size_t OperandNumber = ~0U;
727 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
728 if (&MI.getOperand(i) == &MO) {
732 assert((OperandNumber != ~0U) && "Operand not found");
735 if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
736 &MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI))) {
737 // Calculate the new value distance to the associated producer
738 MCOperand const &MCO =
739 MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI));
740 unsigned SOffset = 0;
741 unsigned VOffset = 0;
742 unsigned Register = MCO.getReg();
745 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
746 auto i = Instructions.begin() + *CurrentIndex - 1;
748 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
749 MCInst const &Inst = *i->getInst();
750 if (HexagonMCInstrInfo::isImmext(Inst))
753 if (HexagonMCInstrInfo::isVector(MCII, Inst))
754 // Vector instructions don't count scalars
757 HexagonMCInstrInfo::hasNewValue(MCII, Inst)
758 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
759 : static_cast<unsigned>(Hexagon::NoRegister);
761 HexagonMCInstrInfo::hasNewValue2(MCII, Inst)
762 ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg()
763 : static_cast<unsigned>(Hexagon::NoRegister);
764 if (!RegisterMatches(Register, Register1, Register2))
765 // This isn't the register we're looking for
767 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
768 // Producer is unpredicated
770 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
771 "Unpredicated consumer depending on predicated producer");
772 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
773 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
774 // Producer predicate sense matched ours
777 // Hexagon PRM 10.11 Construct Nt from distance
779 HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset : SOffset;
782 HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2);
787 unsigned Reg = MO.getReg();
788 if (HexagonMCInstrInfo::isSubInstruction(MI) ||
789 llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
790 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
791 return MCT.getRegisterInfo()->getEncodingValue(Reg);
794 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
797 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
798 MCRegisterInfo const &MRI,
800 return new HexagonMCCodeEmitter(MII, MCT);
803 #define ENABLE_INSTR_PREDICATE_VERIFIER
804 #include "HexagonGenMCCodeEmitter.inc"