1 //===- HexagonMCDuplexInfo.cpp - Instruction bundle checking --------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This implements duplexing of instructions to reduce code size
11 //===----------------------------------------------------------------------===//
13 #include "MCTargetDesc/HexagonBaseInfo.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/raw_ostream.h"
31 using namespace Hexagon;
33 #define DEBUG_TYPE "hexagon-mcduplex-info"
35 // pair table of subInstructions with opcodes
36 static const std::pair<unsigned, unsigned> opcodeData[] = {
37 std::make_pair((unsigned)SA1_addi, 0),
38 std::make_pair((unsigned)SA1_addrx, 6144),
39 std::make_pair((unsigned)SA1_addsp, 3072),
40 std::make_pair((unsigned)SA1_and1, 4608),
41 std::make_pair((unsigned)SA1_clrf, 6768),
42 std::make_pair((unsigned)SA1_clrfnew, 6736),
43 std::make_pair((unsigned)SA1_clrt, 6752),
44 std::make_pair((unsigned)SA1_clrtnew, 6720),
45 std::make_pair((unsigned)SA1_cmpeqi, 6400),
46 std::make_pair((unsigned)SA1_combine0i, 7168),
47 std::make_pair((unsigned)SA1_combine1i, 7176),
48 std::make_pair((unsigned)SA1_combine2i, 7184),
49 std::make_pair((unsigned)SA1_combine3i, 7192),
50 std::make_pair((unsigned)SA1_combinerz, 7432),
51 std::make_pair((unsigned)SA1_combinezr, 7424),
52 std::make_pair((unsigned)SA1_dec, 4864),
53 std::make_pair((unsigned)SA1_inc, 4352),
54 std::make_pair((unsigned)SA1_seti, 2048),
55 std::make_pair((unsigned)SA1_setin1, 6656),
56 std::make_pair((unsigned)SA1_sxtb, 5376),
57 std::make_pair((unsigned)SA1_sxth, 5120),
58 std::make_pair((unsigned)SA1_tfr, 4096),
59 std::make_pair((unsigned)SA1_zxtb, 5888),
60 std::make_pair((unsigned)SA1_zxth, 5632),
61 std::make_pair((unsigned)SL1_loadri_io, 0),
62 std::make_pair((unsigned)SL1_loadrub_io, 4096),
63 std::make_pair((unsigned)SL2_deallocframe, 7936),
64 std::make_pair((unsigned)SL2_jumpr31, 8128),
65 std::make_pair((unsigned)SL2_jumpr31_f, 8133),
66 std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),
67 std::make_pair((unsigned)SL2_jumpr31_t, 8132),
68 std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),
69 std::make_pair((unsigned)SL2_loadrb_io, 4096),
70 std::make_pair((unsigned)SL2_loadrd_sp, 7680),
71 std::make_pair((unsigned)SL2_loadrh_io, 0),
72 std::make_pair((unsigned)SL2_loadri_sp, 7168),
73 std::make_pair((unsigned)SL2_loadruh_io, 2048),
74 std::make_pair((unsigned)SL2_return, 8000),
75 std::make_pair((unsigned)SL2_return_f, 8005),
76 std::make_pair((unsigned)SL2_return_fnew, 8007),
77 std::make_pair((unsigned)SL2_return_t, 8004),
78 std::make_pair((unsigned)SL2_return_tnew, 8006),
79 std::make_pair((unsigned)SS1_storeb_io, 4096),
80 std::make_pair((unsigned)SS1_storew_io, 0),
81 std::make_pair((unsigned)SS2_allocframe, 7168),
82 std::make_pair((unsigned)SS2_storebi0, 4608),
83 std::make_pair((unsigned)SS2_storebi1, 4864),
84 std::make_pair((unsigned)SS2_stored_sp, 2560),
85 std::make_pair((unsigned)SS2_storeh_io, 0),
86 std::make_pair((unsigned)SS2_storew_sp, 2048),
87 std::make_pair((unsigned)SS2_storewi0, 4096),
88 std::make_pair((unsigned)SS2_storewi1, 4352)};
90 bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) {
92 case HexagonII::HSIG_None:
95 case HexagonII::HSIG_L1:
96 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
97 case HexagonII::HSIG_L2:
98 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
99 Gb == HexagonII::HSIG_A);
100 case HexagonII::HSIG_S1:
101 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
102 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
103 case HexagonII::HSIG_S2:
104 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
105 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
106 Gb == HexagonII::HSIG_A);
107 case HexagonII::HSIG_A:
108 return (Gb == HexagonII::HSIG_A);
109 case HexagonII::HSIG_Compound:
110 return (Gb == HexagonII::HSIG_Compound);
115 unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
117 case HexagonII::HSIG_None:
120 case HexagonII::HSIG_L1:
124 case HexagonII::HSIG_L1:
126 case HexagonII::HSIG_A:
130 case HexagonII::HSIG_L2:
134 case HexagonII::HSIG_L1:
136 case HexagonII::HSIG_L2:
138 case HexagonII::HSIG_A:
142 case HexagonII::HSIG_S1:
146 case HexagonII::HSIG_L1:
148 case HexagonII::HSIG_L2:
150 case HexagonII::HSIG_S1:
152 case HexagonII::HSIG_A:
156 case HexagonII::HSIG_S2:
160 case HexagonII::HSIG_L1:
162 case HexagonII::HSIG_L2:
164 case HexagonII::HSIG_S1:
166 case HexagonII::HSIG_S2:
168 case HexagonII::HSIG_A:
172 case HexagonII::HSIG_A:
176 case HexagonII::HSIG_A:
180 case HexagonII::HSIG_Compound:
182 case HexagonII::HSIG_Compound:
190 unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
193 switch (MCI.getOpcode()) {
195 return HexagonII::HSIG_None;
199 // Rd = memw(Rs+#u4:2)
200 // Rd = memub(Rs+#u4:0)
201 case Hexagon::L2_loadri_io:
202 DstReg = MCI.getOperand(0).getReg();
203 SrcReg = MCI.getOperand(1).getReg();
204 // Special case this one from Group L2.
205 // Rd = memw(r29+#u5:2)
206 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
207 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
208 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
209 return HexagonII::HSIG_L2;
211 // Rd = memw(Rs+#u4:2)
212 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
213 inRange<4, 2>(MCI, 2)) {
214 return HexagonII::HSIG_L1;
218 case Hexagon::L2_loadrub_io:
219 // Rd = memub(Rs+#u4:0)
220 DstReg = MCI.getOperand(0).getReg();
221 SrcReg = MCI.getOperand(1).getReg();
222 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
223 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
224 inRange<4>(MCI, 2)) {
225 return HexagonII::HSIG_L1;
231 // Rd = memh/memuh(Rs+#u3:1)
232 // Rd = memb(Rs+#u3:0)
233 // Rd = memw(r29+#u5:2) - Handled above.
234 // Rdd = memd(r29+#u5:3)
236 // [if ([!]p0[.new])] dealloc_return
237 // [if ([!]p0[.new])] jumpr r31
238 case Hexagon::L2_loadrh_io:
239 case Hexagon::L2_loadruh_io:
240 // Rd = memh/memuh(Rs+#u3:1)
241 DstReg = MCI.getOperand(0).getReg();
242 SrcReg = MCI.getOperand(1).getReg();
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
244 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
245 inRange<3, 1>(MCI, 2)) {
246 return HexagonII::HSIG_L2;
249 case Hexagon::L2_loadrb_io:
250 // Rd = memb(Rs+#u3:0)
251 DstReg = MCI.getOperand(0).getReg();
252 SrcReg = MCI.getOperand(1).getReg();
253 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
254 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
255 inRange<3>(MCI, 2)) {
256 return HexagonII::HSIG_L2;
259 case Hexagon::L2_loadrd_io:
260 // Rdd = memd(r29+#u5:3)
261 DstReg = MCI.getOperand(0).getReg();
262 SrcReg = MCI.getOperand(1).getReg();
263 if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
264 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
265 inRange<5, 3>(MCI, 2)) {
266 return HexagonII::HSIG_L2;
270 case Hexagon::L4_return:
271 case Hexagon::L2_deallocframe:
272 return HexagonII::HSIG_L2;
274 case Hexagon::EH_RETURN_JMPR:
275 case Hexagon::J2_jumpr:
276 case Hexagon::PS_jmpret:
278 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
279 DstReg = MCI.getOperand(0).getReg();
280 if (Hexagon::R31 == DstReg)
281 return HexagonII::HSIG_L2;
284 case Hexagon::J2_jumprt:
285 case Hexagon::J2_jumprf:
286 case Hexagon::J2_jumprtnew:
287 case Hexagon::J2_jumprfnew:
288 case Hexagon::J2_jumprtnewpt:
289 case Hexagon::J2_jumprfnewpt:
290 case Hexagon::PS_jmprett:
291 case Hexagon::PS_jmpretf:
292 case Hexagon::PS_jmprettnew:
293 case Hexagon::PS_jmpretfnew:
294 case Hexagon::PS_jmprettnewpt:
295 case Hexagon::PS_jmpretfnewpt:
296 DstReg = MCI.getOperand(1).getReg();
297 SrcReg = MCI.getOperand(0).getReg();
298 // [if ([!]p0[.new])] jumpr r31
299 if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) &&
300 (Hexagon::R31 == DstReg)) {
301 return HexagonII::HSIG_L2;
304 case Hexagon::L4_return_t:
305 case Hexagon::L4_return_f:
306 case Hexagon::L4_return_tnew_pnt:
307 case Hexagon::L4_return_fnew_pnt:
308 case Hexagon::L4_return_tnew_pt:
309 case Hexagon::L4_return_fnew_pt:
310 // [if ([!]p0[.new])] dealloc_return
311 SrcReg = MCI.getOperand(1).getReg();
312 if (Hexagon::P0 == SrcReg) {
313 return HexagonII::HSIG_L2;
319 // memw(Rs+#u4:2) = Rt
320 // memb(Rs+#u4:0) = Rt
321 case Hexagon::S2_storeri_io:
322 // Special case this one from Group S2.
323 // memw(r29+#u5:2) = Rt
324 Src1Reg = MCI.getOperand(0).getReg();
325 Src2Reg = MCI.getOperand(2).getReg();
326 if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
327 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
328 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
329 return HexagonII::HSIG_S2;
331 // memw(Rs+#u4:2) = Rt
332 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
333 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
334 inRange<4, 2>(MCI, 1)) {
335 return HexagonII::HSIG_S1;
338 case Hexagon::S2_storerb_io:
339 // memb(Rs+#u4:0) = Rt
340 Src1Reg = MCI.getOperand(0).getReg();
341 Src2Reg = MCI.getOperand(2).getReg();
342 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
343 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
344 inRange<4>(MCI, 1)) {
345 return HexagonII::HSIG_S1;
351 // memh(Rs+#u3:1) = Rt
352 // memw(r29+#u5:2) = Rt
353 // memd(r29+#s6:3) = Rtt
354 // memw(Rs+#u4:2) = #U1
355 // memb(Rs+#u4) = #U1
357 case Hexagon::S2_storerh_io:
358 // memh(Rs+#u3:1) = Rt
359 Src1Reg = MCI.getOperand(0).getReg();
360 Src2Reg = MCI.getOperand(2).getReg();
361 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
362 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
363 inRange<3, 1>(MCI, 1)) {
364 return HexagonII::HSIG_S2;
367 case Hexagon::S2_storerd_io:
368 // memd(r29+#s6:3) = Rtt
369 Src1Reg = MCI.getOperand(0).getReg();
370 Src2Reg = MCI.getOperand(2).getReg();
371 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) &&
372 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg &&
373 inSRange<6, 3>(MCI, 1)) {
374 return HexagonII::HSIG_S2;
377 case Hexagon::S4_storeiri_io:
378 // memw(Rs+#u4:2) = #U1
379 Src1Reg = MCI.getOperand(0).getReg();
380 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
381 inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {
382 return HexagonII::HSIG_S2;
385 case Hexagon::S4_storeirb_io:
386 // memb(Rs+#u4) = #U1
387 Src1Reg = MCI.getOperand(0).getReg();
388 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
389 inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {
390 return HexagonII::HSIG_S2;
393 case Hexagon::S2_allocframe:
394 if (inRange<5, 3>(MCI, 2))
395 return HexagonII::HSIG_S2;
404 // if ([!]P0[.new]) Rd = #0
405 // Rd = add(r29,#u6:2)
407 // P0 = cmp.eq(Rs,#u2)
408 // Rdd = combine(#0,Rs)
409 // Rdd = combine(Rs,#0)
410 // Rdd = combine(#u2,#U2)
413 // Rd = sxth/sxtb/zxtb/zxth(Rs)
415 case Hexagon::A2_addi:
416 DstReg = MCI.getOperand(0).getReg();
417 SrcReg = MCI.getOperand(1).getReg();
418 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
419 // Rd = add(r29,#u6:2)
420 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
421 inRange<6, 2>(MCI, 2)) {
422 return HexagonII::HSIG_A;
425 if (DstReg == SrcReg) {
426 return HexagonII::HSIG_A;
430 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
431 (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == -1)) {
432 return HexagonII::HSIG_A;
436 case Hexagon::A2_add:
438 DstReg = MCI.getOperand(0).getReg();
439 Src1Reg = MCI.getOperand(1).getReg();
440 Src2Reg = MCI.getOperand(2).getReg();
441 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
442 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) {
443 return HexagonII::HSIG_A;
446 case Hexagon::A2_andir:
447 DstReg = MCI.getOperand(0).getReg();
448 SrcReg = MCI.getOperand(1).getReg();
449 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
450 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
451 (minConstant(MCI, 2) == 1 || minConstant(MCI, 2) == 255)) {
452 return HexagonII::HSIG_A;
455 case Hexagon::A2_tfr:
457 DstReg = MCI.getOperand(0).getReg();
458 SrcReg = MCI.getOperand(1).getReg();
459 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
460 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)) {
461 return HexagonII::HSIG_A;
464 case Hexagon::A2_tfrsi:
465 DstReg = MCI.getOperand(0).getReg();
467 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
468 return HexagonII::HSIG_A;
471 case Hexagon::C2_cmoveit:
472 case Hexagon::C2_cmovenewit:
473 case Hexagon::C2_cmoveif:
474 case Hexagon::C2_cmovenewif:
475 // if ([!]P0[.new]) Rd = #0
477 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
478 DstReg = MCI.getOperand(0).getReg(); // Rd
479 PredReg = MCI.getOperand(1).getReg(); // P0
480 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
481 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
482 return HexagonII::HSIG_A;
485 case Hexagon::C2_cmpeqi:
486 // P0 = cmp.eq(Rs,#u2)
487 DstReg = MCI.getOperand(0).getReg();
488 SrcReg = MCI.getOperand(1).getReg();
489 if (Hexagon::P0 == DstReg &&
490 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
491 inRange<2>(MCI, 2)) {
492 return HexagonII::HSIG_A;
495 case Hexagon::A2_combineii:
496 case Hexagon::A4_combineii:
497 // Rdd = combine(#u2,#U2)
498 DstReg = MCI.getOperand(0).getReg();
499 if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
500 inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {
501 return HexagonII::HSIG_A;
504 case Hexagon::A4_combineri:
505 // Rdd = combine(Rs,#0)
506 DstReg = MCI.getOperand(0).getReg();
507 SrcReg = MCI.getOperand(1).getReg();
508 if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
509 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
510 minConstant(MCI, 2) == 0) {
511 return HexagonII::HSIG_A;
514 case Hexagon::A4_combineir:
515 // Rdd = combine(#0,Rs)
516 DstReg = MCI.getOperand(0).getReg();
517 SrcReg = MCI.getOperand(2).getReg();
518 if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) &&
519 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
520 minConstant(MCI, 1) == 0) {
521 return HexagonII::HSIG_A;
524 case Hexagon::A2_sxtb:
525 case Hexagon::A2_sxth:
526 case Hexagon::A2_zxtb:
527 case Hexagon::A2_zxth:
528 // Rd = sxth/sxtb/zxtb/zxth(Rs)
529 DstReg = MCI.getOperand(0).getReg();
530 SrcReg = MCI.getOperand(1).getReg();
531 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
532 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)) {
533 return HexagonII::HSIG_A;
538 return HexagonII::HSIG_None;
541 bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
542 unsigned DstReg, SrcReg;
543 switch (potentialDuplex.getOpcode()) {
544 case Hexagon::A2_addi:
545 // testing for case of: Rx = add(Rx,#s7)
546 DstReg = potentialDuplex.getOperand(0).getReg();
547 SrcReg = potentialDuplex.getOperand(1).getReg();
548 if (DstReg == SrcReg && HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
550 if (!potentialDuplex.getOperand(2).getExpr()->evaluateAsAbsolute(Value))
552 if (!isShiftedInt<7, 0>(Value))
556 case Hexagon::A2_tfrsi:
557 DstReg = potentialDuplex.getOperand(0).getReg();
559 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
561 if (!potentialDuplex.getOperand(1).getExpr()->evaluateAsAbsolute(Value))
563 // Check for case of Rd = #-1.
566 // Check for case of Rd = #u6.
567 if (!isShiftedUInt<6, 0>(Value))
577 /// non-Symmetrical. See if these two instructions are fit for duplex pair.
578 bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII,
579 MCInst const &MIa, bool ExtendedA,
580 MCInst const &MIb, bool ExtendedB,
582 MCSubtargetInfo const &STI) {
583 // Slot 1 cannot be extended in duplexes PRM 10.5
586 // Only A2_addi and A2_tfrsi can be extended in duplex form PRM 10.5
588 unsigned Opcode = MIb.getOpcode();
589 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
592 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa),
593 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb);
595 static std::map<unsigned, unsigned> subinstOpcodeMap(std::begin(opcodeData),
596 std::end(opcodeData));
598 // If a duplex contains 2 insns in the same group, the insns must be
599 // ordered such that the numerically smaller opcode is in slot 1.
600 if ((MIaG != HexagonII::HSIG_None) && (MIaG == MIbG) && bisReversable) {
601 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa);
602 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
604 unsigned zeroedSubInstS0 =
605 subinstOpcodeMap.find(SubInst0.getOpcode())->second;
606 unsigned zeroedSubInstS1 =
607 subinstOpcodeMap.find(SubInst1.getOpcode())->second;
609 if (zeroedSubInstS0 < zeroedSubInstS1)
610 // subinstS0 (maps to slot 0) must be greater than
611 // subinstS1 (maps to slot 1)
615 // allocframe must always be in slot 0
616 if (MIb.getOpcode() == Hexagon::S2_allocframe)
619 if ((MIaG != HexagonII::HSIG_None) && (MIbG != HexagonII::HSIG_None)) {
620 // Prevent 2 instructions with extenders from duplexing
621 // Note that MIb (slot1) can be extended and MIa (slot0)
622 // can never be extended
623 if (subInstWouldBeExtended(MIa))
626 // If duplexing produces an extender, but the original did not
627 // have an extender, do not duplex.
628 if (subInstWouldBeExtended(MIb) && !ExtendedB)
632 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
633 if (MIbG == HexagonII::HSIG_L2) {
634 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() &&
635 (MIb.getOperand(1).getReg() == Hexagon::R31))
637 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() &&
638 (MIb.getOperand(0).getReg() == Hexagon::R31))
642 if (STI.getCPU().equals_lower("hexagonv5") ||
643 STI.getCPU().equals_lower("hexagonv55") ||
644 STI.getCPU().equals_lower("hexagonv60")) {
645 // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb);
646 // therefore, not duplexable if slot 1 is a store, and slot 0 is not.
647 if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) {
648 if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2))
653 return (isDuplexPairMatch(MIaG, MIbG));
656 /// Symmetrical. See if these two instructions are fit for duplex pair.
657 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
658 unsigned MIaG = getDuplexCandidateGroup(MIa),
659 MIbG = getDuplexCandidateGroup(MIb);
660 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
663 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
665 if (Inst.getOperand(opNum).isReg()) {
666 switch (Inst.getOperand(opNum).getReg()) {
668 llvm_unreachable("Not Duplexable Register");
695 subInstPtr.addOperand(Inst.getOperand(opNum));
699 subInstPtr.addOperand(Inst.getOperand(opNum));
702 MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
706 switch (Inst.getOpcode()) {
708 // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
709 llvm_unreachable("Unimplemented subinstruction \n");
711 case Hexagon::A2_addi:
712 Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
715 Result.setOpcode(Hexagon::SA1_inc);
716 addOps(Result, Inst, 0);
717 addOps(Result, Inst, 1);
719 } // 1,2 SUBInst $Rd = add($Rs, #1)
721 Result.setOpcode(Hexagon::SA1_dec);
722 addOps(Result, Inst, 0);
723 addOps(Result, Inst, 1);
724 addOps(Result, Inst, 2);
726 } // 1,2 SUBInst $Rd = add($Rs,#-1)
727 if (Inst.getOperand(1).getReg() == Hexagon::R29) {
728 Result.setOpcode(Hexagon::SA1_addsp);
729 addOps(Result, Inst, 0);
730 addOps(Result, Inst, 2);
732 } // 1,3 SUBInst $Rd = add(r29, #$u6_2)
734 Result.setOpcode(Hexagon::SA1_addi);
735 addOps(Result, Inst, 0);
736 addOps(Result, Inst, 1);
737 addOps(Result, Inst, 2);
738 break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
739 case Hexagon::A2_add:
740 Result.setOpcode(Hexagon::SA1_addrx);
741 addOps(Result, Inst, 0);
742 addOps(Result, Inst, 1);
743 addOps(Result, Inst, 2);
744 break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
745 case Hexagon::S2_allocframe:
746 Result.setOpcode(Hexagon::SS2_allocframe);
747 addOps(Result, Inst, 2);
748 break; // 1 SUBInst allocframe(#$u5_3)
749 case Hexagon::A2_andir:
750 if (minConstant(Inst, 2) == 255) {
751 Result.setOpcode(Hexagon::SA1_zxtb);
752 addOps(Result, Inst, 0);
753 addOps(Result, Inst, 1);
754 break; // 1,2 $Rd = and($Rs, #255)
756 Result.setOpcode(Hexagon::SA1_and1);
757 addOps(Result, Inst, 0);
758 addOps(Result, Inst, 1);
759 break; // 1,2 SUBInst $Rd = and($Rs, #1)
761 case Hexagon::C2_cmpeqi:
762 Result.setOpcode(Hexagon::SA1_cmpeqi);
763 addOps(Result, Inst, 1);
764 addOps(Result, Inst, 2);
765 break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
766 case Hexagon::A4_combineii:
767 case Hexagon::A2_combineii:
768 Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
769 assert(Absolute);(void)Absolute;
771 Result.setOpcode(Hexagon::SA1_combine1i);
772 addOps(Result, Inst, 0);
773 addOps(Result, Inst, 2);
774 break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
777 Result.setOpcode(Hexagon::SA1_combine3i);
778 addOps(Result, Inst, 0);
779 addOps(Result, Inst, 2);
780 break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
783 Result.setOpcode(Hexagon::SA1_combine0i);
784 addOps(Result, Inst, 0);
785 addOps(Result, Inst, 2);
786 break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
789 Result.setOpcode(Hexagon::SA1_combine2i);
790 addOps(Result, Inst, 0);
791 addOps(Result, Inst, 2);
792 break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
795 case Hexagon::A4_combineir:
796 Result.setOpcode(Hexagon::SA1_combinezr);
797 addOps(Result, Inst, 0);
798 addOps(Result, Inst, 2);
799 break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
800 case Hexagon::A4_combineri:
801 Result.setOpcode(Hexagon::SA1_combinerz);
802 addOps(Result, Inst, 0);
803 addOps(Result, Inst, 1);
804 break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
805 case Hexagon::L4_return_tnew_pnt:
806 case Hexagon::L4_return_tnew_pt:
807 Result.setOpcode(Hexagon::SL2_return_tnew);
808 break; // none SUBInst if (p0.new) dealloc_return:nt
809 case Hexagon::L4_return_fnew_pnt:
810 case Hexagon::L4_return_fnew_pt:
811 Result.setOpcode(Hexagon::SL2_return_fnew);
812 break; // none SUBInst if (!p0.new) dealloc_return:nt
813 case Hexagon::L4_return_f:
814 Result.setOpcode(Hexagon::SL2_return_f);
815 break; // none SUBInst if (!p0) dealloc_return
816 case Hexagon::L4_return_t:
817 Result.setOpcode(Hexagon::SL2_return_t);
818 break; // none SUBInst if (p0) dealloc_return
819 case Hexagon::L4_return:
820 Result.setOpcode(Hexagon::SL2_return);
821 break; // none SUBInst dealloc_return
822 case Hexagon::L2_deallocframe:
823 Result.setOpcode(Hexagon::SL2_deallocframe);
824 break; // none SUBInst deallocframe
825 case Hexagon::EH_RETURN_JMPR:
826 case Hexagon::J2_jumpr:
827 case Hexagon::PS_jmpret:
828 Result.setOpcode(Hexagon::SL2_jumpr31);
829 break; // none SUBInst jumpr r31
830 case Hexagon::J2_jumprf:
831 case Hexagon::PS_jmpretf:
832 Result.setOpcode(Hexagon::SL2_jumpr31_f);
833 break; // none SUBInst if (!p0) jumpr r31
834 case Hexagon::J2_jumprfnew:
835 case Hexagon::J2_jumprfnewpt:
836 case Hexagon::PS_jmpretfnewpt:
837 case Hexagon::PS_jmpretfnew:
838 Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
839 break; // none SUBInst if (!p0.new) jumpr:nt r31
840 case Hexagon::J2_jumprt:
841 case Hexagon::PS_jmprett:
842 Result.setOpcode(Hexagon::SL2_jumpr31_t);
843 break; // none SUBInst if (p0) jumpr r31
844 case Hexagon::J2_jumprtnew:
845 case Hexagon::J2_jumprtnewpt:
846 case Hexagon::PS_jmprettnewpt:
847 case Hexagon::PS_jmprettnew:
848 Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
849 break; // none SUBInst if (p0.new) jumpr:nt r31
850 case Hexagon::L2_loadrb_io:
851 Result.setOpcode(Hexagon::SL2_loadrb_io);
852 addOps(Result, Inst, 0);
853 addOps(Result, Inst, 1);
854 addOps(Result, Inst, 2);
855 break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
856 case Hexagon::L2_loadrd_io:
857 Result.setOpcode(Hexagon::SL2_loadrd_sp);
858 addOps(Result, Inst, 0);
859 addOps(Result, Inst, 2);
860 break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
861 case Hexagon::L2_loadrh_io:
862 Result.setOpcode(Hexagon::SL2_loadrh_io);
863 addOps(Result, Inst, 0);
864 addOps(Result, Inst, 1);
865 addOps(Result, Inst, 2);
866 break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
867 case Hexagon::L2_loadrub_io:
868 Result.setOpcode(Hexagon::SL1_loadrub_io);
869 addOps(Result, Inst, 0);
870 addOps(Result, Inst, 1);
871 addOps(Result, Inst, 2);
872 break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
873 case Hexagon::L2_loadruh_io:
874 Result.setOpcode(Hexagon::SL2_loadruh_io);
875 addOps(Result, Inst, 0);
876 addOps(Result, Inst, 1);
877 addOps(Result, Inst, 2);
878 break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
879 case Hexagon::L2_loadri_io:
880 if (Inst.getOperand(1).getReg() == Hexagon::R29) {
881 Result.setOpcode(Hexagon::SL2_loadri_sp);
882 addOps(Result, Inst, 0);
883 addOps(Result, Inst, 2);
884 break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
886 Result.setOpcode(Hexagon::SL1_loadri_io);
887 addOps(Result, Inst, 0);
888 addOps(Result, Inst, 1);
889 addOps(Result, Inst, 2);
890 break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
892 case Hexagon::S4_storeirb_io:
893 Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
894 assert(Absolute);(void)Absolute;
896 Result.setOpcode(Hexagon::SS2_storebi0);
897 addOps(Result, Inst, 0);
898 addOps(Result, Inst, 1);
899 break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
900 } else if (Value == 1) {
901 Result.setOpcode(Hexagon::SS2_storebi1);
902 addOps(Result, Inst, 0);
903 addOps(Result, Inst, 1);
904 break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
907 case Hexagon::S2_storerb_io:
908 Result.setOpcode(Hexagon::SS1_storeb_io);
909 addOps(Result, Inst, 0);
910 addOps(Result, Inst, 1);
911 addOps(Result, Inst, 2);
912 break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
913 case Hexagon::S2_storerd_io:
914 Result.setOpcode(Hexagon::SS2_stored_sp);
915 addOps(Result, Inst, 1);
916 addOps(Result, Inst, 2);
917 break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
918 case Hexagon::S2_storerh_io:
919 Result.setOpcode(Hexagon::SS2_storeh_io);
920 addOps(Result, Inst, 0);
921 addOps(Result, Inst, 1);
922 addOps(Result, Inst, 2);
923 break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
924 case Hexagon::S4_storeiri_io:
925 Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
926 assert(Absolute);(void)Absolute;
928 Result.setOpcode(Hexagon::SS2_storewi0);
929 addOps(Result, Inst, 0);
930 addOps(Result, Inst, 1);
931 break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
932 } else if (Value == 1) {
933 Result.setOpcode(Hexagon::SS2_storewi1);
934 addOps(Result, Inst, 0);
935 addOps(Result, Inst, 1);
936 break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
937 } else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
938 Result.setOpcode(Hexagon::SS2_storew_sp);
939 addOps(Result, Inst, 1);
940 addOps(Result, Inst, 2);
941 break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
944 case Hexagon::S2_storeri_io:
945 if (Inst.getOperand(0).getReg() == Hexagon::R29) {
946 Result.setOpcode(Hexagon::SS2_storew_sp);
947 addOps(Result, Inst, 1);
948 addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
950 Result.setOpcode(Hexagon::SS1_storew_io);
951 addOps(Result, Inst, 0);
952 addOps(Result, Inst, 1);
953 addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
956 case Hexagon::A2_sxtb:
957 Result.setOpcode(Hexagon::SA1_sxtb);
958 addOps(Result, Inst, 0);
959 addOps(Result, Inst, 1);
960 break; // 1,2 SUBInst $Rd = sxtb($Rs)
961 case Hexagon::A2_sxth:
962 Result.setOpcode(Hexagon::SA1_sxth);
963 addOps(Result, Inst, 0);
964 addOps(Result, Inst, 1);
965 break; // 1,2 SUBInst $Rd = sxth($Rs)
966 case Hexagon::A2_tfr:
967 Result.setOpcode(Hexagon::SA1_tfr);
968 addOps(Result, Inst, 0);
969 addOps(Result, Inst, 1);
970 break; // 1,2 SUBInst $Rd = $Rs
971 case Hexagon::C2_cmovenewif:
972 Result.setOpcode(Hexagon::SA1_clrfnew);
973 addOps(Result, Inst, 0);
974 addOps(Result, Inst, 1);
975 break; // 2 SUBInst if (!p0.new) $Rd = #0
976 case Hexagon::C2_cmovenewit:
977 Result.setOpcode(Hexagon::SA1_clrtnew);
978 addOps(Result, Inst, 0);
979 addOps(Result, Inst, 1);
980 break; // 2 SUBInst if (p0.new) $Rd = #0
981 case Hexagon::C2_cmoveif:
982 Result.setOpcode(Hexagon::SA1_clrf);
983 addOps(Result, Inst, 0);
984 addOps(Result, Inst, 1);
985 break; // 2 SUBInst if (!p0) $Rd = #0
986 case Hexagon::C2_cmoveit:
987 Result.setOpcode(Hexagon::SA1_clrt);
988 addOps(Result, Inst, 0);
989 addOps(Result, Inst, 1);
990 break; // 2 SUBInst if (p0) $Rd = #0
991 case Hexagon::A2_tfrsi:
992 Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
993 if (Absolute && Value == -1) {
994 Result.setOpcode(Hexagon::SA1_setin1);
995 addOps(Result, Inst, 0);
996 addOps(Result, Inst, 1);
997 break; // 2 1 SUBInst $Rd = #-1
999 Result.setOpcode(Hexagon::SA1_seti);
1000 addOps(Result, Inst, 0);
1001 addOps(Result, Inst, 1);
1002 break; // 1,2 SUBInst $Rd = #$u6
1004 case Hexagon::A2_zxtb:
1005 Result.setOpcode(Hexagon::SA1_zxtb);
1006 addOps(Result, Inst, 0);
1007 addOps(Result, Inst, 1);
1008 break; // 1,2 $Rd = and($Rs, #255)
1010 case Hexagon::A2_zxth:
1011 Result.setOpcode(Hexagon::SA1_zxth);
1012 addOps(Result, Inst, 0);
1013 addOps(Result, Inst, 1);
1014 break; // 1,2 SUBInst $Rd = zxth($Rs)
1019 static bool isStoreInst(unsigned opCode) {
1021 case Hexagon::S2_storeri_io:
1022 case Hexagon::S2_storerb_io:
1023 case Hexagon::S2_storerh_io:
1024 case Hexagon::S2_storerd_io:
1025 case Hexagon::S4_storeiri_io:
1026 case Hexagon::S4_storeirb_io:
1027 case Hexagon::S2_allocframe:
1034 SmallVector<DuplexCandidate, 8>
1035 HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII,
1036 MCSubtargetInfo const &STI,
1037 MCInst const &MCB) {
1038 assert(isBundle(MCB));
1039 SmallVector<DuplexCandidate, 8> duplexToTry;
1040 // Use an "order matters" version of isDuplexPair.
1041 unsigned numInstrInPacket = MCB.getNumOperands();
1043 for (unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1044 for (unsigned j = HexagonMCInstrInfo::bundleInstructionsOffset,
1046 (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1048 // Check if reversible.
1049 bool bisReversable = true;
1050 if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1051 isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {
1052 LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j
1054 bisReversable = false;
1056 if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf
1057 bisReversable = false;
1060 if (isOrderedDuplexPair(
1061 MCII, *MCB.getOperand(k).getInst(),
1062 HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
1063 *MCB.getOperand(j).getInst(),
1064 HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
1065 bisReversable, STI)) {
1067 unsigned iClass = iClassOfDuplexPair(
1068 getDuplexCandidateGroup(*MCB.getOperand(k).getInst()),
1069 getDuplexCandidateGroup(*MCB.getOperand(j).getInst()));
1071 // Save off pairs for duplex checking.
1072 duplexToTry.push_back(DuplexCandidate(j, k, iClass));
1073 LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":"
1074 << MCB.getOperand(j).getInst()->getOpcode() << ","
1075 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1078 LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":"
1079 << MCB.getOperand(j).getInst()->getOpcode() << ","
1080 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1084 if (bisReversable) {
1085 if (isOrderedDuplexPair(
1086 MCII, *MCB.getOperand(j).getInst(),
1087 HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
1088 *MCB.getOperand(k).getInst(),
1089 HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
1090 bisReversable, STI)) {
1092 unsigned iClass = iClassOfDuplexPair(
1093 getDuplexCandidateGroup(*MCB.getOperand(j).getInst()),
1094 getDuplexCandidateGroup(*MCB.getOperand(k).getInst()));
1096 // Save off pairs for duplex checking.
1097 duplexToTry.push_back(DuplexCandidate(k, j, iClass));
1099 << "adding pair:" << k << "," << j << ":"
1100 << MCB.getOperand(j).getInst()->getOpcode() << ","
1101 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1104 << "skipping pair: " << k << "," << j << ":"
1105 << MCB.getOperand(j).getInst()->getOpcode() << ","
1106 << MCB.getOperand(k).getInst()->getOpcode() << "\n");