contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

   1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Hexagon specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MCTargetDesc/HexagonMCTargetDesc.h"
  15 #include "Hexagon.h"
  16 #include "HexagonDepArch.h"
  17 #include "HexagonTargetStreamer.h"
  18 #include "MCTargetDesc/HexagonInstPrinter.h"
  19 #include "MCTargetDesc/HexagonMCAsmInfo.h"
  20 #include "MCTargetDesc/HexagonMCELFStreamer.h"
  21 #include "MCTargetDesc/HexagonMCInstrInfo.h"
  22 #include "llvm/ADT/StringExtras.h"
  23 #include "llvm/ADT/StringRef.h"
  24 #include "llvm/BinaryFormat/ELF.h"
  25 #include "llvm/MC/MCAsmBackend.h"
  26 #include "llvm/MC/MCCodeEmitter.h"
  27 #include "llvm/MC/MCContext.h"
  28 #include "llvm/MC/MCDwarf.h"
  29 #include "llvm/MC/MCELFStreamer.h"
  30 #include "llvm/MC/MCInstrAnalysis.h"
  31 #include "llvm/MC/MCInstrInfo.h"
  32 #include "llvm/MC/MCObjectWriter.h"
  33 #include "llvm/MC/MCRegisterInfo.h"
  34 #include "llvm/MC/MCStreamer.h"
  35 #include "llvm/MC/MCSubtargetInfo.h"
  36 #include "llvm/Support/ErrorHandling.h"
  37 #include "llvm/Support/TargetRegistry.h"
  38 #include "llvm/Support/raw_ostream.h"
  39 #include <cassert>
  40 #include <cstdint>
  41 #include <new>
  42 #include <string>
  43
  44 using namespace llvm;
  45
  46 #define GET_INSTRINFO_MC_DESC
  47 #include "HexagonGenInstrInfo.inc"
  48
  49 #define GET_SUBTARGETINFO_MC_DESC
  50 #include "HexagonGenSubtargetInfo.inc"
  51
  52 #define GET_REGINFO_MC_DESC
  53 #include "HexagonGenRegisterInfo.inc"
  54
  55 cl::opt<bool> llvm::HexagonDisableCompound
  56   ("mno-compound",
  57    cl::desc("Disable looking for compound instructions for Hexagon"));
  58
  59 cl::opt<bool> llvm::HexagonDisableDuplex
  60   ("mno-pairing",
  61    cl::desc("Disable looking for duplex instructions for Hexagon"));
  62
  63 namespace { // These flags are to be deprecated
  64 cl::opt<bool> MV4("mv4", cl::Hidden, cl::desc("Build for Hexagon V4"),
  65                   cl::init(false));
  66 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
  67                   cl::init(false));
  68 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
  69                    cl::init(false));
  70 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
  71                    cl::init(false));
  72 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
  73                    cl::init(false));
  74 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
  75                    cl::init(false));
  76 } // namespace
  77
  78 cl::opt<Hexagon::ArchEnum>
  79     EnableHVX("mhvx",
  80       cl::desc("Enable Hexagon Vector eXtensions"),
  81       cl::values(
  82         clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
  83         clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
  84         clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
  85         // Sentinal for no value specified
  86         clEnumValN(Hexagon::ArchEnum::V5, "", "")),
  87       // Sentinal for flag not present
  88       cl::init(Hexagon::ArchEnum::V4), cl::ValueOptional);
  89 static cl::opt<bool>
  90   DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"));
  91
  92
  93 static StringRef DefaultArch = "hexagonv60";
  94
  95 static StringRef HexagonGetArchVariant() {
  96   if (MV4)
  97     return "hexagonv4";
  98   if (MV5)
  99     return "hexagonv5";
 100   if (MV55)
 101     return "hexagonv55";
 102   if (MV60)
 103     return "hexagonv60";
 104   if (MV62)
 105     return "hexagonv62";
 106   if (MV65)
 107     return "hexagonv65";
 108   return "";
 109 }
 110
 111 StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
 112   StringRef ArchV = HexagonGetArchVariant();
 113   if (!ArchV.empty() && !CPU.empty()) {
 114     if (ArchV != CPU)
 115       report_fatal_error("conflicting architectures specified.");
 116     return CPU;
 117   }
 118   if (ArchV.empty()) {
 119     if (CPU.empty())
 120       CPU = DefaultArch;
 121     return CPU;
 122   }
 123   return ArchV;
 124 }
 125
 126 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV4FU::SLOT3; }
 127
 128 namespace {
 129
 130 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
 131 public:
 132   HexagonTargetAsmStreamer(MCStreamer &S,
 133                            formatted_raw_ostream &OS,
 134                            bool isVerboseAsm,
 135                            MCInstPrinter &IP)
 136       : HexagonTargetStreamer(S) {}
 137
 138   void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
 139                       const MCInst &Inst, const MCSubtargetInfo &STI) override {
 140     assert(HexagonMCInstrInfo::isBundle(Inst));
 141     assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
 142     std::string Buffer;
 143     {
 144       raw_string_ostream TempStream(Buffer);
 145       InstPrinter.printInst(&Inst, TempStream, "", STI);
 146     }
 147     StringRef Contents(Buffer);
 148     auto PacketBundle = Contents.rsplit('\n');
 149     auto HeadTail = PacketBundle.first.split('\n');
 150     StringRef Separator = "\n";
 151     StringRef Indent = "\t";
 152     OS << "\t{\n";
 153     while (!HeadTail.first.empty()) {
 154       StringRef InstTxt;
 155       auto Duplex = HeadTail.first.split('\v');
 156       if (!Duplex.second.empty()) {
 157         OS << Indent << Duplex.first << Separator;
 158         InstTxt = Duplex.second;
 159       } else if (!HeadTail.first.trim().startswith("immext")) {
 160         InstTxt = Duplex.first;
 161       }
 162       if (!InstTxt.empty())
 163         OS << Indent << InstTxt << Separator;
 164       HeadTail = HeadTail.second.split('\n');
 165     }
 166
 167     if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
 168       OS << "\n\t} :mem_noshuf" << PacketBundle.second;
 169     else
 170       OS << "\t}" << PacketBundle.second;
 171   }
 172 };
 173
 174 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
 175 public:
 176   MCELFStreamer &getStreamer() {
 177     return static_cast<MCELFStreamer &>(Streamer);
 178   }
 179   HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
 180       : HexagonTargetStreamer(S) {
 181     MCAssembler &MCA = getStreamer().getAssembler();
 182     MCA.setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
 183   }
 184
 185
 186   void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 187                               unsigned ByteAlignment,
 188                               unsigned AccessSize) override {
 189     HexagonMCELFStreamer &HexagonELFStreamer =
 190         static_cast<HexagonMCELFStreamer &>(getStreamer());
 191     HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
 192                                                  AccessSize);
 193   }
 194
 195   void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 196                                    unsigned ByteAlignment,
 197                                    unsigned AccessSize) override {
 198     HexagonMCELFStreamer &HexagonELFStreamer =
 199         static_cast<HexagonMCELFStreamer &>(getStreamer());
 200     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
 201         Symbol, Size, ByteAlignment, AccessSize);
 202   }
 203 };
 204
 205 } // end anonymous namespace
 206
 207 llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
 208   MCInstrInfo *X = new MCInstrInfo();
 209   InitHexagonMCInstrInfo(X);
 210   return X;
 211 }
 212
 213 static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
 214   MCRegisterInfo *X = new MCRegisterInfo();
 215   InitHexagonMCRegisterInfo(X, Hexagon::R31);
 216   return X;
 217 }
 218
 219 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
 220                                          const Triple &TT) {
 221   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
 222
 223   // VirtualFP = (R30 + #0).
 224   MCCFIInstruction Inst =
 225       MCCFIInstruction::createDefCfa(nullptr,
 226           MRI.getDwarfRegNum(Hexagon::R30, true), 0);
 227   MAI->addInitialFrameState(Inst);
 228
 229   return MAI;
 230 }
 231
 232 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
 233                                                  unsigned SyntaxVariant,
 234                                                  const MCAsmInfo &MAI,
 235                                                  const MCInstrInfo &MII,
 236                                                  const MCRegisterInfo &MRI)
 237 {
 238   if (SyntaxVariant == 0)
 239     return new HexagonInstPrinter(MAI, MII, MRI);
 240   else
 241     return nullptr;
 242 }
 243
 244 static MCTargetStreamer *
 245 createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
 246                           MCInstPrinter *IP, bool IsVerboseAsm) {
 247   return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
 248 }
 249
 250 static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
 251                                     std::unique_ptr<MCAsmBackend> &&MAB,
 252                                     std::unique_ptr<MCObjectWriter> &&OW,
 253                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
 254                                     bool RelaxAll) {
 255   return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
 256                                   std::move(Emitter));
 257 }
 258
 259 static MCTargetStreamer *
 260 createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
 261   return new HexagonTargetELFStreamer(S, STI);
 262 }
 263
 264 static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
 265   uint64_t FB = STI->getFeatureBits().to_ullong();
 266   if (FB & (1ULL << F))
 267     STI->ToggleFeature(F);
 268 }
 269
 270 static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
 271   uint64_t FB = STI->getFeatureBits().to_ullong();
 272   return (FB & (1ULL << F)) != 0;
 273 }
 274
 275 namespace {
 276 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
 277   SmallVector<StringRef, 3> Result;
 278   if (!FS.empty())
 279     Result.push_back(FS);
 280
 281   switch (EnableHVX) {
 282   case Hexagon::ArchEnum::V55:
 283     break;
 284   case Hexagon::ArchEnum::V60:
 285     Result.push_back("+hvxv60");
 286     break;
 287   case Hexagon::ArchEnum::V62:
 288     Result.push_back("+hvxv62");
 289     break;
 290   case Hexagon::ArchEnum::V65:
 291     Result.push_back("+hvxv65");
 292     break;
 293   case Hexagon::ArchEnum::V5:{
 294     Result.push_back(StringSwitch<StringRef>(CPU)
 295              .Case("hexagonv60", "+hvxv60")
 296              .Case("hexagonv62", "+hvxv62")
 297              .Case("hexagonv65", "+hvxv65"));
 298     break;
 299   }
 300   case Hexagon::ArchEnum::V4:
 301     // Sentinal if -mhvx isn't specified
 302     break;
 303   }
 304   return join(Result.begin(), Result.end(), ",");
 305 }
 306 }
 307
 308 static bool isCPUValid(std::string CPU)
 309 {
 310   std::vector<std::string> table
 311   {
 312     "generic",
 313     "hexagonv4",
 314     "hexagonv5",
 315     "hexagonv55",
 316     "hexagonv60",
 317     "hexagonv62",
 318     "hexagonv65",
 319   };
 320
 321   return std::find(table.begin(), table.end(), CPU) != table.end();
 322 }
 323
 324 namespace {
 325 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
 326                                                    StringRef FS) {
 327   std::pair<std::string, std::string> Result;
 328   Result.first = Hexagon_MC::selectHexagonCPU(CPU);
 329   Result.second = selectHexagonFS(Result.first, FS);
 330   return Result;
 331 }
 332 }
 333
 334 FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
 335   using namespace Hexagon;
 336   // Make sure that +hvx-length turns hvx on, and that "hvx" alone
 337   // turns on hvxvNN, corresponding to the existing ArchVNN.
 338   FeatureBitset FB = S;
 339   unsigned CpuArch = ArchV4;
 340   for (unsigned F : {ArchV65, ArchV62, ArchV60, ArchV55, ArchV5, ArchV4}) {
 341     if (!FB.test(F))
 342       continue;
 343     CpuArch = F;
 344     break;
 345   }
 346   bool UseHvx = false;
 347   for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
 348     if (!FB.test(F))
 349       continue;
 350     UseHvx = true;
 351     break;
 352   }
 353   bool HasHvxVer = false;
 354   for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65}) {
 355     if (!FB.test(F))
 356       continue;
 357     HasHvxVer = true;
 358     UseHvx = true;
 359     break;
 360   }
 361
 362   if (!UseHvx || HasHvxVer)
 363     return FB;
 364
 365   // HasHvxVer is false, and UseHvx is true.
 366   switch (CpuArch) {
 367     case ArchV65:
 368       FB.set(ExtensionHVXV65);
 369       LLVM_FALLTHROUGH;
 370     case ArchV62:
 371       FB.set(ExtensionHVXV62);
 372       LLVM_FALLTHROUGH;
 373     case ArchV60:
 374       FB.set(ExtensionHVXV60);
 375       break;
 376   }
 377   return FB;
 378 }
 379
 380 MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
 381                                                           StringRef CPU,
 382                                                           StringRef FS) {
 383   std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
 384   StringRef CPUName = Features.first;
 385   StringRef ArchFS = Features.second;
 386
 387   if (!isCPUValid(CPUName.str())) {
 388     errs() << "error: invalid CPU \"" << CPUName.str().c_str()
 389            << "\" specified\n";
 390     return nullptr;
 391   }
 392
 393   MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
 394   if (HexagonDisableDuplex) {
 395     llvm::FeatureBitset Features = X->getFeatureBits();
 396     X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false));
 397   }
 398
 399   X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
 400   return X;
 401 }
 402
 403 unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
 404   static std::map<StringRef,unsigned> ElfFlags = {
 405     {"hexagonv4",  ELF::EF_HEXAGON_MACH_V4},
 406     {"hexagonv5",  ELF::EF_HEXAGON_MACH_V5},
 407     {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
 408     {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
 409     {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
 410     {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
 411   };
 412
 413   auto F = ElfFlags.find(STI.getCPU());
 414   assert(F != ElfFlags.end() && "Unrecognized Architecture");
 415   return F->second;
 416 }
 417
 418 namespace {
 419 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
 420 public:
 421   HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
 422
 423   bool isUnconditionalBranch(MCInst const &Inst) const override {
 424     //assert(!HexagonMCInstrInfo::isBundle(Inst));
 425     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 426   }
 427
 428   bool isConditionalBranch(MCInst const &Inst) const override {
 429     //assert(!HexagonMCInstrInfo::isBundle(Inst));
 430     return MCInstrAnalysis::isConditionalBranch(Inst);
 431   }
 432
 433   bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
 434                       uint64_t Size, uint64_t &Target) const override {
 435     //assert(!HexagonMCInstrInfo::isBundle(Inst));
 436     if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
 437       return false;
 438     auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
 439     assert(Extended.isExpr());
 440     int64_t Value;
 441     if(!Extended.getExpr()->evaluateAsAbsolute(Value))
 442       return false;
 443     Target = Value;
 444     return true;
 445   }
 446 };
 447 }
 448
 449 static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
 450   return new HexagonMCInstrAnalysis(Info);
 451 }
 452
 453 // Force static initialization.
 454 extern "C" void LLVMInitializeHexagonTargetMC() {
 455   // Register the MC asm info.
 456   RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
 457
 458   // Register the MC instruction info.
 459   TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
 460                                       createHexagonMCInstrInfo);
 461
 462   // Register the MC register info.
 463   TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
 464                                     createHexagonMCRegisterInfo);
 465
 466   // Register the MC subtarget info.
 467   TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(),
 468     Hexagon_MC::createHexagonMCSubtargetInfo);
 469
 470   // Register the MC Code Emitter
 471   TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
 472                                         createHexagonMCCodeEmitter);
 473
 474   // Register the asm backend
 475   TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
 476                                        createHexagonAsmBackend);
 477
 478
 479   // Register the MC instruction analyzer.
 480   TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(),
 481                                           createHexagonMCInstrAnalysis);
 482
 483   // Register the obj streamer
 484   TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(),
 485                                       createMCStreamer);
 486
 487   // Register the obj target streamer
 488   TargetRegistry::RegisterObjectTargetStreamer(getTheHexagonTarget(),
 489                                       createHexagonObjectTargetStreamer);
 490
 491   // Register the asm streamer
 492   TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
 493                                             createMCAsmTargetStreamer);
 494
 495   // Register the MC Inst Printer
 496   TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
 497                                         createHexagonMCInstPrinter);
 498 }