1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Hexagon specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
17 #include "llvm/Support/CommandLine.h"
21 #define Hexagon_POINTER_SIZE 4
23 #define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
24 #define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
25 #define Hexagon_WordSize Hexagon_PointerSize
26 #define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
28 // allocframe saves LR and FP on stack before allocating
29 // a new stack frame. This takes 8 bytes.
30 #define HEXAGON_LRFP_SIZE 8
32 // Normal instruction size (in bytes).
33 #define HEXAGON_INSTR_SIZE 4
35 // Maximum number of words and instructions in a packet.
36 #define HEXAGON_PACKET_SIZE 4
37 #define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
38 // Minimum number of instructions in an end-loop packet.
39 #define HEXAGON_PACKET_INNER_SIZE 2
40 #define HEXAGON_PACKET_OUTER_SIZE 3
41 // Maximum number of instructions in a packet before shuffling,
42 // including a compound one or a duplex or an extender.
43 #define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
45 // Name of the global offset table as defined by the Hexagon ABI
46 #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
50 struct InstrItinerary;
57 class MCObjectTargetWriter;
59 class MCSubtargetInfo;
60 class MCTargetOptions;
65 class raw_pwrite_stream;
67 Target &getTheHexagonTarget();
68 extern cl::opt<bool> HexagonDisableCompound;
69 extern cl::opt<bool> HexagonDisableDuplex;
70 extern const InstrStage HexagonStages[];
72 MCInstrInfo *createHexagonMCInstrInfo();
73 MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
75 namespace Hexagon_MC {
76 StringRef selectHexagonCPU(StringRef CPU);
78 FeatureBitset completeHVXFeatures(const FeatureBitset &FB);
79 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
80 /// etc. do not need to go through TargetRegistry.
81 MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU,
83 unsigned GetELFFlags(const MCSubtargetInfo &STI);
86 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
87 const MCRegisterInfo &MRI,
90 MCAsmBackend *createHexagonAsmBackend(const Target &T,
91 const MCSubtargetInfo &STI,
92 const MCRegisterInfo &MRI,
93 const MCTargetOptions &Options);
95 std::unique_ptr<MCObjectTargetWriter>
96 createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
98 unsigned HexagonGetLastSlot();
100 } // End llvm namespace
102 // Define symbolic names for Hexagon registers. This defines a mapping from
103 // register name to register number.
105 #define GET_REGINFO_ENUM
106 #include "HexagonGenRegisterInfo.inc"
108 // Defines symbolic names for the Hexagon instructions.
110 #define GET_INSTRINFO_ENUM
111 #define GET_INSTRINFO_SCHED_ENUM
112 #include "HexagonGenInstrInfo.inc"
114 #define GET_SUBTARGETINFO_ENUM
115 #include "HexagonGenSubtargetInfo.inc"
117 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H