1 //===--- RDFRegisters.h -----------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
11 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
17 #include <unordered_map>
23 typedef uint32_t RegisterId;
25 // Template class for a map translating uint32_t into arbitrary types.
26 // The map will act like an indexed set: upon insertion of a new object,
27 // it will automatically assign a new index to it. Index of 0 is treated
28 // as invalid and is never allocated.
29 template <typename T, unsigned N = 32>
31 IndexedSet() : Map() { Map.reserve(N); }
33 T get(uint32_t Idx) const {
34 // Index Idx corresponds to Map[Idx-1].
35 assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
39 uint32_t insert(T Val) {
41 auto F = llvm::find(Map, Val);
43 return F - Map.begin() + 1;
45 return Map.size(); // Return actual_index + 1.
48 uint32_t find(T Val) const {
49 auto F = llvm::find(Map, Val);
50 assert(F != Map.end());
51 return F - Map.begin() + 1;
54 typedef typename std::vector<T>::const_iterator const_iterator;
55 const_iterator begin() const { return Map.begin(); }
56 const_iterator end() const { return Map.end(); }
64 LaneBitmask Mask = LaneBitmask::getNone();
66 RegisterRef() = default;
67 explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
68 : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
70 operator bool() const {
71 return Reg != 0 && Mask.any();
73 bool operator== (const RegisterRef &RR) const {
74 return Reg == RR.Reg && Mask == RR.Mask;
76 bool operator!= (const RegisterRef &RR) const {
77 return !operator==(RR);
79 bool operator< (const RegisterRef &RR) const {
80 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
85 struct PhysicalRegisterInfo {
86 PhysicalRegisterInfo(const TargetRegisterInfo &tri,
87 const MachineFunction &mf);
89 static bool isRegMaskId(RegisterId R) {
90 return TargetRegisterInfo::isStackSlot(R);
92 RegisterId getRegMaskId(const uint32_t *RM) const {
93 return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
95 const uint32_t *getRegMaskBits(RegisterId R) const {
96 return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
98 RegisterRef normalize(RegisterRef RR) const;
100 bool alias(RegisterRef RA, RegisterRef RB) const {
101 if (!isRegMaskId(RA.Reg))
102 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
103 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
105 std::set<RegisterId> getAliasSet(RegisterId Reg) const;
107 RegisterRef getRefForUnit(uint32_t U) const {
108 return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
111 const TargetRegisterInfo &getTRI() const { return TRI; }
115 const TargetRegisterClass *RegClass = nullptr;
122 const TargetRegisterInfo &TRI;
123 std::vector<RegInfo> RegInfos;
124 std::vector<UnitInfo> UnitInfos;
125 IndexedSet<const uint32_t*> RegMasks;
127 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
128 bool aliasRM(RegisterRef RR, RegisterRef RM) const;
129 bool aliasMM(RegisterRef RM, RegisterRef RN) const;
133 struct RegisterAggr {
134 RegisterAggr(const PhysicalRegisterInfo &pri)
135 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
136 RegisterAggr(const RegisterAggr &RG) = default;
138 bool empty() const { return Units.empty(); }
139 bool hasAliasOf(RegisterRef RR) const;
140 bool hasCoverOf(RegisterRef RR) const;
141 static bool isCoverOf(RegisterRef RA, RegisterRef RB,
142 const PhysicalRegisterInfo &PRI) {
143 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
146 RegisterAggr &insert(RegisterRef RR);
147 RegisterAggr &insert(const RegisterAggr &RG);
148 RegisterAggr &intersect(RegisterRef RR);
149 RegisterAggr &intersect(const RegisterAggr &RG);
150 RegisterAggr &clear(RegisterRef RR);
151 RegisterAggr &clear(const RegisterAggr &RG);
153 RegisterRef intersectWith(RegisterRef RR) const;
154 RegisterRef clearIn(RegisterRef RR) const;
155 RegisterRef makeRegRef() const;
157 void print(raw_ostream &OS) const;
160 typedef std::map<RegisterId,LaneBitmask> MapType;
163 MapType::iterator Pos;
165 const RegisterAggr *Owner;
167 rr_iterator(const RegisterAggr &RG, bool End);
168 RegisterRef operator*() const {
169 return RegisterRef(Pos->first, Pos->second);
171 rr_iterator &operator++() {
176 bool operator==(const rr_iterator &I) const {
177 assert(Owner == I.Owner);
178 return Index == I.Index;
180 bool operator!=(const rr_iterator &I) const {
181 return !(*this == I);
185 rr_iterator rr_begin() const {
186 return rr_iterator(*this, false);
188 rr_iterator rr_end() const {
189 return rr_iterator(*this, true);
194 const PhysicalRegisterInfo &PRI;
198 // Optionally print the lane mask, if it is not ~0.
199 struct PrintLaneMaskOpt {
200 PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {}
203 raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P);