1 //===--- RDFRegisters.h -----------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
11 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
17 #include <unordered_map>
23 typedef uint32_t RegisterId;
25 // Template class for a map translating uint32_t into arbitrary types.
26 // The map will act like an indexed set: upon insertion of a new object,
27 // it will automatically assign a new index to it. Index of 0 is treated
28 // as invalid and is never allocated.
29 template <typename T, unsigned N = 32>
31 IndexedSet() : Map() { Map.reserve(N); }
33 T get(uint32_t Idx) const {
34 // Index Idx corresponds to Map[Idx-1].
35 assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
39 uint32_t insert(T Val) {
41 auto F = llvm::find(Map, Val);
43 return F - Map.begin() + 1;
45 return Map.size(); // Return actual_index + 1.
48 uint32_t find(T Val) const {
49 auto F = llvm::find(Map, Val);
50 assert(F != Map.end());
51 return F - Map.begin() + 1;
54 uint32_t size() const { return Map.size(); }
56 typedef typename std::vector<T>::const_iterator const_iterator;
57 const_iterator begin() const { return Map.begin(); }
58 const_iterator end() const { return Map.end(); }
66 LaneBitmask Mask = LaneBitmask::getNone();
68 RegisterRef() = default;
69 explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
70 : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
72 operator bool() const {
73 return Reg != 0 && Mask.any();
75 bool operator== (const RegisterRef &RR) const {
76 return Reg == RR.Reg && Mask == RR.Mask;
78 bool operator!= (const RegisterRef &RR) const {
79 return !operator==(RR);
81 bool operator< (const RegisterRef &RR) const {
82 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
87 struct PhysicalRegisterInfo {
88 PhysicalRegisterInfo(const TargetRegisterInfo &tri,
89 const MachineFunction &mf);
91 static bool isRegMaskId(RegisterId R) {
92 return TargetRegisterInfo::isStackSlot(R);
94 RegisterId getRegMaskId(const uint32_t *RM) const {
95 return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
97 const uint32_t *getRegMaskBits(RegisterId R) const {
98 return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
100 RegisterRef normalize(RegisterRef RR) const;
102 bool alias(RegisterRef RA, RegisterRef RB) const {
103 if (!isRegMaskId(RA.Reg))
104 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
105 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
107 std::set<RegisterId> getAliasSet(RegisterId Reg) const;
109 RegisterRef getRefForUnit(uint32_t U) const {
110 return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
112 const BitVector &getMaskUnits(RegisterId MaskId) const {
113 return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
115 RegisterRef mapTo(RegisterRef RR, unsigned R) const;
117 const TargetRegisterInfo &getTRI() const { return TRI; }
121 const TargetRegisterClass *RegClass = nullptr;
131 const TargetRegisterInfo &TRI;
132 IndexedSet<const uint32_t*> RegMasks;
133 std::vector<RegInfo> RegInfos;
134 std::vector<UnitInfo> UnitInfos;
135 std::vector<MaskInfo> MaskInfos;
137 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
138 bool aliasRM(RegisterRef RR, RegisterRef RM) const;
139 bool aliasMM(RegisterRef RM, RegisterRef RN) const;
143 struct RegisterAggr {
144 RegisterAggr(const PhysicalRegisterInfo &pri)
145 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
146 RegisterAggr(const RegisterAggr &RG) = default;
148 bool empty() const { return Units.none(); }
149 bool hasAliasOf(RegisterRef RR) const;
150 bool hasCoverOf(RegisterRef RR) const;
151 static bool isCoverOf(RegisterRef RA, RegisterRef RB,
152 const PhysicalRegisterInfo &PRI) {
153 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
156 RegisterAggr &insert(RegisterRef RR);
157 RegisterAggr &insert(const RegisterAggr &RG);
158 RegisterAggr &intersect(RegisterRef RR);
159 RegisterAggr &intersect(const RegisterAggr &RG);
160 RegisterAggr &clear(RegisterRef RR);
161 RegisterAggr &clear(const RegisterAggr &RG);
163 RegisterRef intersectWith(RegisterRef RR) const;
164 RegisterRef clearIn(RegisterRef RR) const;
165 RegisterRef makeRegRef() const;
167 void print(raw_ostream &OS) const;
170 typedef std::map<RegisterId,LaneBitmask> MapType;
173 MapType::iterator Pos;
175 const RegisterAggr *Owner;
177 rr_iterator(const RegisterAggr &RG, bool End);
178 RegisterRef operator*() const {
179 return RegisterRef(Pos->first, Pos->second);
181 rr_iterator &operator++() {
186 bool operator==(const rr_iterator &I) const {
187 assert(Owner == I.Owner);
188 return Index == I.Index;
190 bool operator!=(const rr_iterator &I) const {
191 return !(*this == I);
195 rr_iterator rr_begin() const {
196 return rr_iterator(*this, false);
198 rr_iterator rr_end() const {
199 return rr_iterator(*this, true);
204 const PhysicalRegisterInfo &PRI;
208 // Optionally print the lane mask, if it is not ~0.
209 struct PrintLaneMaskOpt {
210 PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {}
213 raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P);