1 //===-- LanaiDelaySlotFiller.cpp - Lanai delay slot filler ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fills delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
15 #include "LanaiTargetMachine.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
25 #define DEBUG_TYPE "delay-slot-filler"
27 STATISTIC(FilledSlots, "Number of delay slots filled");
30 NopDelaySlotFiller("lanai-nop-delay-filler", cl::init(false),
31 cl::desc("Fill Lanai delay slots with NOPs."),
35 struct Filler : public MachineFunctionPass {
36 // Target machine description which we query for reg. names, data
38 const TargetInstrInfo *TII;
39 const TargetRegisterInfo *TRI;
40 MachineBasicBlock::instr_iterator LastFiller;
43 explicit Filler() : MachineFunctionPass(ID) {}
45 StringRef getPassName() const override { return "Lanai Delay Slot Filler"; }
47 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
49 bool runOnMachineFunction(MachineFunction &MF) override {
50 const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>();
51 TII = Subtarget.getInstrInfo();
52 TRI = Subtarget.getRegisterInfo();
55 for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
57 Changed |= runOnMachineBasicBlock(*FI);
61 MachineFunctionProperties getRequiredProperties() const override {
62 return MachineFunctionProperties().set(
63 MachineFunctionProperties::Property::NoVRegs);
66 void insertDefsUses(MachineBasicBlock::instr_iterator MI,
67 SmallSet<unsigned, 32> &RegDefs,
68 SmallSet<unsigned, 32> &RegUses);
70 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
72 bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
73 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
74 SmallSet<unsigned, 32> &RegUses);
76 bool findDelayInstr(MachineBasicBlock &MBB,
77 MachineBasicBlock::instr_iterator Slot,
78 MachineBasicBlock::instr_iterator &Filler);
81 } // end of anonymous namespace
83 // createLanaiDelaySlotFillerPass - Returns a pass that fills in delay
84 // slots in Lanai MachineFunctions
86 llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine & /*tm*/) {
90 // runOnMachineBasicBlock - Fill in delay slots for the given basic block.
91 // There is one or two delay slot per delayed instruction.
92 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
94 LastFiller = MBB.instr_end();
96 for (MachineBasicBlock::instr_iterator I = MBB.instr_begin();
97 I != MBB.instr_end(); ++I) {
98 if (I->getDesc().hasDelaySlot()) {
99 MachineBasicBlock::instr_iterator InstrWithSlot = I;
100 MachineBasicBlock::instr_iterator J = I;
102 // Treat RET specially as it is only instruction with 2 delay slots
103 // generated while all others generated have 1 delay slot.
104 if (I->getOpcode() == Lanai::RET) {
105 // RET is generated as part of epilogue generation and hence we know
106 // what the two instructions preceding it are and that it is safe to
107 // insert RET above them.
108 MachineBasicBlock::reverse_instr_iterator RI = ++I.getReverse();
109 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
110 RI->getOperand(0).getReg() == Lanai::FP &&
111 RI->getOperand(1).isReg() &&
112 RI->getOperand(1).getReg() == Lanai::FP &&
113 RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8);
115 assert(RI->getOpcode() == Lanai::ADD_I_LO &&
116 RI->getOperand(0).isReg() &&
117 RI->getOperand(0).getReg() == Lanai::SP &&
118 RI->getOperand(1).isReg() &&
119 RI->getOperand(1).getReg() == Lanai::FP);
120 MachineBasicBlock::instr_iterator FI = RI.getReverse();
121 MBB.splice(std::next(I), &MBB, FI, I);
124 if (!NopDelaySlotFiller && findDelayInstr(MBB, I, J)) {
125 MBB.splice(std::next(I), &MBB, J);
127 BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP));
133 // Record the filler instruction that filled the delay slot.
134 // The instruction after it will be visited in the next iteration.
137 // Bundle the delay slot filler to InstrWithSlot so that the machine
138 // verifier doesn't expect this instruction to be a terminator.
139 MIBundleBuilder(MBB, InstrWithSlot, std::next(LastFiller));
145 bool Filler::findDelayInstr(MachineBasicBlock &MBB,
146 MachineBasicBlock::instr_iterator Slot,
147 MachineBasicBlock::instr_iterator &Filler) {
148 SmallSet<unsigned, 32> RegDefs;
149 SmallSet<unsigned, 32> RegUses;
151 insertDefsUses(Slot, RegDefs, RegUses);
153 bool SawLoad = false;
154 bool SawStore = false;
156 for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
157 I != MBB.instr_rend(); ++I) {
159 if (I->isDebugValue())
162 // Convert to forward iterator.
163 MachineBasicBlock::instr_iterator FI = I.getReverse();
165 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isLabel() ||
166 FI == LastFiller || I->isPseudo())
169 if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) {
170 insertDefsUses(FI, RegDefs, RegUses);
179 bool Filler::delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
180 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
181 SmallSet<unsigned, 32> &RegUses) {
182 if (MI->isImplicitDef() || MI->isKill())
185 // Loads or stores cannot be moved past a store to the delay slot
186 // and stores cannot be moved past a load.
193 if (MI->mayStore()) {
201 assert((!MI->isCall() && !MI->isReturn()) &&
202 "Cannot put calls or returns in delay slot.");
204 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
205 const MachineOperand &MO = MI->getOperand(I);
208 if (!MO.isReg() || !(Reg = MO.getReg()))
212 // check whether Reg is defined or used before delay slot.
213 if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
217 // check whether Reg is defined before delay slot.
218 if (isRegInSet(RegDefs, Reg))
225 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
226 void Filler::insertDefsUses(MachineBasicBlock::instr_iterator MI,
227 SmallSet<unsigned, 32> &RegDefs,
228 SmallSet<unsigned, 32> &RegUses) {
229 // If MI is a call or return, just examine the explicit non-variadic operands.
230 MCInstrDesc MCID = MI->getDesc();
231 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
232 : MI->getNumOperands();
233 for (unsigned I = 0; I != E; ++I) {
234 const MachineOperand &MO = MI->getOperand(I);
237 if (!MO.isReg() || !(Reg = MO.getReg()))
246 // Call & return instructions defines SP implicitly. Implicit defines are not
247 // included in the RegDefs set of calls but instructions modifying SP cannot
248 // be inserted in the delay slot of a call/return as these instructions are
249 // expanded to multiple instructions with SP modified before the branch that
250 // has the delay slot.
251 if (MI->isCall() || MI->isReturn())
252 RegDefs.insert(Lanai::SP);
255 // Returns true if the Reg or its alias is in the RegSet.
256 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
257 // Check Reg and all aliased Registers.
258 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
259 if (RegSet.count(*AI))