1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LanaiTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "LanaiISelLowering.h"
16 #include "LanaiCondCode.h"
17 #include "LanaiMachineFunctionInfo.h"
18 #include "LanaiSubtarget.h"
19 #include "LanaiTargetObjectFile.h"
20 #include "MCTargetDesc/LanaiBaseInfo.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/MachineValueType.h"
32 #include "llvm/CodeGen/RuntimeLibcalls.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SelectionDAGNodes.h"
35 #include "llvm/CodeGen/TargetCallingConv.h"
36 #include "llvm/CodeGen/ValueTypes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/KnownBits.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetMachine.h"
56 #define DEBUG_TYPE "lanai-lower"
60 // Limit on number of instructions the lowered multiplication may have before a
61 // call to the library function should be generated instead. The threshold is
62 // currently set to 14 as this was the smallest threshold that resulted in all
63 // constant multiplications being lowered. A threshold of 5 covered all cases
64 // except for one multiplication which required 14. mulsi3 requires 16
65 // instructions (including the prologue and epilogue but excluding instructions
66 // at call site). Until we can inline mulsi3, generating at most 14 instructions
67 // will be faster than invoking mulsi3.
68 static cl::opt<int> LanaiLowerConstantMulThreshold(
69 "lanai-constant-mul-threshold", cl::Hidden,
70 cl::desc("Maximum number of instruction to generate when lowering constant "
71 "multiplication instead of calling library function [default=14]"),
74 LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
75 const LanaiSubtarget &STI)
76 : TargetLowering(TM) {
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
80 // Compute derived properties from the register classes
81 TRI = STI.getRegisterInfo();
82 computeRegisterProperties(TRI);
84 setStackPointerRegisterToSaveRestore(Lanai::SP);
86 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
87 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
88 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
89 setOperationAction(ISD::SETCC, MVT::i32, Custom);
90 setOperationAction(ISD::SETCCE, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT, MVT::i32, Expand);
92 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
95 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
99 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
100 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
101 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
103 setOperationAction(ISD::VASTART, MVT::Other, Custom);
104 setOperationAction(ISD::VAARG, MVT::Other, Expand);
105 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
106 setOperationAction(ISD::VAEND, MVT::Other, Expand);
108 setOperationAction(ISD::SDIV, MVT::i32, Expand);
109 setOperationAction(ISD::UDIV, MVT::i32, Expand);
110 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
111 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i32, Expand);
113 setOperationAction(ISD::UREM, MVT::i32, Expand);
115 setOperationAction(ISD::MUL, MVT::i32, Custom);
116 setOperationAction(ISD::MULHU, MVT::i32, Expand);
117 setOperationAction(ISD::MULHS, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
121 setOperationAction(ISD::ROTR, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
123 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
124 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
125 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
128 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
129 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
130 setOperationAction(ISD::CTTZ, MVT::i32, Legal);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
133 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
136 // Extended load operations for i1 types must be promoted
137 for (MVT VT : MVT::integer_valuetypes()) {
138 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
143 setTargetDAGCombine(ISD::ADD);
144 setTargetDAGCombine(ISD::SUB);
145 setTargetDAGCombine(ISD::AND);
146 setTargetDAGCombine(ISD::OR);
147 setTargetDAGCombine(ISD::XOR);
149 // Function alignments (log2)
150 setMinFunctionAlignment(2);
151 setPrefFunctionAlignment(2);
153 setJumpIsExpensive(true);
155 // TODO: Setting the minimum jump table entries needed before a
156 // switch is transformed to a jump table to 100 to avoid creating jump tables
157 // as this was causing bad performance compared to a large group of if
158 // statements. Re-evaluate this on new benchmarks.
159 setMinimumJumpTableEntries(100);
161 // Use fast calling convention for library functions.
162 for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
163 setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
166 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
167 MaxStoresPerMemsetOptSize = 8;
168 MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
169 MaxStoresPerMemcpyOptSize = 8;
170 MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
171 MaxStoresPerMemmoveOptSize = 8;
173 // Booleans always contain 0 or 1.
174 setBooleanContents(ZeroOrOneBooleanContent);
177 SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
178 SelectionDAG &DAG) const {
179 switch (Op.getOpcode()) {
181 return LowerMUL(Op, DAG);
183 return LowerBR_CC(Op, DAG);
184 case ISD::ConstantPool:
185 return LowerConstantPool(Op, DAG);
186 case ISD::GlobalAddress:
187 return LowerGlobalAddress(Op, DAG);
188 case ISD::BlockAddress:
189 return LowerBlockAddress(Op, DAG);
191 return LowerJumpTable(Op, DAG);
193 return LowerSELECT_CC(Op, DAG);
195 return LowerSETCC(Op, DAG);
197 return LowerSETCCE(Op, DAG);
199 return LowerSHL_PARTS(Op, DAG);
201 return LowerSRL_PARTS(Op, DAG);
203 return LowerVASTART(Op, DAG);
204 case ISD::DYNAMIC_STACKALLOC:
205 return LowerDYNAMIC_STACKALLOC(Op, DAG);
206 case ISD::RETURNADDR:
207 return LowerRETURNADDR(Op, DAG);
209 return LowerFRAMEADDR(Op, DAG);
211 llvm_unreachable("unimplemented operand");
215 //===----------------------------------------------------------------------===//
216 // Lanai Inline Assembly Support
217 //===----------------------------------------------------------------------===//
219 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
220 SelectionDAG & /*DAG*/) const {
221 // Only unallocatable registers should be matched here.
222 unsigned Reg = StringSwitch<unsigned>(RegName)
223 .Case("pc", Lanai::PC)
224 .Case("sp", Lanai::SP)
225 .Case("fp", Lanai::FP)
226 .Case("rr1", Lanai::RR1)
227 .Case("r10", Lanai::R10)
228 .Case("rr2", Lanai::RR2)
229 .Case("r11", Lanai::R11)
230 .Case("rca", Lanai::RCA)
235 report_fatal_error("Invalid register name global variable");
238 std::pair<unsigned, const TargetRegisterClass *>
239 LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
240 StringRef Constraint,
242 if (Constraint.size() == 1)
243 // GCC Constraint Letters
244 switch (Constraint[0]) {
245 case 'r': // GENERAL_REGS
246 return std::make_pair(0U, &Lanai::GPRRegClass);
251 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
254 // Examine constraint type and operand type and determine a weight value.
255 // This object must already have been set up with the operand type
256 // and the current alternative constraint selected.
257 TargetLowering::ConstraintWeight
258 LanaiTargetLowering::getSingleConstraintMatchWeight(
259 AsmOperandInfo &Info, const char *Constraint) const {
260 ConstraintWeight Weight = CW_Invalid;
261 Value *CallOperandVal = Info.CallOperandVal;
262 // If we don't have a value, we can't do a match,
263 // but allow it at the lowest weight.
264 if (CallOperandVal == nullptr)
266 // Look at the constraint type.
267 switch (*Constraint) {
268 case 'I': // signed 16 bit immediate
269 case 'J': // integer zero
270 case 'K': // unsigned 16 bit immediate
271 case 'L': // immediate in the range 0 to 31
272 case 'M': // signed 32 bit immediate where lower 16 bits are 0
273 case 'N': // signed 26 bit immediate
274 case 'O': // integer zero
275 if (isa<ConstantInt>(CallOperandVal))
276 Weight = CW_Constant;
279 Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
285 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
286 // vector. If it is invalid, don't add anything to Ops.
287 void LanaiTargetLowering::LowerAsmOperandForConstraint(
288 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
289 SelectionDAG &DAG) const {
290 SDValue Result(nullptr, 0);
292 // Only support length 1 constraints for now.
293 if (Constraint.length() > 1)
296 char ConstraintLetter = Constraint[0];
297 switch (ConstraintLetter) {
298 case 'I': // Signed 16 bit constant
299 // If this fails, the parent routine will give an error
300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
301 if (isInt<16>(C->getSExtValue())) {
302 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
308 case 'J': // integer zero
310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
311 if (C->getZExtValue() == 0) {
312 Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
317 case 'K': // unsigned 16 bit immediate
318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
319 if (isUInt<16>(C->getZExtValue())) {
320 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
326 case 'L': // immediate in the range 0 to 31
327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
328 if (C->getZExtValue() <= 31) {
329 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
335 case 'M': // signed 32 bit immediate where lower 16 bits are 0
336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
337 int64_t Val = C->getSExtValue();
338 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
339 Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
344 case 'N': // signed 26 bit immediate
345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
346 int64_t Val = C->getSExtValue();
347 if ((Val >= -33554432) && (Val <= 33554431)) {
348 Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
354 break; // This will fall through to the generic implementation
357 if (Result.getNode()) {
358 Ops.push_back(Result);
362 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
365 //===----------------------------------------------------------------------===//
366 // Calling Convention Implementation
367 //===----------------------------------------------------------------------===//
369 #include "LanaiGenCallingConv.inc"
371 static unsigned NumFixedArgs;
372 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
373 CCValAssign::LocInfo LocInfo,
374 ISD::ArgFlagsTy ArgFlags, CCState &State) {
375 // Handle fixed arguments with default CC.
376 // Note: Both the default and fast CC handle VarArg the same and hence the
377 // calling convention of the function is not considered here.
378 if (ValNo < NumFixedArgs) {
379 return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
382 // Promote i8/i16 args to i32
383 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
385 if (ArgFlags.isSExt())
386 LocInfo = CCValAssign::SExt;
387 else if (ArgFlags.isZExt())
388 LocInfo = CCValAssign::ZExt;
390 LocInfo = CCValAssign::AExt;
393 // VarArgs get passed on stack
394 unsigned Offset = State.AllocateStack(4, 4);
395 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
399 SDValue LanaiTargetLowering::LowerFormalArguments(
400 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
401 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
402 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
405 case CallingConv::Fast:
406 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
408 report_fatal_error("Unsupported calling convention");
412 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
413 SmallVectorImpl<SDValue> &InVals) const {
414 SelectionDAG &DAG = CLI.DAG;
416 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
417 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
418 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
419 SDValue Chain = CLI.Chain;
420 SDValue Callee = CLI.Callee;
421 bool &IsTailCall = CLI.IsTailCall;
422 CallingConv::ID CallConv = CLI.CallConv;
423 bool IsVarArg = CLI.IsVarArg;
425 // Lanai target does not yet support tail call optimization.
429 case CallingConv::Fast:
431 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
432 OutVals, Ins, DL, DAG, InVals);
434 report_fatal_error("Unsupported calling convention");
438 // LowerCCCArguments - transform physical registers into virtual registers and
439 // generate load operations for arguments places on the stack.
440 SDValue LanaiTargetLowering::LowerCCCArguments(
441 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
442 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
443 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
444 MachineFunction &MF = DAG.getMachineFunction();
445 MachineFrameInfo &MFI = MF.getFrameInfo();
446 MachineRegisterInfo &RegInfo = MF.getRegInfo();
447 LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
449 // Assign locations to all of the incoming arguments.
450 SmallVector<CCValAssign, 16> ArgLocs;
451 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
453 if (CallConv == CallingConv::Fast) {
454 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
456 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
459 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
460 CCValAssign &VA = ArgLocs[i];
462 // Arguments passed in registers
463 EVT RegVT = VA.getLocVT();
464 switch (RegVT.getSimpleVT().SimpleTy) {
466 unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
467 RegInfo.addLiveIn(VA.getLocReg(), VReg);
468 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
470 // If this is an 8/16-bit value, it is really passed promoted to 32
471 // bits. Insert an assert[sz]ext to capture this, then truncate to the
473 if (VA.getLocInfo() == CCValAssign::SExt)
474 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
475 DAG.getValueType(VA.getValVT()));
476 else if (VA.getLocInfo() == CCValAssign::ZExt)
477 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
478 DAG.getValueType(VA.getValVT()));
480 if (VA.getLocInfo() != CCValAssign::Full)
481 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
483 InVals.push_back(ArgValue);
487 DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
488 << RegVT.getEVTString() << "\n");
489 llvm_unreachable("unhandled argument type");
493 assert(VA.isMemLoc());
494 // Load the argument to a virtual register
495 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
496 // Check that the argument fits in stack slot
498 errs() << "LowerFormalArguments Unhandled argument type: "
499 << EVT(VA.getLocVT()).getEVTString() << "\n";
501 // Create the frame index object for this incoming parameter...
502 int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
504 // Create the SelectionDAG nodes corresponding to a load
505 // from this parameter
506 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
507 InVals.push_back(DAG.getLoad(
508 VA.getLocVT(), DL, Chain, FIN,
509 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
513 // The Lanai ABI for returning structs by value requires that we copy
514 // the sret argument into rv for the return. Save the argument into
515 // a virtual register so that we can access it from the return points.
516 if (MF.getFunction().hasStructRetAttr()) {
517 unsigned Reg = LanaiMFI->getSRetReturnReg();
519 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
520 LanaiMFI->setSRetReturnReg(Reg);
522 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
523 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
527 // Record the frame index of the first variable argument
528 // which is a value necessary to VASTART.
529 int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
530 LanaiMFI->setVarArgsFrameIndex(FI);
537 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
539 const SmallVectorImpl<ISD::OutputArg> &Outs,
540 const SmallVectorImpl<SDValue> &OutVals,
541 const SDLoc &DL, SelectionDAG &DAG) const {
542 // CCValAssign - represent the assignment of the return value to a location
543 SmallVector<CCValAssign, 16> RVLocs;
545 // CCState - Info about the registers and stack slot.
546 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
549 // Analize return values.
550 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
553 SmallVector<SDValue, 4> RetOps(1, Chain);
555 // Copy the result values into the output registers.
556 for (unsigned i = 0; i != RVLocs.size(); ++i) {
557 CCValAssign &VA = RVLocs[i];
558 assert(VA.isRegLoc() && "Can only return in registers!");
560 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
562 // Guarantee that all emitted copies are stuck together with flags.
563 Flag = Chain.getValue(1);
564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
567 // The Lanai ABI for returning structs by value requires that we copy
568 // the sret argument into rv for the return. We saved the argument into
569 // a virtual register in the entry block, so now we copy the value out
571 if (DAG.getMachineFunction().getFunction().hasStructRetAttr()) {
572 MachineFunction &MF = DAG.getMachineFunction();
573 LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
574 unsigned Reg = LanaiMFI->getSRetReturnReg();
576 "SRetReturnReg should have been set in LowerFormalArguments().");
578 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
580 Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
581 Flag = Chain.getValue(1);
583 DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
586 RetOps[0] = Chain; // Update chain
588 unsigned Opc = LanaiISD::RET_FLAG;
590 RetOps.push_back(Flag);
593 return DAG.getNode(Opc, DL, MVT::Other,
594 ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
597 // LowerCCCCallTo - functions arguments are copied from virtual regs to
598 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
599 SDValue LanaiTargetLowering::LowerCCCCallTo(
600 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
601 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<SDValue> &OutVals,
603 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
604 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
605 // Analyze operands of the call, assigning locations to each operand.
606 SmallVector<CCValAssign, 16> ArgLocs;
607 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
609 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
610 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
614 const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
616 NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
619 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
621 if (CallConv == CallingConv::Fast)
622 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
624 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
627 // Get a count of how many bytes are to be pushed on the stack.
628 unsigned NumBytes = CCInfo.getNextStackOffset();
630 // Create local copies for byval args.
631 SmallVector<SDValue, 8> ByValArgs;
632 for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
633 ISD::ArgFlagsTy Flags = Outs[I].Flags;
634 if (!Flags.isByVal())
637 SDValue Arg = OutVals[I];
638 unsigned Size = Flags.getByValSize();
639 unsigned Align = Flags.getByValAlign();
641 int FI = MFI.CreateStackObject(Size, Align, false);
642 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
643 SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
645 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
646 /*IsVolatile=*/false,
647 /*AlwaysInline=*/false,
648 /*isTailCall=*/false, MachinePointerInfo(),
649 MachinePointerInfo());
650 ByValArgs.push_back(FIPtr);
653 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
655 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
656 SmallVector<SDValue, 12> MemOpChains;
659 // Walk the register/memloc assignments, inserting copies/loads.
660 for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
661 CCValAssign &VA = ArgLocs[I];
662 SDValue Arg = OutVals[I];
663 ISD::ArgFlagsTy Flags = Outs[I].Flags;
665 // Promote the value if needed.
666 switch (VA.getLocInfo()) {
667 case CCValAssign::Full:
669 case CCValAssign::SExt:
670 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
672 case CCValAssign::ZExt:
673 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
675 case CCValAssign::AExt:
676 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
679 llvm_unreachable("Unknown loc info!");
682 // Use local copy if it is a byval arg.
684 Arg = ByValArgs[J++];
686 // Arguments that can be passed on register must be kept at RegsToPass
689 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
691 assert(VA.isMemLoc());
693 if (StackPtr.getNode() == nullptr)
694 StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
695 getPointerTy(DAG.getDataLayout()));
698 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
699 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
701 MemOpChains.push_back(
702 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
706 // Transform all store nodes into one single node because all store nodes are
707 // independent of each other.
708 if (!MemOpChains.empty())
709 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
710 ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
714 // Build a sequence of copy-to-reg nodes chained together with token chain and
715 // flag operands which copy the outgoing args into registers. The InFlag in
716 // necessary since all emitted instructions must be stuck together.
717 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
718 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
719 RegsToPass[I].second, InFlag);
720 InFlag = Chain.getValue(1);
723 // If the callee is a GlobalAddress node (quite common, every direct call is)
724 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
725 // Likewise ExternalSymbol -> TargetExternalSymbol.
726 uint8_t OpFlag = LanaiII::MO_NO_FLAG;
728 Callee = DAG.getTargetGlobalAddress(
729 G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
730 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
731 Callee = DAG.getTargetExternalSymbol(
732 E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
735 // Returns a chain & a flag for retval copy to use.
736 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
737 SmallVector<SDValue, 8> Ops;
738 Ops.push_back(Chain);
739 Ops.push_back(Callee);
741 // Add a register mask operand representing the call-preserved registers.
742 // TODO: Should return-twice functions be handled?
743 const uint32_t *Mask =
744 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
745 assert(Mask && "Missing call preserved mask for calling convention");
746 Ops.push_back(DAG.getRegisterMask(Mask));
748 // Add argument registers to the end of the list so that they are
749 // known live into the call.
750 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
751 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
752 RegsToPass[I].second.getValueType()));
754 if (InFlag.getNode())
755 Ops.push_back(InFlag);
757 Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
758 ArrayRef<SDValue>(&Ops[0], Ops.size()));
759 InFlag = Chain.getValue(1);
761 // Create the CALLSEQ_END node.
762 Chain = DAG.getCALLSEQ_END(
764 DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
765 DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
767 InFlag = Chain.getValue(1);
769 // Handle result values, copying them out of physregs into vregs that we
771 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
775 // LowerCallResult - Lower the result values of a call into the
776 // appropriate copies out of appropriate physical registers.
777 SDValue LanaiTargetLowering::LowerCallResult(
778 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
779 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
780 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
781 // Assign locations to each value returned by this call.
782 SmallVector<CCValAssign, 16> RVLocs;
783 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786 CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
788 // Copy all of the result registers out of their specified physreg.
789 for (unsigned I = 0; I != RVLocs.size(); ++I) {
790 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
791 RVLocs[I].getValVT(), InFlag)
793 InFlag = Chain.getValue(2);
794 InVals.push_back(Chain.getValue(0));
800 //===----------------------------------------------------------------------===//
802 //===----------------------------------------------------------------------===//
804 static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
805 SDValue &RHS, SelectionDAG &DAG) {
806 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
808 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
809 // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
810 // and Lanai only supports integer comparisons, so only provide definitions
812 switch (SetCCOpcode) {
816 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
817 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
818 // X > -1 -> X >= 0 -> is_plus(X)
819 RHS = DAG.getConstant(0, DL, RHS.getValueType());
824 return LPCC::ICC_UGT;
826 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
827 if (RHSC->getZExtValue() == 0)
828 // X < 0 -> is_minus(X)
832 return LPCC::ICC_ULT;
834 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
835 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
836 // X <= -1 -> X < 0 -> is_minus(X)
837 RHS = DAG.getConstant(0, DL, RHS.getValueType());
842 return LPCC::ICC_ULE;
844 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
845 if (RHSC->getZExtValue() == 0)
846 // X >= 0 -> is_plus(X)
850 return LPCC::ICC_UGE;
863 llvm_unreachable("Unsupported comparison.");
865 llvm_unreachable("Unknown integer condition code!");
869 SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
870 SDValue Chain = Op.getOperand(0);
871 SDValue Cond = Op.getOperand(1);
872 SDValue LHS = Op.getOperand(2);
873 SDValue RHS = Op.getOperand(3);
874 SDValue Dest = Op.getOperand(4);
877 LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
878 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
880 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
882 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
886 SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
887 EVT VT = Op->getValueType(0);
891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
895 int64_t MulAmt = C->getSExtValue();
896 int32_t HighestOne = -1;
897 uint32_t NonzeroEntries = 0;
898 int SignedDigit[32] = {0};
900 // Convert to non-adjacent form (NAF) signed-digit representation.
901 // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
902 // minimal Hamming weight representation of a number (on average 1/3 of the
903 // digits will be non-zero vs 1/2 for regular binary representation). And as
904 // the non-zero digits will be the only digits contributing to the instruction
905 // count, this is desirable. The next loop converts it to NAF (following the
906 // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
907 // choosing the non-zero coefficients such that the resulting quotient is
908 // divisible by 2 which will cause the next coefficient to be zero.
909 int64_t E = std::abs(MulAmt);
910 int S = (MulAmt < 0 ? -1 : 1);
919 SignedDigit[I] = S * ZI;
920 if (SignedDigit[I] == 1)
926 // Compute number of instructions required. Due to differences in lowering
927 // between the different processors this count is not exact.
928 // Start by assuming a shift and a add/sub for every non-zero entry (hence
929 // every non-zero entry requires 1 shift and 1 add/sub except for the first
931 int32_t InstrRequired = 2 * NonzeroEntries - 1;
932 // Correct possible over-adding due to shift by 0 (which is not emitted).
933 if (std::abs(MulAmt) % 2 == 1)
935 // Return if the form generated would exceed the instruction threshold.
936 if (InstrRequired > LanaiLowerConstantMulThreshold)
941 SDValue V = Op->getOperand(0);
943 // Initialize the running sum. Set the running sum to the maximal shifted
944 // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
946 if (HighestOne == -1)
947 Res = DAG.getConstant(0, DL, MVT::i32);
949 Res = DAG.getNode(ISD::SHL, DL, VT, V,
950 DAG.getConstant(HighestOne, DL, MVT::i32));
951 SignedDigit[HighestOne] = 0;
954 // Assemble multiplication from shift, add, sub using NAF form and running
956 for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
958 if (SignedDigit[I] == 0)
961 // Shifted multiplicand (v<<i).
963 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
964 if (SignedDigit[I] == 1)
965 Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
966 else if (SignedDigit[I] == -1)
967 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
972 SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
973 SDValue LHS = Op.getOperand(0);
974 SDValue RHS = Op.getOperand(1);
975 SDValue Carry = Op.getOperand(2);
976 SDValue Cond = Op.getOperand(3);
979 LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
980 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
981 SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
982 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
985 SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
986 SDValue LHS = Op.getOperand(0);
987 SDValue RHS = Op.getOperand(1);
988 SDValue Cond = Op.getOperand(2);
991 LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
992 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
994 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
996 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
999 SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
1000 SelectionDAG &DAG) const {
1001 SDValue LHS = Op.getOperand(0);
1002 SDValue RHS = Op.getOperand(1);
1003 SDValue TrueV = Op.getOperand(2);
1004 SDValue FalseV = Op.getOperand(3);
1005 SDValue Cond = Op.getOperand(4);
1008 LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
1009 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
1011 DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1013 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1014 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1018 SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1019 MachineFunction &MF = DAG.getMachineFunction();
1020 LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
1023 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1024 getPointerTy(DAG.getDataLayout()));
1026 // vastart just stores the address of the VarArgsFrameIndex slot into the
1027 // memory location argument.
1028 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1029 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1030 MachinePointerInfo(SV));
1033 SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1034 SelectionDAG &DAG) const {
1035 SDValue Chain = Op.getOperand(0);
1036 SDValue Size = Op.getOperand(1);
1039 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1041 // Get a reference to the stack pointer.
1042 SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1044 // Subtract the dynamic size from the actual stack size to
1045 // obtain the new stack size.
1046 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1048 // For Lanai, the outgoing memory arguments area should be on top of the
1049 // alloca area on the stack i.e., the outgoing memory arguments should be
1050 // at a lower address than the alloca area. Move the alloca area down the
1051 // stack by adding back the space reserved for outgoing arguments to SP
1054 // We do not know what the size of the outgoing args is at this point.
1055 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1056 // stack pointer. We replace this instruction with on that has the correct,
1057 // known offset in emitPrologue().
1058 SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1060 // The Sub result contains the new stack start address, so it
1061 // must be placed in the stack pointer register.
1062 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1064 SDValue Ops[2] = {ArgAdjust, CopyChain};
1065 return DAG.getMergeValues(Ops, DL);
1068 SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
1069 SelectionDAG &DAG) const {
1070 MachineFunction &MF = DAG.getMachineFunction();
1071 MachineFrameInfo &MFI = MF.getFrameInfo();
1072 MFI.setReturnAddressIsTaken(true);
1074 EVT VT = Op.getValueType();
1076 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1078 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1079 const unsigned Offset = -4;
1080 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1081 DAG.getIntPtrConstant(Offset, DL));
1082 return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1085 // Return the link register, which contains the return address.
1086 // Mark it an implicit live-in.
1087 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1088 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1091 SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
1092 SelectionDAG &DAG) const {
1093 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1094 MFI.setFrameAddressIsTaken(true);
1096 EVT VT = Op.getValueType();
1098 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1099 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1101 const unsigned Offset = -8;
1102 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1103 DAG.getIntPtrConstant(Offset, DL));
1105 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1110 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1112 case LanaiISD::ADJDYNALLOC:
1113 return "LanaiISD::ADJDYNALLOC";
1114 case LanaiISD::RET_FLAG:
1115 return "LanaiISD::RET_FLAG";
1116 case LanaiISD::CALL:
1117 return "LanaiISD::CALL";
1118 case LanaiISD::SELECT_CC:
1119 return "LanaiISD::SELECT_CC";
1120 case LanaiISD::SETCC:
1121 return "LanaiISD::SETCC";
1122 case LanaiISD::SUBBF:
1123 return "LanaiISD::SUBBF";
1124 case LanaiISD::SET_FLAG:
1125 return "LanaiISD::SET_FLAG";
1126 case LanaiISD::BR_CC:
1127 return "LanaiISD::BR_CC";
1128 case LanaiISD::Wrapper:
1129 return "LanaiISD::Wrapper";
1131 return "LanaiISD::HI";
1133 return "LanaiISD::LO";
1134 case LanaiISD::SMALL:
1135 return "LanaiISD::SMALL";
1141 SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
1142 SelectionDAG &DAG) const {
1144 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1145 const Constant *C = N->getConstVal();
1146 const LanaiTargetObjectFile *TLOF =
1147 static_cast<const LanaiTargetObjectFile *>(
1148 getTargetMachine().getObjFileLowering());
1150 // If the code model is small or constant will be placed in the small section,
1151 // then assume address will fit in 21-bits.
1152 if (getTargetMachine().getCodeModel() == CodeModel::Small ||
1153 TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1154 SDValue Small = DAG.getTargetConstantPool(
1155 C, MVT::i32, N->getAlignment(), N->getOffset(), LanaiII::MO_NO_FLAG);
1156 return DAG.getNode(ISD::OR, DL, MVT::i32,
1157 DAG.getRegister(Lanai::R0, MVT::i32),
1158 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1160 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1161 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1163 SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1164 N->getOffset(), OpFlagHi);
1165 SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1166 N->getOffset(), OpFlagLo);
1167 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1168 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1169 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1174 SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
1175 SelectionDAG &DAG) const {
1177 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1178 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1180 const LanaiTargetObjectFile *TLOF =
1181 static_cast<const LanaiTargetObjectFile *>(
1182 getTargetMachine().getObjFileLowering());
1184 // If the code model is small or global variable will be placed in the small
1185 // section, then assume address will fit in 21-bits.
1186 const GlobalObject *GO = GV->getBaseObject();
1187 if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1188 SDValue Small = DAG.getTargetGlobalAddress(
1189 GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1190 return DAG.getNode(ISD::OR, DL, MVT::i32,
1191 DAG.getRegister(Lanai::R0, MVT::i32),
1192 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1194 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1195 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1197 // Create the TargetGlobalAddress node, folding in the constant offset.
1198 SDValue Hi = DAG.getTargetGlobalAddress(
1199 GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1200 SDValue Lo = DAG.getTargetGlobalAddress(
1201 GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1202 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1203 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1204 return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1208 SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
1209 SelectionDAG &DAG) const {
1211 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1213 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1214 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1216 SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1217 SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1218 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1219 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1220 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1224 SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
1225 SelectionDAG &DAG) const {
1227 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1229 // If the code model is small assume address will fit in 21-bits.
1230 if (getTargetMachine().getCodeModel() == CodeModel::Small) {
1231 SDValue Small = DAG.getTargetJumpTable(
1232 JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1233 return DAG.getNode(ISD::OR, DL, MVT::i32,
1234 DAG.getRegister(Lanai::R0, MVT::i32),
1235 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1237 uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1238 uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1240 SDValue Hi = DAG.getTargetJumpTable(
1241 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1242 SDValue Lo = DAG.getTargetJumpTable(
1243 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1244 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1245 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1246 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1251 SDValue LanaiTargetLowering::LowerSHL_PARTS(SDValue Op,
1252 SelectionDAG &DAG) const {
1253 EVT VT = Op.getValueType();
1254 unsigned VTBits = VT.getSizeInBits();
1256 assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1257 SDValue ShOpLo = Op.getOperand(0);
1258 SDValue ShOpHi = Op.getOperand(1);
1259 SDValue ShAmt = Op.getOperand(2);
1261 // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1262 // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1263 // HiBitsForHi = ShOpHi << ShAmt
1264 // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1265 // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1266 // return (Hi << 32) | Lo;
1268 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1269 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1270 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1272 // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1273 // wanted 0, so CSEL it directly.
1274 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1275 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1276 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1278 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1279 DAG.getConstant(VTBits, dl, MVT::i32));
1280 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1281 SDValue HiForNormalShift =
1282 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1284 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1286 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1288 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1290 // Lanai shifts of larger than register sizes are wrapped rather than
1291 // clamped, so we can't just emit "lo << b" if b is too big.
1292 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1293 SDValue Lo = DAG.getSelect(
1294 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1296 SDValue Ops[2] = {Lo, Hi};
1297 return DAG.getMergeValues(Ops, dl);
1300 SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
1301 SelectionDAG &DAG) const {
1302 MVT VT = Op.getSimpleValueType();
1303 unsigned VTBits = VT.getSizeInBits();
1305 SDValue ShOpLo = Op.getOperand(0);
1306 SDValue ShOpHi = Op.getOperand(1);
1307 SDValue ShAmt = Op.getOperand(2);
1309 // Performs the following for a >> b:
1310 // unsigned r_high = a_high >> b;
1311 // r_high = (32 - b <= 0) ? 0 : r_high;
1313 // unsigned r_low = a_low >> b;
1314 // r_low = (32 - b <= 0) ? r_high : r_low;
1315 // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1316 // return (unsigned long long)r_high << 32 | r_low;
1317 // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1318 // mask the shift amount.
1320 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1321 SDValue NegatedPlus32 = DAG.getNode(
1322 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1323 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1325 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1326 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1328 SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1329 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1331 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1332 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1333 Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1334 DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1336 SDValue Ops[2] = {Lo, Hi};
1337 return DAG.getMergeValues(Ops, dl);
1340 // Helper function that checks if N is a null or all ones constant.
1341 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1342 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1345 // Return true if N is conditionally 0 or all ones.
1346 // Detects these expressions where cc is an i1 value:
1348 // (select cc 0, y) [AllOnes=0]
1349 // (select cc y, 0) [AllOnes=0]
1350 // (zext cc) [AllOnes=0]
1351 // (sext cc) [AllOnes=0/1]
1352 // (select cc -1, y) [AllOnes=1]
1353 // (select cc y, -1) [AllOnes=1]
1355 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1356 // all ones operand (AllOnes true).
1357 // * Invert is set when N is the all zero/ones constant when CC is false.
1358 // * OtherOp is set to the alternative value of N.
1360 // For example, for (select cc X, Y) and AllOnes = 0 if:
1361 // * X = 0, Invert = False and OtherOp = Y
1362 // * Y = 0, Invert = True and OtherOp = X
1363 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1364 bool &Invert, SDValue &OtherOp,
1365 SelectionDAG &DAG) {
1366 switch (N->getOpcode()) {
1370 CC = N->getOperand(0);
1371 SDValue N1 = N->getOperand(1);
1372 SDValue N2 = N->getOperand(2);
1373 if (isZeroOrAllOnes(N1, AllOnes)) {
1378 if (isZeroOrAllOnes(N2, AllOnes)) {
1385 case ISD::ZERO_EXTEND: {
1386 // (zext cc) can never be the all ones value.
1389 CC = N->getOperand(0);
1390 if (CC.getValueType() != MVT::i1)
1393 EVT VT = N->getValueType(0);
1394 OtherOp = DAG.getConstant(1, dl, VT);
1398 case ISD::SIGN_EXTEND: {
1399 CC = N->getOperand(0);
1400 if (CC.getValueType() != MVT::i1)
1403 EVT VT = N->getValueType(0);
1406 // When looking for an AllOnes constant, N is an sext, and the 'other'
1408 OtherOp = DAG.getConstant(0, dl, VT);
1411 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
1417 // Combine a constant select operand into its use:
1419 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1420 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1421 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1422 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1423 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1425 // The transform is rejected if the select doesn't have a constant operand that
1426 // is null, or all ones when AllOnes is set.
1428 // Also recognize sext/zext from i1:
1430 // (add (zext cc), x) -> (select cc (add x, 1), x)
1431 // (add (sext cc), x) -> (select cc (add x, -1), x)
1433 // These transformations eventually create predicated instructions.
1434 static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1435 TargetLowering::DAGCombinerInfo &DCI,
1437 SelectionDAG &DAG = DCI.DAG;
1438 EVT VT = N->getValueType(0);
1439 SDValue NonConstantVal;
1442 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1443 NonConstantVal, DAG))
1446 // Slct is now know to be the desired identity constant when CC is true.
1447 SDValue TrueVal = OtherOp;
1449 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1450 // Unless SwapSelectOps says CC should be false.
1452 std::swap(TrueVal, FalseVal);
1454 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1457 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1459 combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1461 SDValue N0 = N->getOperand(0);
1462 SDValue N1 = N->getOperand(1);
1463 if (N0.getNode()->hasOneUse())
1464 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1466 if (N1.getNode()->hasOneUse())
1467 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1472 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1473 static SDValue PerformSUBCombine(SDNode *N,
1474 TargetLowering::DAGCombinerInfo &DCI) {
1475 SDValue N0 = N->getOperand(0);
1476 SDValue N1 = N->getOperand(1);
1478 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1479 if (N1.getNode()->hasOneUse())
1480 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1486 SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
1487 DAGCombinerInfo &DCI) const {
1488 switch (N->getOpcode()) {
1494 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1496 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1498 return PerformSUBCombine(N, DCI);
1504 void LanaiTargetLowering::computeKnownBitsForTargetNode(
1505 const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1506 const SelectionDAG &DAG, unsigned Depth) const {
1507 unsigned BitWidth = Known.getBitWidth();
1508 switch (Op.getOpcode()) {
1511 case LanaiISD::SETCC:
1512 Known = KnownBits(BitWidth);
1513 Known.Zero.setBits(1, BitWidth);
1515 case LanaiISD::SELECT_CC:
1517 DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
1518 DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
1519 Known.Zero &= Known2.Zero;
1520 Known.One &= Known2.One;