1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Lanai uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
19 #include "LanaiRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 // Return with a flag operand. Operand 0 is the chain operand.
33 // CALL - These operations represent an abstract call instruction, which
34 // includes a bunch of information.
37 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
38 // is condition code and operand 4 is flag operand.
41 // SETCC - Store the conditional code to a register.
44 // SET_FLAG - Set flag compare.
47 // SUBBF - Subtract with borrow that sets flags.
50 // BR_CC - Used to glue together a conditional branch and comparison
53 // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
54 // and TargetGlobalAddress.
57 // Get the Higher/Lower 16 bits from a 32-bit immediate.
61 // Small 21-bit immediate in global memory.
64 } // namespace LanaiISD
68 class LanaiTargetLowering : public TargetLowering {
70 LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
72 // LowerOperation - Provide custom lowering hooks for some operations.
73 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
75 // getTargetNodeName - This method returns the name of a target specific
77 const char *getTargetNodeName(unsigned Opcode) const override;
79 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
94 unsigned getRegisterByName(const char *RegName, EVT VT,
95 SelectionDAG &DAG) const override;
96 std::pair<unsigned, const TargetRegisterClass *>
97 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
98 StringRef Constraint, MVT VT) const override;
100 getSingleConstraintMatchWeight(AsmOperandInfo &Info,
101 const char *Constraint) const override;
102 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
103 std::vector<SDValue> &Ops,
104 SelectionDAG &DAG) const override;
106 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
108 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
109 const APInt &DemandedElts,
110 const SelectionDAG &DAG,
111 unsigned Depth = 0) const override;
114 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
115 CallingConv::ID CallConv, bool IsVarArg,
117 const SmallVectorImpl<ISD::OutputArg> &Outs,
118 const SmallVectorImpl<SDValue> &OutVals,
119 const SmallVectorImpl<ISD::InputArg> &Ins,
120 const SDLoc &dl, SelectionDAG &DAG,
121 SmallVectorImpl<SDValue> &InVals) const;
123 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
125 const SmallVectorImpl<ISD::InputArg> &Ins,
126 const SDLoc &DL, SelectionDAG &DAG,
127 SmallVectorImpl<SDValue> &InVals) const;
129 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
130 CallingConv::ID CallConv, bool IsVarArg,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
132 const SDLoc &DL, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals) const;
135 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
136 SmallVectorImpl<SDValue> &InVals) const override;
138 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
141 const SDLoc &DL, SelectionDAG &DAG,
142 SmallVectorImpl<SDValue> &InVals) const override;
144 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
145 const SmallVectorImpl<ISD::OutputArg> &Outs,
146 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
147 SelectionDAG &DAG) const override;
149 const LanaiRegisterInfo *TRI;
153 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H