1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that Lanai uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
18 #include "LanaiRegisterInfo.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 // Return with a flag operand. Operand 0 is the chain operand.
32 // CALL - These operations represent an abstract call instruction, which
33 // includes a bunch of information.
36 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
37 // is condition code and operand 4 is flag operand.
40 // SETCC - Store the conditional code to a register.
43 // SET_FLAG - Set flag compare.
46 // SUBBF - Subtract with borrow that sets flags.
49 // BR_CC - Used to glue together a conditional branch and comparison
52 // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
53 // and TargetGlobalAddress.
56 // Get the Higher/Lower 16 bits from a 32-bit immediate.
60 // Small 21-bit immediate in global memory.
63 } // namespace LanaiISD
67 class LanaiTargetLowering : public TargetLowering {
69 LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
71 // LowerOperation - Provide custom lowering hooks for some operations.
72 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
74 // getTargetNodeName - This method returns the name of a target specific
76 const char *getTargetNodeName(unsigned Opcode) const override;
78 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
79 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
93 unsigned getRegisterByName(const char *RegName, EVT VT,
94 SelectionDAG &DAG) const override;
95 std::pair<unsigned, const TargetRegisterClass *>
96 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
97 StringRef Constraint, MVT VT) const override;
99 getSingleConstraintMatchWeight(AsmOperandInfo &Info,
100 const char *Constraint) const override;
101 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
102 std::vector<SDValue> &Ops,
103 SelectionDAG &DAG) const override;
105 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
107 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
108 const APInt &DemandedElts,
109 const SelectionDAG &DAG,
110 unsigned Depth = 0) const override;
113 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
114 CallingConv::ID CallConv, bool IsVarArg,
116 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<SDValue> &OutVals,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 const SDLoc &dl, SelectionDAG &DAG,
120 SmallVectorImpl<SDValue> &InVals) const;
122 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
124 const SmallVectorImpl<ISD::InputArg> &Ins,
125 const SDLoc &DL, SelectionDAG &DAG,
126 SmallVectorImpl<SDValue> &InVals) const;
128 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
129 CallingConv::ID CallConv, bool IsVarArg,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
131 const SDLoc &DL, SelectionDAG &DAG,
132 SmallVectorImpl<SDValue> &InVals) const;
134 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
135 SmallVectorImpl<SDValue> &InVals) const override;
137 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
139 const SmallVectorImpl<ISD::InputArg> &Ins,
140 const SDLoc &DL, SelectionDAG &DAG,
141 SmallVectorImpl<SDValue> &InVals) const override;
143 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
144 const SmallVectorImpl<ISD::OutputArg> &Outs,
145 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
146 SelectionDAG &DAG) const override;
148 const LanaiRegisterInfo *TRI;
152 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H