1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Lanai uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
19 #include "LanaiRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 // Return with a flag operand. Operand 0 is the chain operand.
33 // CALL - These operations represent an abstract call instruction, which
34 // includes a bunch of information.
37 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
38 // is condition code and operand 4 is flag operand.
41 // SETCC - Store the conditional code to a register.
44 // SET_FLAG - Set flag compare.
47 // SUBBF - Subtract with borrow that sets flags.
50 // BR_CC - Used to glue together a conditional branch and comparison
53 // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
54 // and TargetGlobalAddress.
57 // Get the Higher/Lower 16 bits from a 32-bit immediate.
61 // Small 21-bit immediate in global memory.
64 } // namespace LanaiISD
68 class LanaiTargetLowering : public TargetLowering {
70 LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
72 // LowerOperation - Provide custom lowering hooks for some operations.
73 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
75 // getTargetNodeName - This method returns the name of a target specific
77 const char *getTargetNodeName(unsigned Opcode) const override;
79 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
95 unsigned getRegisterByName(const char *RegName, EVT VT,
96 SelectionDAG &DAG) const override;
97 std::pair<unsigned, const TargetRegisterClass *>
98 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
99 StringRef Constraint, MVT VT) const override;
101 getSingleConstraintMatchWeight(AsmOperandInfo &Info,
102 const char *Constraint) const override;
103 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
104 std::vector<SDValue> &Ops,
105 SelectionDAG &DAG) const override;
107 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
109 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
110 const APInt &DemandedElts,
111 const SelectionDAG &DAG,
112 unsigned Depth = 0) const override;
115 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
116 CallingConv::ID CallConv, bool IsVarArg,
118 const SmallVectorImpl<ISD::OutputArg> &Outs,
119 const SmallVectorImpl<SDValue> &OutVals,
120 const SmallVectorImpl<ISD::InputArg> &Ins,
121 const SDLoc &dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const;
124 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
127 const SDLoc &DL, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals) const;
130 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
131 CallingConv::ID CallConv, bool IsVarArg,
132 const SmallVectorImpl<ISD::InputArg> &Ins,
133 const SDLoc &DL, SelectionDAG &DAG,
134 SmallVectorImpl<SDValue> &InVals) const;
136 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
137 SmallVectorImpl<SDValue> &InVals) const override;
139 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
141 const SmallVectorImpl<ISD::InputArg> &Ins,
142 const SDLoc &DL, SelectionDAG &DAG,
143 SmallVectorImpl<SDValue> &InVals) const override;
145 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
146 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
148 SelectionDAG &DAG) const override;
150 const LanaiRegisterInfo *TRI;
154 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H