1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DerivedTypes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetLowering.h"
33 #define DEBUG_TYPE "msp430-isel"
36 struct MSP430ISelAddressMode {
42 struct { // This is really a union, discriminated by BaseType!
48 const GlobalValue *GV;
50 const BlockAddress *BlockAddr;
53 unsigned Align; // CP alignment.
55 MSP430ISelAddressMode()
56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
57 BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
60 bool hasSymbolicDisplacement() const {
61 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
64 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
65 LLVM_DUMP_METHOD void dump() {
66 errs() << "MSP430ISelAddressMode " << this << '\n';
67 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
68 errs() << "Base.Reg ";
69 Base.Reg.getNode()->dump();
70 } else if (BaseType == FrameIndexBase) {
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
73 errs() << " Disp " << Disp << '\n';
80 errs() << " Align" << Align << '\n';
85 errs() << " JT" << JT << " Align" << Align << '\n';
91 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
92 /// instructions for SelectionDAG operations.
95 class MSP430DAGToDAGISel : public SelectionDAGISel {
97 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
98 : SelectionDAGISel(TM, OptLevel) {}
100 StringRef getPassName() const override {
101 return "MSP430 DAG->DAG Pattern Instruction Selection";
104 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
105 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
106 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
108 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
109 std::vector<SDValue> &OutOps) override;
111 // Include the pieces autogenerated from the target description.
112 #include "MSP430GenDAGISel.inc"
115 void Select(SDNode *N) override;
116 bool tryIndexedLoad(SDNode *Op);
117 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
120 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
122 } // end anonymous namespace
124 /// createMSP430ISelDag - This pass converts a legalized DAG into a
125 /// MSP430-specific DAG, ready for instruction scheduling.
127 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
128 CodeGenOpt::Level OptLevel) {
129 return new MSP430DAGToDAGISel(TM, OptLevel);
133 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
134 /// These wrap things that will resolve down into a symbol reference. If no
135 /// match is possible, this returns true, otherwise it returns false.
136 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
137 // If the addressing mode already has a symbol as the displacement, we can
138 // never match another symbol.
139 if (AM.hasSymbolicDisplacement())
142 SDValue N0 = N.getOperand(0);
144 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
145 AM.GV = G->getGlobal();
146 AM.Disp += G->getOffset();
147 //AM.SymbolFlags = G->getTargetFlags();
148 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
149 AM.CP = CP->getConstVal();
150 AM.Align = CP->getAlignment();
151 AM.Disp += CP->getOffset();
152 //AM.SymbolFlags = CP->getTargetFlags();
153 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
154 AM.ES = S->getSymbol();
155 //AM.SymbolFlags = S->getTargetFlags();
156 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
157 AM.JT = J->getIndex();
158 //AM.SymbolFlags = J->getTargetFlags();
160 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
161 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
166 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
167 /// specified addressing mode without any further recursion.
168 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
169 // Is the base register already occupied?
170 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
171 // If so, we cannot select it.
175 // Default, generate it as a register.
176 AM.BaseType = MSP430ISelAddressMode::RegBase;
181 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
182 DEBUG(errs() << "MatchAddress: "; AM.dump());
184 switch (N.getOpcode()) {
186 case ISD::Constant: {
187 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
192 case MSP430ISD::Wrapper:
193 if (!MatchWrapper(N, AM))
197 case ISD::FrameIndex:
198 if (AM.BaseType == MSP430ISelAddressMode::RegBase
199 && AM.Base.Reg.getNode() == nullptr) {
200 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
201 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
207 MSP430ISelAddressMode Backup = AM;
208 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
209 !MatchAddress(N.getNode()->getOperand(1), AM))
212 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
213 !MatchAddress(N.getNode()->getOperand(0), AM))
221 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
222 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
223 MSP430ISelAddressMode Backup = AM;
224 uint64_t Offset = CN->getSExtValue();
225 // Start with the LHS as an addr mode.
226 if (!MatchAddress(N.getOperand(0), AM) &&
227 // Address could not have picked a GV address for the displacement.
229 // Check to see if the LHS & C is zero.
230 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
239 return MatchAddressBase(N, AM);
242 /// SelectAddr - returns true if it is able pattern match an addressing mode.
243 /// It returns the operands which make up the maximal addressing mode it can
244 /// match by reference.
245 bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
246 SDValue &Base, SDValue &Disp) {
247 MSP430ISelAddressMode AM;
249 if (MatchAddress(N, AM))
252 EVT VT = N.getValueType();
253 if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
254 if (!AM.Base.Reg.getNode())
255 AM.Base.Reg = CurDAG->getRegister(0, VT);
258 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
259 ? CurDAG->getTargetFrameIndex(
261 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
265 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
267 0/*AM.SymbolFlags*/);
269 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
270 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
272 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
273 else if (AM.JT != -1)
274 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
275 else if (AM.BlockAddr)
276 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
277 0/*AM.SymbolFlags*/);
279 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
284 bool MSP430DAGToDAGISel::
285 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
286 std::vector<SDValue> &OutOps) {
288 switch (ConstraintID) {
289 default: return true;
290 case InlineAsm::Constraint_m: // memory
291 if (!SelectAddr(Op, Op0, Op1))
296 OutOps.push_back(Op0);
297 OutOps.push_back(Op1);
301 static bool isValidIndexedLoad(const LoadSDNode *LD) {
302 ISD::MemIndexedMode AM = LD->getAddressingMode();
303 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
306 EVT VT = LD->getMemoryVT();
308 switch (VT.getSimpleVT().SimpleTy) {
311 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
317 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
328 bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
329 LoadSDNode *LD = cast<LoadSDNode>(N);
330 if (!isValidIndexedLoad(LD))
333 MVT VT = LD->getMemoryVT().getSimpleVT();
336 switch (VT.SimpleTy) {
338 Opcode = MSP430::MOV8rm_POST;
341 Opcode = MSP430::MOV16rm_POST;
348 CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
349 LD->getBasePtr(), LD->getChain()));
353 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
354 unsigned Opc8, unsigned Opc16) {
355 if (N1.getOpcode() == ISD::LOAD &&
357 IsLegalToFold(N1, Op, Op, OptLevel)) {
358 LoadSDNode *LD = cast<LoadSDNode>(N1);
359 if (!isValidIndexedLoad(LD))
362 MVT VT = LD->getMemoryVT().getSimpleVT();
363 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
364 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
365 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
366 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
368 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
369 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
371 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
372 // Transfer writeback.
373 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
381 void MSP430DAGToDAGISel::Select(SDNode *Node) {
384 // Dump information about the Node being selected
385 DEBUG(errs() << "Selecting: ");
386 DEBUG(Node->dump(CurDAG));
387 DEBUG(errs() << "\n");
389 // If we have a custom node, we already have selected!
390 if (Node->isMachineOpcode()) {
391 DEBUG(errs() << "== ";
398 // Few custom selection stuff.
399 switch (Node->getOpcode()) {
401 case ISD::FrameIndex: {
402 assert(Node->getValueType(0) == MVT::i16);
403 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
404 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
405 if (Node->hasOneUse()) {
406 CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
407 CurDAG->getTargetConstant(0, dl, MVT::i16));
410 ReplaceNode(Node, CurDAG->getMachineNode(
411 MSP430::ADDframe, dl, MVT::i16, TFI,
412 CurDAG->getTargetConstant(0, dl, MVT::i16)));
416 if (tryIndexedLoad(Node))
418 // Other cases are autogenerated.
421 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
422 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
424 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
425 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
428 // Other cases are autogenerated.
431 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
432 MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
435 // Other cases are autogenerated.
438 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
439 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
441 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
442 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
445 // Other cases are autogenerated.
448 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
449 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
451 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
452 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
455 // Other cases are autogenerated.
458 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
459 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
461 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
462 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
465 // Other cases are autogenerated.
469 // Select the default instruction