1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
34 #define DEBUG_TYPE "msp430-isel"
37 struct MSP430ISelAddressMode {
43 struct { // This is really a union, discriminated by BaseType!
49 const GlobalValue *GV;
51 const BlockAddress *BlockAddr;
54 unsigned Align; // CP alignment.
56 MSP430ISelAddressMode()
57 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
58 BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
61 bool hasSymbolicDisplacement() const {
62 return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
65 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
66 LLVM_DUMP_METHOD void dump() {
67 errs() << "MSP430ISelAddressMode " << this << '\n';
68 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
69 errs() << "Base.Reg ";
70 Base.Reg.getNode()->dump();
71 } else if (BaseType == FrameIndexBase) {
72 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
74 errs() << " Disp " << Disp << '\n';
81 errs() << " Align" << Align << '\n';
86 errs() << " JT" << JT << " Align" << Align << '\n';
92 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
93 /// instructions for SelectionDAG operations.
96 class MSP430DAGToDAGISel : public SelectionDAGISel {
98 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
99 : SelectionDAGISel(TM, OptLevel) {}
102 StringRef getPassName() const override {
103 return "MSP430 DAG->DAG Pattern Instruction Selection";
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
110 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
111 std::vector<SDValue> &OutOps) override;
113 // Include the pieces autogenerated from the target description.
114 #include "MSP430GenDAGISel.inc"
116 // Main method to transform nodes into machine nodes.
117 void Select(SDNode *N) override;
119 bool tryIndexedLoad(SDNode *Op);
120 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
125 } // end anonymous namespace
127 /// createMSP430ISelDag - This pass converts a legalized DAG into a
128 /// MSP430-specific DAG, ready for instruction scheduling.
130 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
131 CodeGenOpt::Level OptLevel) {
132 return new MSP430DAGToDAGISel(TM, OptLevel);
136 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
137 /// These wrap things that will resolve down into a symbol reference. If no
138 /// match is possible, this returns true, otherwise it returns false.
139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
140 // If the addressing mode already has a symbol as the displacement, we can
141 // never match another symbol.
142 if (AM.hasSymbolicDisplacement())
145 SDValue N0 = N.getOperand(0);
147 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
148 AM.GV = G->getGlobal();
149 AM.Disp += G->getOffset();
150 //AM.SymbolFlags = G->getTargetFlags();
151 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
152 AM.CP = CP->getConstVal();
153 AM.Align = CP->getAlignment();
154 AM.Disp += CP->getOffset();
155 //AM.SymbolFlags = CP->getTargetFlags();
156 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
157 AM.ES = S->getSymbol();
158 //AM.SymbolFlags = S->getTargetFlags();
159 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
160 AM.JT = J->getIndex();
161 //AM.SymbolFlags = J->getTargetFlags();
163 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
164 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
169 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
170 /// specified addressing mode without any further recursion.
171 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
172 // Is the base register already occupied?
173 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
174 // If so, we cannot select it.
178 // Default, generate it as a register.
179 AM.BaseType = MSP430ISelAddressMode::RegBase;
184 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
185 LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
187 switch (N.getOpcode()) {
189 case ISD::Constant: {
190 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
195 case MSP430ISD::Wrapper:
196 if (!MatchWrapper(N, AM))
200 case ISD::FrameIndex:
201 if (AM.BaseType == MSP430ISelAddressMode::RegBase
202 && AM.Base.Reg.getNode() == nullptr) {
203 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
204 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
210 MSP430ISelAddressMode Backup = AM;
211 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212 !MatchAddress(N.getNode()->getOperand(1), AM))
215 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216 !MatchAddress(N.getNode()->getOperand(0), AM))
224 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
226 MSP430ISelAddressMode Backup = AM;
227 uint64_t Offset = CN->getSExtValue();
228 // Start with the LHS as an addr mode.
229 if (!MatchAddress(N.getOperand(0), AM) &&
230 // Address could not have picked a GV address for the displacement.
232 // Check to see if the LHS & C is zero.
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
242 return MatchAddressBase(N, AM);
245 /// SelectAddr - returns true if it is able pattern match an addressing mode.
246 /// It returns the operands which make up the maximal addressing mode it can
247 /// match by reference.
248 bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
249 SDValue &Base, SDValue &Disp) {
250 MSP430ISelAddressMode AM;
252 if (MatchAddress(N, AM))
255 if (AM.BaseType == MSP430ISelAddressMode::RegBase)
256 if (!AM.Base.Reg.getNode())
257 AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16);
259 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
260 ? CurDAG->getTargetFrameIndex(
262 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
266 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
268 0/*AM.SymbolFlags*/);
270 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
271 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
273 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
274 else if (AM.JT != -1)
275 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
276 else if (AM.BlockAddr)
277 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
278 0/*AM.SymbolFlags*/);
280 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
285 bool MSP430DAGToDAGISel::
286 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
287 std::vector<SDValue> &OutOps) {
289 switch (ConstraintID) {
290 default: return true;
291 case InlineAsm::Constraint_m: // memory
292 if (!SelectAddr(Op, Op0, Op1))
297 OutOps.push_back(Op0);
298 OutOps.push_back(Op1);
302 static bool isValidIndexedLoad(const LoadSDNode *LD) {
303 ISD::MemIndexedMode AM = LD->getAddressingMode();
304 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
307 EVT VT = LD->getMemoryVT();
309 switch (VT.getSimpleVT().SimpleTy) {
312 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
318 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
329 bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
330 LoadSDNode *LD = cast<LoadSDNode>(N);
331 if (!isValidIndexedLoad(LD))
334 MVT VT = LD->getMemoryVT().getSimpleVT();
337 switch (VT.SimpleTy) {
339 Opcode = MSP430::MOV8rp;
342 Opcode = MSP430::MOV16rp;
349 CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
350 LD->getBasePtr(), LD->getChain()));
354 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
355 unsigned Opc8, unsigned Opc16) {
356 if (N1.getOpcode() == ISD::LOAD &&
358 IsLegalToFold(N1, Op, Op, OptLevel)) {
359 LoadSDNode *LD = cast<LoadSDNode>(N1);
360 if (!isValidIndexedLoad(LD))
363 MVT VT = LD->getMemoryVT().getSimpleVT();
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
365 MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand();
366 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
368 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
369 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemRef});
371 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
372 // Transfer writeback.
373 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
381 void MSP430DAGToDAGISel::Select(SDNode *Node) {
384 // If we have a custom node, we already have selected!
385 if (Node->isMachineOpcode()) {
386 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
391 // Few custom selection stuff.
392 switch (Node->getOpcode()) {
394 case ISD::FrameIndex: {
395 assert(Node->getValueType(0) == MVT::i16);
396 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
397 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
398 if (Node->hasOneUse()) {
399 CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
400 CurDAG->getTargetConstant(0, dl, MVT::i16));
403 ReplaceNode(Node, CurDAG->getMachineNode(
404 MSP430::ADDframe, dl, MVT::i16, TFI,
405 CurDAG->getTargetConstant(0, dl, MVT::i16)));
409 if (tryIndexedLoad(Node))
411 // Other cases are autogenerated.
414 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
415 MSP430::ADD8rp, MSP430::ADD16rp))
417 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
418 MSP430::ADD8rp, MSP430::ADD16rp))
421 // Other cases are autogenerated.
424 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
425 MSP430::SUB8rp, MSP430::SUB16rp))
428 // Other cases are autogenerated.
431 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
432 MSP430::AND8rp, MSP430::AND16rp))
434 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
435 MSP430::AND8rp, MSP430::AND16rp))
438 // Other cases are autogenerated.
441 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
442 MSP430::BIS8rp, MSP430::BIS16rp))
444 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
445 MSP430::BIS8rp, MSP430::BIS16rp))
448 // Other cases are autogenerated.
451 if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
452 MSP430::XOR8rp, MSP430::XOR16rp))
454 else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
455 MSP430::XOR8rp, MSP430::XOR16rp))
458 // Other cases are autogenerated.
462 // Select the default instruction