1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
24 enum NodeType : unsigned {
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 /// Return with a flag operand. Operand 0 is the chain operand.
30 /// Same as RET_FLAG, but used for returning from ISRs.
33 /// Y = R{R,L}A X, rotate right (left) arithmetically
36 /// Y = RRC X, rotate right via carry
39 /// Rotate right via carry, carry gets cleared beforehand by clrc
42 /// CALL - These operations represent an abstract call
43 /// instruction, which includes a bunch of information.
46 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
47 /// and TargetGlobalAddress.
50 /// CMP - Compare instruction.
53 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
54 /// operand produced by a CMP instruction.
57 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
58 /// is the block to branch if condition is true, operand 2 is the
59 /// condition code, and operand 3 is the flag operand produced by a CMP
63 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
64 /// is condition code and operand 4 is flag operand.
67 /// DADD - Decimal addition with carry
68 /// TODO Nothing generates a node of this type yet.
73 class MSP430Subtarget;
74 class MSP430TargetLowering : public TargetLowering {
76 explicit MSP430TargetLowering(const TargetMachine &TM,
77 const MSP430Subtarget &STI);
79 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
83 /// LowerOperation - Provide custom lowering hooks for some operations.
84 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
86 /// getTargetNodeName - This method returns the name of a target specific
88 const char *getTargetNodeName(unsigned Opcode) const override;
90 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
102 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
104 TargetLowering::ConstraintType
105 getConstraintType(StringRef Constraint) const override;
106 std::pair<unsigned, const TargetRegisterClass *>
107 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
108 StringRef Constraint, MVT VT) const override;
110 /// isTruncateFree - Return true if it's free to truncate a value of type
111 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
112 /// register R15W to i8 by referencing its sub-register R15B.
113 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
114 bool isTruncateFree(EVT VT1, EVT VT2) const override;
116 /// isZExtFree - Return true if any actual instruction that defines a value
117 /// of type Ty1 implicit zero-extends the value to Ty2 in the result
118 /// register. This does not necessarily include registers defined in unknown
119 /// ways, such as incoming arguments, or copies from unknown virtual
120 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
121 /// necessarily apply to truncate instructions. e.g. on msp430, all
122 /// instructions that define 8-bit values implicit zero-extend the result
124 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
125 bool isZExtFree(EVT VT1, EVT VT2) const override;
126 bool isZExtFree(SDValue Val, EVT VT2) const override;
129 EmitInstrWithCustomInserter(MachineInstr &MI,
130 MachineBasicBlock *BB) const override;
131 MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
132 MachineBasicBlock *BB) const;
135 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
136 CallingConv::ID CallConv, bool isVarArg,
138 const SmallVectorImpl<ISD::OutputArg> &Outs,
139 const SmallVectorImpl<SDValue> &OutVals,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
141 const SDLoc &dl, SelectionDAG &DAG,
142 SmallVectorImpl<SDValue> &InVals) const;
144 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
146 const SmallVectorImpl<ISD::InputArg> &Ins,
147 const SDLoc &dl, SelectionDAG &DAG,
148 SmallVectorImpl<SDValue> &InVals) const;
150 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
151 CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
153 const SDLoc &dl, SelectionDAG &DAG,
154 SmallVectorImpl<SDValue> &InVals) const;
157 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
159 const SDLoc &dl, SelectionDAG &DAG,
160 SmallVectorImpl<SDValue> &InVals) const override;
162 LowerCall(TargetLowering::CallLoweringInfo &CLI,
163 SmallVectorImpl<SDValue> &InVals) const override;
165 bool CanLowerReturn(CallingConv::ID CallConv,
168 const SmallVectorImpl<ISD::OutputArg> &Outs,
169 LLVMContext &Context) const override;
171 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
172 const SmallVectorImpl<ISD::OutputArg> &Outs,
173 const SmallVectorImpl<SDValue> &OutVals,
174 const SDLoc &dl, SelectionDAG &DAG) const override;
176 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
179 ISD::MemIndexedMode &AM,
180 SelectionDAG &DAG) const override;