1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MSP430InstrInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MSP430GenInstrInfo.inc"
30 // Pin the vtable to this file.
31 void MSP430InstrInfo::anchor() {}
33 MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI)
34 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
37 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 unsigned SrcReg, bool isKill, int FrameIdx,
40 const TargetRegisterClass *RC,
41 const TargetRegisterInfo *TRI) const {
43 if (MI != MBB.end()) DL = MI->getDebugLoc();
44 MachineFunction &MF = *MBB.getParent();
45 MachineFrameInfo &MFI = MF.getFrameInfo();
47 MachineMemOperand *MMO = MF.getMachineMemOperand(
48 MachinePointerInfo::getFixedStack(MF, FrameIdx),
49 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
50 MFI.getObjectAlignment(FrameIdx));
52 if (RC == &MSP430::GR16RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56 else if (RC == &MSP430::GR8RegClass)
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
58 .addFrameIndex(FrameIdx).addImm(0)
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
61 llvm_unreachable("Cannot store this register to stack slot!");
64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, int FrameIdx,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const{
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = MF.getFrameInfo();
74 MachineMemOperand *MMO = MF.getMachineMemOperand(
75 MachinePointerInfo::getFixedStack(MF, FrameIdx),
76 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
77 MFI.getObjectAlignment(FrameIdx));
79 if (RC == &MSP430::GR16RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
82 .addImm(0).addMemOperand(MMO);
83 else if (RC == &MSP430::GR8RegClass)
84 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
86 .addImm(0).addMemOperand(MMO);
88 llvm_unreachable("Cannot store this register to stack slot!");
91 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I,
93 const DebugLoc &DL, unsigned DestReg,
94 unsigned SrcReg, bool KillSrc) const {
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
97 Opc = MSP430::MOV16rr;
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
101 llvm_unreachable("Impossible reg-to-reg copy");
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
104 .addReg(SrcReg, getKillRegState(KillSrc));
107 unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
108 int *BytesRemoved) const {
109 assert(!BytesRemoved && "code size not handled");
111 MachineBasicBlock::iterator I = MBB.end();
114 while (I != MBB.begin()) {
116 if (I->isDebugValue())
118 if (I->getOpcode() != MSP430::JMP &&
119 I->getOpcode() != MSP430::JCC &&
120 I->getOpcode() != MSP430::Br &&
121 I->getOpcode() != MSP430::Bm)
123 // Remove the branch.
124 I->eraseFromParent();
132 bool MSP430InstrInfo::
133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
139 default: llvm_unreachable("Invalid branch condition!");
140 case MSP430CC::COND_E:
141 CC = MSP430CC::COND_NE;
143 case MSP430CC::COND_NE:
144 CC = MSP430CC::COND_E;
146 case MSP430CC::COND_L:
147 CC = MSP430CC::COND_GE;
149 case MSP430CC::COND_GE:
150 CC = MSP430CC::COND_L;
152 case MSP430CC::COND_HS:
153 CC = MSP430CC::COND_LO;
155 case MSP430CC::COND_LO:
156 CC = MSP430CC::COND_HS;
164 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
165 if (!MI.isTerminator())
168 // Conditional branch is a special case.
169 if (MI.isBranch() && !MI.isBarrier())
171 if (!MI.isPredicable())
173 return !isPredicated(MI);
176 bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
177 MachineBasicBlock *&TBB,
178 MachineBasicBlock *&FBB,
179 SmallVectorImpl<MachineOperand> &Cond,
180 bool AllowModify) const {
181 // Start from the bottom of the block and work up, examining the
182 // terminator instructions.
183 MachineBasicBlock::iterator I = MBB.end();
184 while (I != MBB.begin()) {
186 if (I->isDebugValue())
189 // Working from the bottom, when we see a non-terminator
190 // instruction, we're done.
191 if (!isUnpredicatedTerminator(*I))
194 // A terminator that isn't a branch can't easily be handled
199 // Cannot handle indirect branches.
200 if (I->getOpcode() == MSP430::Br ||
201 I->getOpcode() == MSP430::Bm)
204 // Handle unconditional branches.
205 if (I->getOpcode() == MSP430::JMP) {
207 TBB = I->getOperand(0).getMBB();
211 // If the block has any instructions after a JMP, delete them.
212 while (std::next(I) != MBB.end())
213 std::next(I)->eraseFromParent();
217 // Delete the JMP if it's equivalent to a fall-through.
218 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
220 I->eraseFromParent();
225 // TBB is used to indicate the unconditinal destination.
226 TBB = I->getOperand(0).getMBB();
230 // Handle conditional branches.
231 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
232 MSP430CC::CondCodes BranchCode =
233 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
234 if (BranchCode == MSP430CC::COND_INVALID)
235 return true; // Can't handle weird stuff.
237 // Working from the bottom, handle the first conditional branch.
240 TBB = I->getOperand(0).getMBB();
241 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 // Handle subsequent conditional branches. Only handle the case where all
246 // conditional branches branch to the same destination.
247 assert(Cond.size() == 1);
250 // Only handle the case where all conditional branches branch to
251 // the same destination.
252 if (TBB != I->getOperand(0).getMBB())
255 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
256 // If the conditions are the same, we can leave them alone.
257 if (OldBranchCode == BranchCode)
266 unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB,
267 MachineBasicBlock *TBB,
268 MachineBasicBlock *FBB,
269 ArrayRef<MachineOperand> Cond,
271 int *BytesAdded) const {
272 // Shouldn't be a fall through.
273 assert(TBB && "insertBranch must not be told to insert a fallthrough");
274 assert((Cond.size() == 1 || Cond.size() == 0) &&
275 "MSP430 branch conditions have one component!");
276 assert(!BytesAdded && "code size not handled");
279 // Unconditional branch?
280 assert(!FBB && "Unconditional branch with multiple successors!");
281 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
285 // Conditional branch.
287 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
291 // Two-way Conditional branch. Insert the second branch.
292 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
298 /// GetInstSize - Return the number of bytes of code the specified
299 /// instruction may be. This returns the maximum number of bytes.
301 unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
302 const MCInstrDesc &Desc = MI.getDesc();
304 switch (Desc.TSFlags & MSP430II::SizeMask) {
306 switch (Desc.getOpcode()) {
307 default: llvm_unreachable("Unknown instruction size!");
308 case TargetOpcode::CFI_INSTRUCTION:
309 case TargetOpcode::EH_LABEL:
310 case TargetOpcode::IMPLICIT_DEF:
311 case TargetOpcode::KILL:
312 case TargetOpcode::DBG_VALUE:
314 case TargetOpcode::INLINEASM: {
315 const MachineFunction *MF = MI.getParent()->getParent();
316 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
317 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
318 *MF->getTarget().getMCAsmInfo());
321 case MSP430II::SizeSpecial:
322 switch (MI.getOpcode()) {
323 default: llvm_unreachable("Unknown instruction size!");
324 case MSP430::SAR8r1c:
325 case MSP430::SAR16r1c:
328 case MSP430II::Size2Bytes:
330 case MSP430II::Size4Bytes:
332 case MSP430II::Size6Bytes: