contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.h

   1 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
  15 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
  16
  17 #include "MSP430RegisterInfo.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "MSP430GenInstrInfo.inc"
  22
  23 namespace llvm {
  24
  25 class MSP430Subtarget;
  26
  27 class MSP430InstrInfo : public MSP430GenInstrInfo {
  28   const MSP430RegisterInfo RI;
  29   virtual void anchor();
  30 public:
  31   explicit MSP430InstrInfo(MSP430Subtarget &STI);
  32
  33   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  34   /// such, whenever a client has an instance of instruction info, it should
  35   /// always be able to get register info as well (through this method).
  36   ///
  37   const TargetRegisterInfo &getRegisterInfo() const { return RI; }
  38
  39   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  40                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
  41                    bool KillSrc) const override;
  42
  43   void storeRegToStackSlot(MachineBasicBlock &MBB,
  44                            MachineBasicBlock::iterator MI,
  45                            unsigned SrcReg, bool isKill,
  46                            int FrameIndex,
  47                            const TargetRegisterClass *RC,
  48                            const TargetRegisterInfo *TRI) const override;
  49   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  50                             MachineBasicBlock::iterator MI,
  51                             unsigned DestReg, int FrameIdx,
  52                             const TargetRegisterClass *RC,
  53                             const TargetRegisterInfo *TRI) const override;
  54
  55   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
  56
  57   // Branch folding goodness
  58   bool
  59   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
  60   bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
  61   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  62                      MachineBasicBlock *&FBB,
  63                      SmallVectorImpl<MachineOperand> &Cond,
  64                      bool AllowModify) const override;
  65
  66   unsigned removeBranch(MachineBasicBlock &MBB,
  67                         int *BytesRemoved = nullptr) const override;
  68   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  69                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  70                         const DebugLoc &DL,
  71                         int *BytesAdded = nullptr) const override;
  72
  73   int64_t getFramePoppedByCallee(const MachineInstr &I) const {
  74     assert(isFrameInstr(I) && "Not a frame instruction");
  75     assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
  76     return I.getOperand(1).getImm();
  77   }
  78 };
  79
  80 }
  81
  82 #endif