contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "llvm/ADT/ArrayRef.h"
  16 #include "llvm/MC/MCContext.h"
  17 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/MC/MCRegisterInfo.h"
  22 #include "llvm/Support/Compiler.h"
  23 #include "llvm/Support/Debug.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/MathExtras.h"
  26 #include "llvm/Support/raw_ostream.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28 #include <cassert>
  29 #include <cstdint>
  30
  31 using namespace llvm;
  32
  33 #define DEBUG_TYPE "mips-disassembler"
  34
  35 typedef MCDisassembler::DecodeStatus DecodeStatus;
  36
  37 namespace {
  38
  39 class MipsDisassembler : public MCDisassembler {
  40   bool IsMicroMips;
  41   bool IsBigEndian;
  42
  43 public:
  44   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  45       : MCDisassembler(STI, Ctx),
  46         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  47         IsBigEndian(IsBigEndian) {}
  48
  49   bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
  50   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  51   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  52
  53   bool hasMips32r6() const {
  54     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  55   }
  56
  57   bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
  58
  59   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  60
  61   bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
  62
  63   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  64
  65   bool hasCOP3() const {
  66     // Only present in MIPS-I and MIPS-II
  67     return !hasMips32() && !hasMips3();
  68   }
  69
  70   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  71                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  72                               raw_ostream &VStream,
  73                               raw_ostream &CStream) const override;
  74 };
  75
  76 } // end anonymous namespace
  77
  78 // Forward declare these because the autogenerated code will reference them.
  79 // Definitions are further down.
  80 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  81                                              unsigned RegNo,
  82                                              uint64_t Address,
  83                                              const void *Decoder);
  84
  85 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  86                                                  unsigned RegNo,
  87                                                  uint64_t Address,
  88                                                  const void *Decoder);
  89
  90 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  91                                                unsigned RegNo,
  92                                                uint64_t Address,
  93                                                const void *Decoder);
  94
  95 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  96                                                    unsigned RegNo,
  97                                                    uint64_t Address,
  98                                                    const void *Decoder);
  99
 100 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
 101                                                     unsigned RegNo,
 102                                                     uint64_t Address,
 103                                                     const void *Decoder);
 104
 105 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 106                                              unsigned RegNo,
 107                                              uint64_t Address,
 108                                              const void *Decoder);
 109
 110 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 111                                            unsigned Insn,
 112                                            uint64_t Address,
 113                                            const void *Decoder);
 114
 115 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 116                                             unsigned RegNo,
 117                                             uint64_t Address,
 118                                             const void *Decoder);
 119
 120 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 121                                              unsigned RegNo,
 122                                              uint64_t Address,
 123                                              const void *Decoder);
 124
 125 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 126                                              unsigned RegNo,
 127                                              uint64_t Address,
 128                                              const void *Decoder);
 129
 130 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 131                                            unsigned RegNo,
 132                                            uint64_t Address,
 133                                            const void *Decoder);
 134
 135 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 136                                            unsigned RegNo,
 137                                            uint64_t Address,
 138                                            const void *Decoder);
 139
 140 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 141                                              uint64_t Address,
 142                                              const void *Decoder);
 143
 144 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 145                                               unsigned Insn,
 146                                               uint64_t Address,
 147                                               const void *Decoder);
 148
 149 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 150                                               unsigned RegNo,
 151                                               uint64_t Address,
 152                                               const void *Decoder);
 153
 154 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 155                                                 unsigned RegNo,
 156                                                 uint64_t Address,
 157                                                 const void *Decoder);
 158
 159 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 160                                                unsigned RegNo,
 161                                                uint64_t Address,
 162                                                const void *Decoder);
 163
 164 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 165                                                unsigned RegNo,
 166                                                uint64_t Address,
 167                                                const void *Decoder);
 168
 169 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 170                                                unsigned RegNo,
 171                                                uint64_t Address,
 172                                                const void *Decoder);
 173
 174 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 175                                                unsigned RegNo,
 176                                                uint64_t Address,
 177                                                const void *Decoder);
 178
 179 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 180                                                unsigned RegNo,
 181                                                uint64_t Address,
 182                                                const void *Decoder);
 183
 184 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 185                                                unsigned RegNo,
 186                                                uint64_t Address,
 187                                                const void *Decoder);
 188
 189 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 190                                                unsigned RegNo,
 191                                                uint64_t Address,
 192                                                const void *Decoder);
 193
 194 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 195                                             unsigned RegNo,
 196                                             uint64_t Address,
 197                                             const void *Decoder);
 198
 199 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 200                                             unsigned RegNo,
 201                                             uint64_t Address,
 202                                             const void *Decoder);
 203
 204 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 205                                        unsigned Offset,
 206                                        uint64_t Address,
 207                                        const void *Decoder);
 208
 209 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
 210                                               unsigned Offset,
 211                                               uint64_t Address,
 212                                               const void *Decoder);
 213
 214 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 215                                      unsigned Insn,
 216                                      uint64_t Address,
 217                                      const void *Decoder);
 218
 219 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 220                                          unsigned Offset,
 221                                          uint64_t Address,
 222                                          const void *Decoder);
 223
 224 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
 225                                            unsigned Offset,
 226                                            uint64_t Address,
 227                                            const void *Decoder);
 228
 229 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 235 // shifted left by 1 bit.
 236 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 237                                           unsigned Offset,
 238                                           uint64_t Address,
 239                                           const void *Decoder);
 240
 241 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 242 // shifted left by 1 bit.
 243 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 244                                            unsigned Offset,
 245                                            uint64_t Address,
 246                                            const void *Decoder);
 247
 248 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 249 // shifted left by 1 bit.
 250 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 251                                          unsigned Offset,
 252                                          uint64_t Address,
 253                                          const void *Decoder);
 254
 255 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
 256 // shifted left by 1 bit.
 257 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
 258                                            unsigned Offset,
 259                                            uint64_t Address,
 260                                            const void *Decoder);
 261
 262 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 263 // shifted left by 1 bit.
 264 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 265                                        unsigned Insn,
 266                                        uint64_t Address,
 267                                        const void *Decoder);
 268
 269 static DecodeStatus DecodeMem(MCInst &Inst,
 270                               unsigned Insn,
 271                               uint64_t Address,
 272                               const void *Decoder);
 273
 274 static DecodeStatus DecodeMemEVA(MCInst &Inst,
 275                                  unsigned Insn,
 276                                  uint64_t Address,
 277                                  const void *Decoder);
 278
 279 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
 280                                     unsigned Insn,
 281                                     uint64_t Address,
 282                                     const void *Decoder);
 283
 284 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
 285                                      unsigned Insn,
 286                                      uint64_t Address,
 287                                      const void *Decoder);
 288
 289 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 290                               unsigned Insn,
 291                               uint64_t Address,
 292                               const void *Decoder);
 293
 294 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
 295                                              unsigned Insn,
 296                                              uint64_t Address,
 297                                              const void *Decoder);
 298
 299 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 300                                     unsigned Insn,
 301                                     uint64_t Address,
 302                                     const void *Decoder);
 303
 304 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
 305                                        unsigned Insn,
 306                                        uint64_t Address,
 307                                        const void *Decoder);
 308
 309 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
 310                                     unsigned Insn,
 311                                     uint64_t Address,
 312                                     const void *Decoder);
 313
 314 static DecodeStatus DecodeSyncI(MCInst &Inst,
 315                                 unsigned Insn,
 316                                 uint64_t Address,
 317                                 const void *Decoder);
 318
 319 static DecodeStatus DecodeSynciR6(MCInst &Inst,
 320                                   unsigned Insn,
 321                                   uint64_t Address,
 322                                   const void *Decoder);
 323
 324 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 325                                     uint64_t Address, const void *Decoder);
 326
 327 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 328                                     unsigned Insn,
 329                                     uint64_t Address,
 330                                     const void *Decoder);
 331
 332 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 333                                           unsigned Insn,
 334                                           uint64_t Address,
 335                                           const void *Decoder);
 336
 337 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 338                                           unsigned Insn,
 339                                           uint64_t Address,
 340                                           const void *Decoder);
 341
 342 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 343                                                unsigned Insn,
 344                                                uint64_t Address,
 345                                                const void *Decoder);
 346
 347 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 348                                     unsigned Insn,
 349                                     uint64_t Address,
 350                                     const void *Decoder);
 351
 352 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 353                                      unsigned Insn,
 354                                      uint64_t Address,
 355                                      const void *Decoder);
 356
 357 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 358                                      unsigned Insn,
 359                                      uint64_t Address,
 360                                      const void *Decoder);
 361
 362 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 363                                uint64_t Address,
 364                                const void *Decoder);
 365
 366 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
 367                                    uint64_t Address,
 368                                    const void *Decoder);
 369
 370 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 371                                uint64_t Address,
 372                                const void *Decoder);
 373
 374 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 375                                uint64_t Address,
 376                                const void *Decoder);
 377
 378 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 379                                uint64_t Address,
 380                                const void *Decoder);
 381
 382 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
 383                                        uint64_t Address,
 384                                        const void *Decoder);
 385
 386 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 387                                        unsigned Insn,
 388                                        uint64_t Address,
 389                                        const void *Decoder);
 390
 391 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 392                                        unsigned Value,
 393                                        uint64_t Address,
 394                                        const void *Decoder);
 395
 396 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
 397                                   unsigned Value,
 398                                   uint64_t Address,
 399                                   const void *Decoder);
 400
 401 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
 402                                               unsigned Value,
 403                                               uint64_t Address,
 404                                               const void *Decoder);
 405
 406 template <unsigned Bits, int Offset, int Scale>
 407 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
 408                                                  uint64_t Address,
 409                                                  const void *Decoder);
 410
 411 template <unsigned Bits, int Offset>
 412 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
 413                                          uint64_t Address,
 414                                          const void *Decoder) {
 415   return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
 416                                                        Decoder);
 417 }
 418
 419 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
 420 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
 421                                                  uint64_t Address,
 422                                                  const void *Decoder);
 423
 424 static DecodeStatus DecodeInsSize(MCInst &Inst,
 425                                   unsigned Insn,
 426                                   uint64_t Address,
 427                                   const void *Decoder);
 428
 429 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 430                                      uint64_t Address, const void *Decoder);
 431
 432 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 433                                      uint64_t Address, const void *Decoder);
 434
 435 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 436                                   uint64_t Address, const void *Decoder);
 437
 438 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 439                                     uint64_t Address, const void *Decoder);
 440
 441 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 442                                      uint64_t Address, const void *Decoder);
 443
 444 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 445 /// handle.
 446 template <typename InsnType>
 447 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 448                                    const void *Decoder);
 449
 450 template <typename InsnType>
 451 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 452                                    const void *Decoder);
 453
 454 template <typename InsnType>
 455 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
 456                                    const void *Decoder);
 457
 458 template <typename InsnType>
 459 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 460                                    const void *Decoder);
 461
 462 template <typename InsnType>
 463 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
 464                                    const void *Decoder);
 465
 466 template <typename InsnType>
 467 static DecodeStatus
 468 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 469                       const void *Decoder);
 470
 471 template <typename InsnType>
 472 static DecodeStatus
 473 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 474                            const void *Decoder);
 475
 476 template <typename InsnType>
 477 static DecodeStatus
 478 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 479                        const void *Decoder);
 480
 481 template <typename InsnType>
 482 static DecodeStatus
 483 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 484                            const void *Decoder);
 485
 486 template <typename InsnType>
 487 static DecodeStatus
 488 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 489                            const void *Decoder);
 490
 491 template <typename InsnType>
 492 static DecodeStatus
 493 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 494                            const void *Decoder);
 495
 496 template <typename InsnType>
 497 static DecodeStatus
 498 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 499                        const void *Decoder);
 500
 501 template <typename InsnType>
 502 static DecodeStatus
 503 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 504                        const void *Decoder);
 505
 506 template <typename InsnType>
 507 static DecodeStatus
 508 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 509                       const void *Decoder);
 510
 511 template <typename InsnType>
 512 static DecodeStatus
 513 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 514                        const void *Decoder);
 515
 516 template <typename InsnType>
 517 static DecodeStatus
 518 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 519                           const void *Decoder);
 520
 521 template <typename InsnType>
 522 static DecodeStatus
 523 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 524                           const void *Decoder);
 525
 526 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 527                                          uint64_t Address,
 528                                          const void *Decoder);
 529
 530 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 531                                            uint64_t Address,
 532                                            const void *Decoder);
 533
 534 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 535                                        uint64_t Address,
 536                                        const void *Decoder);
 537
 538 namespace llvm {
 539
 540 Target &getTheMipselTarget();
 541 Target &getTheMipsTarget();
 542 Target &getTheMips64Target();
 543 Target &getTheMips64elTarget();
 544
 545 } // end namespace llvm
 546
 547 static MCDisassembler *createMipsDisassembler(
 548                        const Target &T,
 549                        const MCSubtargetInfo &STI,
 550                        MCContext &Ctx) {
 551   return new MipsDisassembler(STI, Ctx, true);
 552 }
 553
 554 static MCDisassembler *createMipselDisassembler(
 555                        const Target &T,
 556                        const MCSubtargetInfo &STI,
 557                        MCContext &Ctx) {
 558   return new MipsDisassembler(STI, Ctx, false);
 559 }
 560
 561 extern "C" void LLVMInitializeMipsDisassembler() {
 562   // Register the disassembler.
 563   TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
 564                                          createMipsDisassembler);
 565   TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
 566                                          createMipselDisassembler);
 567   TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
 568                                          createMipsDisassembler);
 569   TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
 570                                          createMipselDisassembler);
 571 }
 572
 573 #include "MipsGenDisassemblerTables.inc"
 574
 575 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 576   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 577   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 578   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 579 }
 580
 581 template <typename InsnType>
 582 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 583                                    const void *Decoder) {
 584   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 585   // The size of the n field depends on the element size
 586   // The register class also depends on this.
 587   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 588   unsigned NSize = 0;
 589   DecodeFN RegDecoder = nullptr;
 590   if ((tmp & 0x18) == 0x00) { // INSVE_B
 591     NSize = 4;
 592     RegDecoder = DecodeMSA128BRegisterClass;
 593   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 594     NSize = 3;
 595     RegDecoder = DecodeMSA128HRegisterClass;
 596   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 597     NSize = 2;
 598     RegDecoder = DecodeMSA128WRegisterClass;
 599   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 600     NSize = 1;
 601     RegDecoder = DecodeMSA128DRegisterClass;
 602   } else
 603     llvm_unreachable("Invalid encoding");
 604
 605   assert(NSize != 0 && RegDecoder != nullptr);
 606
 607   // $wd
 608   tmp = fieldFromInstruction(insn, 6, 5);
 609   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 610     return MCDisassembler::Fail;
 611   // $wd_in
 612   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 613     return MCDisassembler::Fail;
 614   // $n
 615   tmp = fieldFromInstruction(insn, 16, NSize);
 616   MI.addOperand(MCOperand::createImm(tmp));
 617   // $ws
 618   tmp = fieldFromInstruction(insn, 11, 5);
 619   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 620     return MCDisassembler::Fail;
 621   // $n2
 622   MI.addOperand(MCOperand::createImm(0));
 623
 624   return MCDisassembler::Success;
 625 }
 626
 627 template <typename InsnType>
 628 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
 629                                const void *Decoder) {
 630   InsnType Rs = fieldFromInstruction(insn, 16, 5);
 631   InsnType Imm = fieldFromInstruction(insn, 0, 16);
 632   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
 633                                        Rs)));
 634   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
 635                                        Rs)));
 636   MI.addOperand(MCOperand::createImm(Imm));
 637
 638   return MCDisassembler::Success;
 639 }
 640
 641 template <typename InsnType>
 642 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
 643                                const void *Decoder) {
 644   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 645   InsnType Imm = fieldFromInstruction(insn, 0, 16);
 646   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
 647                                        Rs)));
 648   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
 649                                        Rs)));
 650   MI.addOperand(MCOperand::createImm(Imm));
 651
 652   return MCDisassembler::Success;
 653 }
 654
 655 template <typename InsnType>
 656 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 657                                           uint64_t Address,
 658                                           const void *Decoder) {
 659   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 660   // (otherwise we would have matched the ADDI instruction from the earlier
 661   // ISA's instead).
 662   //
 663   // We have:
 664   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 665   //      BOVC if rs >= rt
 666   //      BEQZALC if rs == 0 && rt != 0
 667   //      BEQC if rs < rt && rs != 0
 668
 669   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 670   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 671   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 672   bool HasRs = false;
 673
 674   if (Rs >= Rt) {
 675     MI.setOpcode(Mips::BOVC);
 676     HasRs = true;
 677   } else if (Rs != 0 && Rs < Rt) {
 678     MI.setOpcode(Mips::BEQC);
 679     HasRs = true;
 680   } else
 681     MI.setOpcode(Mips::BEQZALC);
 682
 683   if (HasRs)
 684     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 685                                        Rs)));
 686
 687   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 688                                      Rt)));
 689   MI.addOperand(MCOperand::createImm(Imm));
 690
 691   return MCDisassembler::Success;
 692 }
 693
 694 template <typename InsnType>
 695 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
 696                                                uint64_t Address,
 697                                                const void *Decoder) {
 698   InsnType Rt = fieldFromInstruction(insn, 21, 5);
 699   InsnType Rs = fieldFromInstruction(insn, 16, 5);
 700   int64_t Imm = 0;
 701
 702   if (Rs >= Rt) {
 703     MI.setOpcode(Mips::BOVC_MMR6);
 704     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 705                                        Rt)));
 706     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 707                                        Rs)));
 708     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 709   } else if (Rs != 0 && Rs < Rt) {
 710     MI.setOpcode(Mips::BEQC_MMR6);
 711     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 712                                        Rs)));
 713     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 714                                        Rt)));
 715     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 716   } else {
 717     MI.setOpcode(Mips::BEQZALC_MMR6);
 718     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 719                                        Rt)));
 720     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 721   }
 722
 723   MI.addOperand(MCOperand::createImm(Imm));
 724
 725   return MCDisassembler::Success;
 726 }
 727
 728 template <typename InsnType>
 729 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 730                                            uint64_t Address,
 731                                            const void *Decoder) {
 732   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 733   // (otherwise we would have matched the ADDI instruction from the earlier
 734   // ISA's instead).
 735   //
 736   // We have:
 737   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 738   //      BNVC if rs >= rt
 739   //      BNEZALC if rs == 0 && rt != 0
 740   //      BNEC if rs < rt && rs != 0
 741
 742   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 743   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 744   int64_t  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 745   bool HasRs = false;
 746
 747   if (Rs >= Rt) {
 748     MI.setOpcode(Mips::BNVC);
 749     HasRs = true;
 750   } else if (Rs != 0 && Rs < Rt) {
 751     MI.setOpcode(Mips::BNEC);
 752     HasRs = true;
 753   } else
 754     MI.setOpcode(Mips::BNEZALC);
 755
 756   if (HasRs)
 757     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 758                                        Rs)));
 759
 760   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 761                                      Rt)));
 762   MI.addOperand(MCOperand::createImm(Imm));
 763
 764   return MCDisassembler::Success;
 765 }
 766
 767 template <typename InsnType>
 768 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
 769                                                uint64_t Address,
 770                                                const void *Decoder) {
 771   InsnType Rt = fieldFromInstruction(insn, 21, 5);
 772   InsnType Rs = fieldFromInstruction(insn, 16, 5);
 773   int64_t Imm = 0;
 774
 775   if (Rs >= Rt) {
 776     MI.setOpcode(Mips::BNVC_MMR6);
 777     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 778                                        Rt)));
 779     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 780                                        Rs)));
 781     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 782   } else if (Rs != 0 && Rs < Rt) {
 783     MI.setOpcode(Mips::BNEC_MMR6);
 784     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 785                                        Rs)));
 786     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 787                                        Rt)));
 788     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 789   } else {
 790     MI.setOpcode(Mips::BNEZALC_MMR6);
 791     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 792                                        Rt)));
 793     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
 794   }
 795
 796   MI.addOperand(MCOperand::createImm(Imm));
 797
 798   return MCDisassembler::Success;
 799 }
 800
 801 template <typename InsnType>
 802 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
 803                                                uint64_t Address,
 804                                                const void *Decoder) {
 805   // We have:
 806   //    0b110101 ttttt sssss iiiiiiiiiiiiiiii
 807   //      Invalid if rt == 0
 808   //      BGTZC_MMR6   if rs == 0  && rt != 0
 809   //      BLTZC_MMR6   if rs == rt && rt != 0
 810   //      BLTC_MMR6    if rs != rt && rs != 0  && rt != 0
 811
 812   InsnType Rt = fieldFromInstruction(insn, 21, 5);
 813   InsnType Rs = fieldFromInstruction(insn, 16, 5);
 814   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 815   bool HasRs = false;
 816
 817   if (Rt == 0)
 818     return MCDisassembler::Fail;
 819   else if (Rs == 0)
 820     MI.setOpcode(Mips::BGTZC_MMR6);
 821   else if (Rs == Rt)
 822     MI.setOpcode(Mips::BLTZC_MMR6);
 823   else {
 824     MI.setOpcode(Mips::BLTC_MMR6);
 825     HasRs = true;
 826   }
 827
 828   if (HasRs)
 829     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 830                                               Rs)));
 831
 832   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 833                                      Rt)));
 834
 835   MI.addOperand(MCOperand::createImm(Imm));
 836
 837   return MCDisassembler::Success;
 838 }
 839
 840 template <typename InsnType>
 841 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
 842                                                uint64_t Address,
 843                                                const void *Decoder) {
 844   // We have:
 845   //    0b111101 ttttt sssss iiiiiiiiiiiiiiii
 846   //      Invalid if rt == 0
 847   //      BLEZC_MMR6   if rs == 0  && rt != 0
 848   //      BGEZC_MMR6   if rs == rt && rt != 0
 849   //      BGEC_MMR6    if rs != rt && rs != 0  && rt != 0
 850
 851   InsnType Rt = fieldFromInstruction(insn, 21, 5);
 852   InsnType Rs = fieldFromInstruction(insn, 16, 5);
 853   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 854   bool HasRs = false;
 855
 856   if (Rt == 0)
 857     return MCDisassembler::Fail;
 858   else if (Rs == 0)
 859     MI.setOpcode(Mips::BLEZC_MMR6);
 860   else if (Rs == Rt)
 861     MI.setOpcode(Mips::BGEZC_MMR6);
 862   else {
 863     HasRs = true;
 864     MI.setOpcode(Mips::BGEC_MMR6);
 865   }
 866
 867   if (HasRs)
 868     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 869                                        Rs)));
 870
 871   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 872                                      Rt)));
 873
 874   MI.addOperand(MCOperand::createImm(Imm));
 875
 876   return MCDisassembler::Success;
 877 }
 878
 879 template <typename InsnType>
 880 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 881                                            uint64_t Address,
 882                                            const void *Decoder) {
 883   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 884   // (otherwise we would have matched the BLEZL instruction from the earlier
 885   // ISA's instead).
 886   //
 887   // We have:
 888   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 889   //      Invalid if rs == 0
 890   //      BLEZC   if rs == 0  && rt != 0
 891   //      BGEZC   if rs == rt && rt != 0
 892   //      BGEC    if rs != rt && rs != 0  && rt != 0
 893
 894   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 895   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 896   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 897   bool HasRs = false;
 898
 899   if (Rt == 0)
 900     return MCDisassembler::Fail;
 901   else if (Rs == 0)
 902     MI.setOpcode(Mips::BLEZC);
 903   else if (Rs == Rt)
 904     MI.setOpcode(Mips::BGEZC);
 905   else {
 906     HasRs = true;
 907     MI.setOpcode(Mips::BGEC);
 908   }
 909
 910   if (HasRs)
 911     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 912                                        Rs)));
 913
 914   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 915                                      Rt)));
 916
 917   MI.addOperand(MCOperand::createImm(Imm));
 918
 919   return MCDisassembler::Success;
 920 }
 921
 922 template <typename InsnType>
 923 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 924                                            uint64_t Address,
 925                                            const void *Decoder) {
 926   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 927   // (otherwise we would have matched the BGTZL instruction from the earlier
 928   // ISA's instead).
 929   //
 930   // We have:
 931   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 932   //      Invalid if rs == 0
 933   //      BGTZC   if rs == 0  && rt != 0
 934   //      BLTZC   if rs == rt && rt != 0
 935   //      BLTC    if rs != rt && rs != 0  && rt != 0
 936
 937   bool HasRs = false;
 938
 939   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 940   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 941   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 942
 943   if (Rt == 0)
 944     return MCDisassembler::Fail;
 945   else if (Rs == 0)
 946     MI.setOpcode(Mips::BGTZC);
 947   else if (Rs == Rt)
 948     MI.setOpcode(Mips::BLTZC);
 949   else {
 950     MI.setOpcode(Mips::BLTC);
 951     HasRs = true;
 952   }
 953
 954   if (HasRs)
 955     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 956                                               Rs)));
 957
 958   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 959                                      Rt)));
 960
 961   MI.addOperand(MCOperand::createImm(Imm));
 962
 963   return MCDisassembler::Success;
 964 }
 965
 966 template <typename InsnType>
 967 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 968                                           uint64_t Address,
 969                                           const void *Decoder) {
 970   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 971   // (otherwise we would have matched the BGTZ instruction from the earlier
 972   // ISA's instead).
 973   //
 974   // We have:
 975   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 976   //      BGTZ    if rt == 0
 977   //      BGTZALC if rs == 0 && rt != 0
 978   //      BLTZALC if rs != 0 && rs == rt
 979   //      BLTUC   if rs != 0 && rs != rt
 980
 981   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 982   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 983   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
 984   bool HasRs = false;
 985   bool HasRt = false;
 986
 987   if (Rt == 0) {
 988     MI.setOpcode(Mips::BGTZ);
 989     HasRs = true;
 990   } else if (Rs == 0) {
 991     MI.setOpcode(Mips::BGTZALC);
 992     HasRt = true;
 993   } else if (Rs == Rt) {
 994     MI.setOpcode(Mips::BLTZALC);
 995     HasRs = true;
 996   } else {
 997     MI.setOpcode(Mips::BLTUC);
 998     HasRs = true;
 999     HasRt = true;
1000   }
1001
1002   if (HasRs)
1003     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1004                                        Rs)));
1005
1006   if (HasRt)
1007     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1008                                        Rt)));
1009
1010   MI.addOperand(MCOperand::createImm(Imm));
1011
1012   return MCDisassembler::Success;
1013 }
1014
1015 template <typename InsnType>
1016 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1017                                            uint64_t Address,
1018                                            const void *Decoder) {
1019   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1020   // (otherwise we would have matched the BLEZL instruction from the earlier
1021   // ISA's instead).
1022   //
1023   // We have:
1024   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
1025   //      Invalid   if rs == 0
1026   //      BLEZALC   if rs == 0  && rt != 0
1027   //      BGEZALC   if rs == rt && rt != 0
1028   //      BGEUC     if rs != rt && rs != 0  && rt != 0
1029
1030   InsnType Rs = fieldFromInstruction(insn, 21, 5);
1031   InsnType Rt = fieldFromInstruction(insn, 16, 5);
1032   int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1033   bool HasRs = false;
1034
1035   if (Rt == 0)
1036     return MCDisassembler::Fail;
1037   else if (Rs == 0)
1038     MI.setOpcode(Mips::BLEZALC);
1039   else if (Rs == Rt)
1040     MI.setOpcode(Mips::BGEZALC);
1041   else {
1042     HasRs = true;
1043     MI.setOpcode(Mips::BGEUC);
1044   }
1045
1046   if (HasRs)
1047     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1048                                        Rs)));
1049   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1050                                      Rt)));
1051
1052   MI.addOperand(MCOperand::createImm(Imm));
1053
1054   return MCDisassembler::Success;
1055 }
1056
1057 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1058 /// according to the given endianness.
1059 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1060                                       uint64_t &Size, uint32_t &Insn,
1061                                       bool IsBigEndian) {
1062   // We want to read exactly 2 Bytes of data.
1063   if (Bytes.size() < 2) {
1064     Size = 0;
1065     return MCDisassembler::Fail;
1066   }
1067
1068   if (IsBigEndian) {
1069     Insn = (Bytes[0] << 8) | Bytes[1];
1070   } else {
1071     Insn = (Bytes[1] << 8) | Bytes[0];
1072   }
1073
1074   return MCDisassembler::Success;
1075 }
1076
1077 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1078 /// according to the given endianness.
1079 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1080                                       uint64_t &Size, uint32_t &Insn,
1081                                       bool IsBigEndian, bool IsMicroMips) {
1082   // We want to read exactly 4 Bytes of data.
1083   if (Bytes.size() < 4) {
1084     Size = 0;
1085     return MCDisassembler::Fail;
1086   }
1087
1088   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1089   // always precede the low 16 bits in the instruction stream (that is, they
1090   // are placed at lower addresses in the instruction stream).
1091   //
1092   // microMIPS byte ordering:
1093   //   Big-endian:    0 | 1 | 2 | 3
1094   //   Little-endian: 1 | 0 | 3 | 2
1095
1096   if (IsBigEndian) {
1097     // Encoded as a big-endian 32-bit word in the stream.
1098     Insn =
1099         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1100   } else {
1101     if (IsMicroMips) {
1102       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1103              (Bytes[1] << 24);
1104     } else {
1105       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1106              (Bytes[3] << 24);
1107     }
1108   }
1109
1110   return MCDisassembler::Success;
1111 }
1112
1113 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1114                                               ArrayRef<uint8_t> Bytes,
1115                                               uint64_t Address,
1116                                               raw_ostream &VStream,
1117                                               raw_ostream &CStream) const {
1118   uint32_t Insn;
1119   DecodeStatus Result;
1120   Size = 0;
1121
1122   if (IsMicroMips) {
1123     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1124     if (Result == MCDisassembler::Fail)
1125       return MCDisassembler::Fail;
1126
1127     if (hasMips32r6()) {
1128       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1129       // Calling the auto-generated decoder function for microMIPS32R6
1130       // (and microMIPS64R6) 16-bit instructions.
1131       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1132                                  Address, this, STI);
1133       if (Result != MCDisassembler::Fail) {
1134         Size = 2;
1135         return Result;
1136       }
1137     }
1138
1139     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1140     // Calling the auto-generated decoder function for microMIPS 16-bit
1141     // instructions.
1142     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1143                                this, STI);
1144     if (Result != MCDisassembler::Fail) {
1145       Size = 2;
1146       return Result;
1147     }
1148
1149     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1150     if (Result == MCDisassembler::Fail)
1151       return MCDisassembler::Fail;
1152
1153     if (hasMips32r6()) {
1154       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1155       // Calling the auto-generated decoder function.
1156       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1157                                  this, STI);
1158       if (Result != MCDisassembler::Fail) {
1159         Size = 4;
1160         return Result;
1161       }
1162     }
1163
1164     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1165     // Calling the auto-generated decoder function.
1166     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1167                                this, STI);
1168     if (Result != MCDisassembler::Fail) {
1169       Size = 4;
1170       return Result;
1171     }
1172
1173     if (hasMips32r6() && isFP64()) {
1174       DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
1175       Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
1176                                  Address, this, STI);
1177       if (Result != MCDisassembler::Fail) {
1178         Size = 4;
1179         return Result;
1180       }
1181     }
1182
1183     // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1184     // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1185     // could form a valid instruction. The two bytes we rejected as an
1186     // instruction could have actually beeen an inline constant pool that is
1187     // unconditionally branched over.
1188     Size = 2;
1189     return MCDisassembler::Fail;
1190   }
1191
1192   // Attempt to read the instruction so that we can attempt to decode it. If
1193   // the buffer is not 4 bytes long, let the higher level logic figure out
1194   // what to do with a size of zero and MCDisassembler::Fail.
1195   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1196   if (Result == MCDisassembler::Fail)
1197     return MCDisassembler::Fail;
1198
1199   // The only instruction size for standard encoded MIPS.
1200   Size = 4;
1201
1202   if (hasCOP3()) {
1203     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1204     Result =
1205         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1206     if (Result != MCDisassembler::Fail)
1207       return Result;
1208   }
1209
1210   if (hasMips32r6() && isGP64()) {
1211     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1212     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1213                                Address, this, STI);
1214     if (Result != MCDisassembler::Fail)
1215       return Result;
1216   }
1217
1218   if (hasMips32r6() && isPTR64()) {
1219     DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1220     Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1221                                Address, this, STI);
1222     if (Result != MCDisassembler::Fail)
1223       return Result;
1224   }
1225
1226   if (hasMips32r6()) {
1227     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1228     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1229                                Address, this, STI);
1230     if (Result != MCDisassembler::Fail)
1231       return Result;
1232   }
1233
1234   if (hasMips2() && isPTR64()) {
1235     DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1236     Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1237                                Address, this, STI);
1238     if (Result != MCDisassembler::Fail)
1239       return Result;
1240   }
1241
1242   if (hasCnMips()) {
1243     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1244     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1245                                Address, this, STI);
1246     if (Result != MCDisassembler::Fail)
1247       return Result;
1248   }
1249
1250   if (isGP64()) {
1251     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1252     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1253                                Address, this, STI);
1254     if (Result != MCDisassembler::Fail)
1255       return Result;
1256   }
1257
1258   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1259   // Calling the auto-generated decoder function.
1260   Result =
1261       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1262   if (Result != MCDisassembler::Fail)
1263     return Result;
1264
1265   return MCDisassembler::Fail;
1266 }
1267
1268 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
1269                                                  unsigned RegNo,
1270                                                  uint64_t Address,
1271                                                  const void *Decoder) {
1272   return MCDisassembler::Fail;
1273 }
1274
1275 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1276                                              unsigned RegNo,
1277                                              uint64_t Address,
1278                                              const void *Decoder) {
1279   if (RegNo > 31)
1280     return MCDisassembler::Fail;
1281
1282   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1283   Inst.addOperand(MCOperand::createReg(Reg));
1284   return MCDisassembler::Success;
1285 }
1286
1287 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1288                                                unsigned RegNo,
1289                                                uint64_t Address,
1290                                                const void *Decoder) {
1291   if (RegNo > 7)
1292     return MCDisassembler::Fail;
1293   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1294   Inst.addOperand(MCOperand::createReg(Reg));
1295   return MCDisassembler::Success;
1296 }
1297
1298 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1299                                                    unsigned RegNo,
1300                                                    uint64_t Address,
1301                                                    const void *Decoder) {
1302   if (RegNo > 7)
1303     return MCDisassembler::Fail;
1304   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1305   Inst.addOperand(MCOperand::createReg(Reg));
1306   return MCDisassembler::Success;
1307 }
1308
1309 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1310                                                     unsigned RegNo,
1311                                                     uint64_t Address,
1312                                                     const void *Decoder) {
1313   if (RegNo > 7)
1314     return MCDisassembler::Fail;
1315   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1316   Inst.addOperand(MCOperand::createReg(Reg));
1317   return MCDisassembler::Success;
1318 }
1319
1320 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1321                                              unsigned RegNo,
1322                                              uint64_t Address,
1323                                              const void *Decoder) {
1324   if (RegNo > 31)
1325     return MCDisassembler::Fail;
1326   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1327   Inst.addOperand(MCOperand::createReg(Reg));
1328   return MCDisassembler::Success;
1329 }
1330
1331 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1332                                            unsigned RegNo,
1333                                            uint64_t Address,
1334                                            const void *Decoder) {
1335   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1336     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1337
1338   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1339 }
1340
1341 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1342                                             unsigned RegNo,
1343                                             uint64_t Address,
1344                                             const void *Decoder) {
1345   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1346 }
1347
1348 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1349                                              unsigned RegNo,
1350                                              uint64_t Address,
1351                                              const void *Decoder) {
1352   if (RegNo > 31)
1353     return MCDisassembler::Fail;
1354
1355   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1356   Inst.addOperand(MCOperand::createReg(Reg));
1357   return MCDisassembler::Success;
1358 }
1359
1360 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1361                                              unsigned RegNo,
1362                                              uint64_t Address,
1363                                              const void *Decoder) {
1364   if (RegNo > 31)
1365     return MCDisassembler::Fail;
1366
1367   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1368   Inst.addOperand(MCOperand::createReg(Reg));
1369   return MCDisassembler::Success;
1370 }
1371
1372 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1373                                            unsigned RegNo,
1374                                            uint64_t Address,
1375                                            const void *Decoder) {
1376   if (RegNo > 31)
1377     return MCDisassembler::Fail;
1378   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1379   Inst.addOperand(MCOperand::createReg(Reg));
1380   return MCDisassembler::Success;
1381 }
1382
1383 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1384                                            unsigned RegNo,
1385                                            uint64_t Address,
1386                                            const void *Decoder) {
1387   if (RegNo > 7)
1388     return MCDisassembler::Fail;
1389   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1390   Inst.addOperand(MCOperand::createReg(Reg));
1391   return MCDisassembler::Success;
1392 }
1393
1394 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1395                                              uint64_t Address,
1396                                              const void *Decoder) {
1397   if (RegNo > 31)
1398     return MCDisassembler::Fail;
1399
1400   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1401   Inst.addOperand(MCOperand::createReg(Reg));
1402   return MCDisassembler::Success;
1403 }
1404
1405 static DecodeStatus DecodeMem(MCInst &Inst,
1406                               unsigned Insn,
1407                               uint64_t Address,
1408                               const void *Decoder) {
1409   int Offset = SignExtend32<16>(Insn & 0xffff);
1410   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1411   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1412
1413   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1414   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1415
1416   if (Inst.getOpcode() == Mips::SC ||
1417       Inst.getOpcode() == Mips::SCD)
1418     Inst.addOperand(MCOperand::createReg(Reg));
1419
1420   Inst.addOperand(MCOperand::createReg(Reg));
1421   Inst.addOperand(MCOperand::createReg(Base));
1422   Inst.addOperand(MCOperand::createImm(Offset));
1423
1424   return MCDisassembler::Success;
1425 }
1426
1427 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1428                                  unsigned Insn,
1429                                  uint64_t Address,
1430                                  const void *Decoder) {
1431   int Offset = SignExtend32<9>(Insn >> 7);
1432   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1433   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1434
1435   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1436   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1437
1438    if (Inst.getOpcode() == Mips::SCE)
1439      Inst.addOperand(MCOperand::createReg(Reg));
1440
1441   Inst.addOperand(MCOperand::createReg(Reg));
1442   Inst.addOperand(MCOperand::createReg(Base));
1443   Inst.addOperand(MCOperand::createImm(Offset));
1444
1445   return MCDisassembler::Success;
1446 }
1447
1448 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
1449                                     unsigned Insn,
1450                                     uint64_t Address,
1451                                     const void *Decoder) {
1452   int Offset = SignExtend32<9>(Insn & 0x1ff);
1453   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1454   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1455
1456   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1457   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1458
1459   Inst.addOperand(MCOperand::createReg(Reg));
1460   Inst.addOperand(MCOperand::createReg(Base));
1461   Inst.addOperand(MCOperand::createImm(Offset));
1462
1463   return MCDisassembler::Success;
1464 }
1465
1466 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1467                                      unsigned Insn,
1468                                      uint64_t Address,
1469                                      const void *Decoder) {
1470   int Offset = SignExtend32<16>(Insn & 0xffff);
1471   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1472   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1473
1474   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1475   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1476
1477   Inst.addOperand(MCOperand::createReg(Reg));
1478   Inst.addOperand(MCOperand::createReg(Base));
1479   Inst.addOperand(MCOperand::createImm(Offset));
1480
1481   return MCDisassembler::Success;
1482 }
1483
1484 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1485                               unsigned Insn,
1486                               uint64_t Address,
1487                               const void *Decoder) {
1488   int Offset = SignExtend32<16>(Insn & 0xffff);
1489   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1490   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1491
1492   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1493
1494   Inst.addOperand(MCOperand::createReg(Base));
1495   Inst.addOperand(MCOperand::createImm(Offset));
1496   Inst.addOperand(MCOperand::createImm(Hint));
1497
1498   return MCDisassembler::Success;
1499 }
1500
1501 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1502                                     unsigned Insn,
1503                                     uint64_t Address,
1504                                     const void *Decoder) {
1505   int Offset = SignExtend32<12>(Insn & 0xfff);
1506   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1507   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1508
1509   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1510
1511   Inst.addOperand(MCOperand::createReg(Base));
1512   Inst.addOperand(MCOperand::createImm(Offset));
1513   Inst.addOperand(MCOperand::createImm(Hint));
1514
1515   return MCDisassembler::Success;
1516 }
1517
1518 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1519                                     unsigned Insn,
1520                                     uint64_t Address,
1521                                     const void *Decoder) {
1522   int Offset = SignExtend32<9>(Insn & 0x1ff);
1523   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1524   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1525
1526   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1527
1528   Inst.addOperand(MCOperand::createReg(Base));
1529   Inst.addOperand(MCOperand::createImm(Offset));
1530   Inst.addOperand(MCOperand::createImm(Hint));
1531
1532   return MCDisassembler::Success;
1533 }
1534
1535 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1536                                              unsigned Insn,
1537                                              uint64_t Address,
1538                                              const void *Decoder) {
1539   int Offset = SignExtend32<9>(Insn >> 7);
1540   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1541   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1542
1543   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1544
1545   Inst.addOperand(MCOperand::createReg(Base));
1546   Inst.addOperand(MCOperand::createImm(Offset));
1547   Inst.addOperand(MCOperand::createImm(Hint));
1548
1549   return MCDisassembler::Success;
1550 }
1551
1552 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1553                                        unsigned Insn,
1554                                        uint64_t Address,
1555                                        const void *Decoder) {
1556   int Offset = SignExtend32<9>(Insn & 0x1ff);
1557   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1558   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1559
1560   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1561   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1562
1563   Inst.addOperand(MCOperand::createReg(Reg));
1564   Inst.addOperand(MCOperand::createReg(Base));
1565   Inst.addOperand(MCOperand::createImm(Offset));
1566
1567   return MCDisassembler::Success;
1568 }
1569
1570 static DecodeStatus DecodeSyncI(MCInst &Inst,
1571                               unsigned Insn,
1572                               uint64_t Address,
1573                               const void *Decoder) {
1574   int Offset = SignExtend32<16>(Insn & 0xffff);
1575   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1576
1577   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1578
1579   Inst.addOperand(MCOperand::createReg(Base));
1580   Inst.addOperand(MCOperand::createImm(Offset));
1581
1582   return MCDisassembler::Success;
1583 }
1584
1585 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1586                                   unsigned Insn,
1587                                   uint64_t Address,
1588                                   const void *Decoder) {
1589   int Immediate = SignExtend32<16>(Insn & 0xffff);
1590   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1591
1592   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1593
1594   Inst.addOperand(MCOperand::createReg(Base));
1595   Inst.addOperand(MCOperand::createImm(Immediate));
1596
1597   return MCDisassembler::Success;
1598 }
1599
1600 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1601                                     uint64_t Address, const void *Decoder) {
1602   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1603   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1604   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1605
1606   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1607   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1608
1609   Inst.addOperand(MCOperand::createReg(Reg));
1610   Inst.addOperand(MCOperand::createReg(Base));
1611
1612   // The immediate field of an LD/ST instruction is scaled which means it must
1613   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1614   // data format.
1615   // .b - 1 byte
1616   // .h - 2 bytes
1617   // .w - 4 bytes
1618   // .d - 8 bytes
1619   switch(Inst.getOpcode())
1620   {
1621   default:
1622     assert(false && "Unexpected instruction");
1623     return MCDisassembler::Fail;
1624     break;
1625   case Mips::LD_B:
1626   case Mips::ST_B:
1627     Inst.addOperand(MCOperand::createImm(Offset));
1628     break;
1629   case Mips::LD_H:
1630   case Mips::ST_H:
1631     Inst.addOperand(MCOperand::createImm(Offset * 2));
1632     break;
1633   case Mips::LD_W:
1634   case Mips::ST_W:
1635     Inst.addOperand(MCOperand::createImm(Offset * 4));
1636     break;
1637   case Mips::LD_D:
1638   case Mips::ST_D:
1639     Inst.addOperand(MCOperand::createImm(Offset * 8));
1640     break;
1641   }
1642
1643   return MCDisassembler::Success;
1644 }
1645
1646 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1647                                     unsigned Insn,
1648                                     uint64_t Address,
1649                                     const void *Decoder) {
1650   unsigned Offset = Insn & 0xf;
1651   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1652   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1653
1654   switch (Inst.getOpcode()) {
1655     case Mips::LBU16_MM:
1656     case Mips::LHU16_MM:
1657     case Mips::LW16_MM:
1658       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1659             == MCDisassembler::Fail)
1660         return MCDisassembler::Fail;
1661       break;
1662     case Mips::SB16_MM:
1663     case Mips::SB16_MMR6:
1664     case Mips::SH16_MM:
1665     case Mips::SH16_MMR6:
1666     case Mips::SW16_MM:
1667     case Mips::SW16_MMR6:
1668       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1669             == MCDisassembler::Fail)
1670         return MCDisassembler::Fail;
1671       break;
1672   }
1673
1674   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1675         == MCDisassembler::Fail)
1676     return MCDisassembler::Fail;
1677
1678   switch (Inst.getOpcode()) {
1679     case Mips::LBU16_MM:
1680       if (Offset == 0xf)
1681         Inst.addOperand(MCOperand::createImm(-1));
1682       else
1683         Inst.addOperand(MCOperand::createImm(Offset));
1684       break;
1685     case Mips::SB16_MM:
1686     case Mips::SB16_MMR6:
1687       Inst.addOperand(MCOperand::createImm(Offset));
1688       break;
1689     case Mips::LHU16_MM:
1690     case Mips::SH16_MM:
1691     case Mips::SH16_MMR6:
1692       Inst.addOperand(MCOperand::createImm(Offset << 1));
1693       break;
1694     case Mips::LW16_MM:
1695     case Mips::SW16_MM:
1696     case Mips::SW16_MMR6:
1697       Inst.addOperand(MCOperand::createImm(Offset << 2));
1698       break;
1699   }
1700
1701   return MCDisassembler::Success;
1702 }
1703
1704 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1705                                           unsigned Insn,
1706                                           uint64_t Address,
1707                                           const void *Decoder) {
1708   unsigned Offset = Insn & 0x1F;
1709   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1710
1711   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1712
1713   Inst.addOperand(MCOperand::createReg(Reg));
1714   Inst.addOperand(MCOperand::createReg(Mips::SP));
1715   Inst.addOperand(MCOperand::createImm(Offset << 2));
1716
1717   return MCDisassembler::Success;
1718 }
1719
1720 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1721                                           unsigned Insn,
1722                                           uint64_t Address,
1723                                           const void *Decoder) {
1724   unsigned Offset = Insn & 0x7F;
1725   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1726
1727   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1728
1729   Inst.addOperand(MCOperand::createReg(Reg));
1730   Inst.addOperand(MCOperand::createReg(Mips::GP));
1731   Inst.addOperand(MCOperand::createImm(Offset << 2));
1732
1733   return MCDisassembler::Success;
1734 }
1735
1736 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1737                                                unsigned Insn,
1738                                                uint64_t Address,
1739                                                const void *Decoder) {
1740   int Offset;
1741   switch (Inst.getOpcode()) {
1742   case Mips::LWM16_MMR6:
1743   case Mips::SWM16_MMR6:
1744     Offset = fieldFromInstruction(Insn, 4, 4);
1745     break;
1746   default:
1747     Offset = SignExtend32<4>(Insn & 0xf);
1748     break;
1749   }
1750
1751   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1752       == MCDisassembler::Fail)
1753     return MCDisassembler::Fail;
1754
1755   Inst.addOperand(MCOperand::createReg(Mips::SP));
1756   Inst.addOperand(MCOperand::createImm(Offset << 2));
1757
1758   return MCDisassembler::Success;
1759 }
1760
1761 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1762                                     unsigned Insn,
1763                                     uint64_t Address,
1764                                     const void *Decoder) {
1765   int Offset = SignExtend32<9>(Insn & 0x1ff);
1766   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1767   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1768
1769   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1770   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1771
1772   if (Inst.getOpcode() == Mips::SCE_MM)
1773     Inst.addOperand(MCOperand::createReg(Reg));
1774
1775   Inst.addOperand(MCOperand::createReg(Reg));
1776   Inst.addOperand(MCOperand::createReg(Base));
1777   Inst.addOperand(MCOperand::createImm(Offset));
1778
1779   return MCDisassembler::Success;
1780 }
1781
1782 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1783                                      unsigned Insn,
1784                                      uint64_t Address,
1785                                      const void *Decoder) {
1786   int Offset = SignExtend32<12>(Insn & 0x0fff);
1787   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1788   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1789
1790   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1791   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1792
1793   switch (Inst.getOpcode()) {
1794   case Mips::SWM32_MM:
1795   case Mips::LWM32_MM:
1796     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1797         == MCDisassembler::Fail)
1798       return MCDisassembler::Fail;
1799     Inst.addOperand(MCOperand::createReg(Base));
1800     Inst.addOperand(MCOperand::createImm(Offset));
1801     break;
1802   case Mips::SC_MM:
1803     Inst.addOperand(MCOperand::createReg(Reg));
1804     LLVM_FALLTHROUGH;
1805   default:
1806     Inst.addOperand(MCOperand::createReg(Reg));
1807     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
1808         Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
1809       Inst.addOperand(MCOperand::createReg(Reg+1));
1810
1811     Inst.addOperand(MCOperand::createReg(Base));
1812     Inst.addOperand(MCOperand::createImm(Offset));
1813   }
1814
1815   return MCDisassembler::Success;
1816 }
1817
1818 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1819                                      unsigned Insn,
1820                                      uint64_t Address,
1821                                      const void *Decoder) {
1822   int Offset = SignExtend32<16>(Insn & 0xffff);
1823   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1824   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1825
1826   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1827   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1828
1829   Inst.addOperand(MCOperand::createReg(Reg));
1830   Inst.addOperand(MCOperand::createReg(Base));
1831   Inst.addOperand(MCOperand::createImm(Offset));
1832
1833   return MCDisassembler::Success;
1834 }
1835
1836 static DecodeStatus DecodeFMem(MCInst &Inst,
1837                                unsigned Insn,
1838                                uint64_t Address,
1839                                const void *Decoder) {
1840   int Offset = SignExtend32<16>(Insn & 0xffff);
1841   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1842   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1843
1844   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1845   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1846
1847   Inst.addOperand(MCOperand::createReg(Reg));
1848   Inst.addOperand(MCOperand::createReg(Base));
1849   Inst.addOperand(MCOperand::createImm(Offset));
1850
1851   return MCDisassembler::Success;
1852 }
1853
1854 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1855                                    uint64_t Address, const void *Decoder) {
1856   // This function is the same as DecodeFMem but with the Reg and Base fields
1857   // swapped according to microMIPS spec.
1858   int Offset = SignExtend32<16>(Insn & 0xffff);
1859   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1860   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1861
1862   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1863   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1864
1865   Inst.addOperand(MCOperand::createReg(Reg));
1866   Inst.addOperand(MCOperand::createReg(Base));
1867   Inst.addOperand(MCOperand::createImm(Offset));
1868
1869   return MCDisassembler::Success;
1870 }
1871
1872 static DecodeStatus DecodeFMem2(MCInst &Inst,
1873                                unsigned Insn,
1874                                uint64_t Address,
1875                                const void *Decoder) {
1876   int Offset = SignExtend32<16>(Insn & 0xffff);
1877   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1878   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1879
1880   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1881   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1882
1883   Inst.addOperand(MCOperand::createReg(Reg));
1884   Inst.addOperand(MCOperand::createReg(Base));
1885   Inst.addOperand(MCOperand::createImm(Offset));
1886
1887   return MCDisassembler::Success;
1888 }
1889
1890 static DecodeStatus DecodeFMem3(MCInst &Inst,
1891                                unsigned Insn,
1892                                uint64_t Address,
1893                                const void *Decoder) {
1894   int Offset = SignExtend32<16>(Insn & 0xffff);
1895   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1896   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1897
1898   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1899   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1900
1901   Inst.addOperand(MCOperand::createReg(Reg));
1902   Inst.addOperand(MCOperand::createReg(Base));
1903   Inst.addOperand(MCOperand::createImm(Offset));
1904
1905   return MCDisassembler::Success;
1906 }
1907
1908 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1909                                     unsigned Insn,
1910                                     uint64_t Address,
1911                                     const void *Decoder) {
1912   int Offset = SignExtend32<11>(Insn & 0x07ff);
1913   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1914   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1915
1916   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1917   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1918
1919   Inst.addOperand(MCOperand::createReg(Reg));
1920   Inst.addOperand(MCOperand::createReg(Base));
1921   Inst.addOperand(MCOperand::createImm(Offset));
1922
1923   return MCDisassembler::Success;
1924 }
1925
1926 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1927                                        uint64_t Address, const void *Decoder) {
1928   int Offset = SignExtend32<11>(Insn & 0x07ff);
1929   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1930   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1931
1932   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1933   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1934
1935   Inst.addOperand(MCOperand::createReg(Reg));
1936   Inst.addOperand(MCOperand::createReg(Base));
1937   Inst.addOperand(MCOperand::createImm(Offset));
1938
1939   return MCDisassembler::Success;
1940 }
1941
1942 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1943                                        unsigned Insn,
1944                                        uint64_t Address,
1945                                        const void *Decoder) {
1946   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1947   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1948   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1949
1950   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1951   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1952
1953   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1954     Inst.addOperand(MCOperand::createReg(Rt));
1955   }
1956
1957   Inst.addOperand(MCOperand::createReg(Rt));
1958   Inst.addOperand(MCOperand::createReg(Base));
1959   Inst.addOperand(MCOperand::createImm(Offset));
1960
1961   return MCDisassembler::Success;
1962 }
1963
1964 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1965                                               unsigned RegNo,
1966                                               uint64_t Address,
1967                                               const void *Decoder) {
1968   // Currently only hardware register 29 is supported.
1969   if (RegNo != 29)
1970     return  MCDisassembler::Fail;
1971   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1972   return MCDisassembler::Success;
1973 }
1974
1975 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1976                                               unsigned RegNo,
1977                                               uint64_t Address,
1978                                               const void *Decoder) {
1979   if (RegNo > 30 || RegNo %2)
1980     return MCDisassembler::Fail;
1981
1982   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1983   Inst.addOperand(MCOperand::createReg(Reg));
1984   return MCDisassembler::Success;
1985 }
1986
1987 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1988                                                 unsigned RegNo,
1989                                                 uint64_t Address,
1990                                                 const void *Decoder) {
1991   if (RegNo >= 4)
1992     return MCDisassembler::Fail;
1993
1994   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1995   Inst.addOperand(MCOperand::createReg(Reg));
1996   return MCDisassembler::Success;
1997 }
1998
1999 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
2000                                                unsigned RegNo,
2001                                                uint64_t Address,
2002                                                const void *Decoder) {
2003   if (RegNo >= 4)
2004     return MCDisassembler::Fail;
2005
2006   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2007   Inst.addOperand(MCOperand::createReg(Reg));
2008   return MCDisassembler::Success;
2009 }
2010
2011 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
2012                                                unsigned RegNo,
2013                                                uint64_t Address,
2014                                                const void *Decoder) {
2015   if (RegNo >= 4)
2016     return MCDisassembler::Fail;
2017
2018   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2019   Inst.addOperand(MCOperand::createReg(Reg));
2020   return MCDisassembler::Success;
2021 }
2022
2023 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
2024                                                unsigned RegNo,
2025                                                uint64_t Address,
2026                                                const void *Decoder) {
2027   if (RegNo > 31)
2028     return MCDisassembler::Fail;
2029
2030   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2031   Inst.addOperand(MCOperand::createReg(Reg));
2032   return MCDisassembler::Success;
2033 }
2034
2035 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
2036                                                unsigned RegNo,
2037                                                uint64_t Address,
2038                                                const void *Decoder) {
2039   if (RegNo > 31)
2040     return MCDisassembler::Fail;
2041
2042   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2043   Inst.addOperand(MCOperand::createReg(Reg));
2044   return MCDisassembler::Success;
2045 }
2046
2047 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
2048                                                unsigned RegNo,
2049                                                uint64_t Address,
2050                                                const void *Decoder) {
2051   if (RegNo > 31)
2052     return MCDisassembler::Fail;
2053
2054   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2055   Inst.addOperand(MCOperand::createReg(Reg));
2056   return MCDisassembler::Success;
2057 }
2058
2059 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
2060                                                unsigned RegNo,
2061                                                uint64_t Address,
2062                                                const void *Decoder) {
2063   if (RegNo > 31)
2064     return MCDisassembler::Fail;
2065
2066   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2067   Inst.addOperand(MCOperand::createReg(Reg));
2068   return MCDisassembler::Success;
2069 }
2070
2071 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
2072                                                unsigned RegNo,
2073                                                uint64_t Address,
2074                                                const void *Decoder) {
2075   if (RegNo > 7)
2076     return MCDisassembler::Fail;
2077
2078   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2079   Inst.addOperand(MCOperand::createReg(Reg));
2080   return MCDisassembler::Success;
2081 }
2082
2083 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
2084                                             unsigned RegNo,
2085                                             uint64_t Address,
2086                                             const void *Decoder) {
2087   if (RegNo > 31)
2088     return MCDisassembler::Fail;
2089
2090   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2091   Inst.addOperand(MCOperand::createReg(Reg));
2092   return MCDisassembler::Success;
2093 }
2094
2095 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
2096                                             unsigned RegNo,
2097                                             uint64_t Address,
2098                                             const void *Decoder) {
2099   if (RegNo > 31)
2100     return MCDisassembler::Fail;
2101
2102   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2103   Inst.addOperand(MCOperand::createReg(Reg));
2104   return MCDisassembler::Success;
2105 }
2106
2107 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
2108                                        unsigned Offset,
2109                                        uint64_t Address,
2110                                        const void *Decoder) {
2111   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2112   Inst.addOperand(MCOperand::createImm(BranchOffset));
2113   return MCDisassembler::Success;
2114 }
2115
2116 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
2117                                               unsigned Offset,
2118                                               uint64_t Address,
2119                                               const void *Decoder) {
2120   int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2121   Inst.addOperand(MCOperand::createImm(BranchOffset));
2122   return MCDisassembler::Success;
2123 }
2124
2125 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
2126                                      unsigned Insn,
2127                                      uint64_t Address,
2128                                      const void *Decoder) {
2129   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2130   Inst.addOperand(MCOperand::createImm(JumpOffset));
2131   return MCDisassembler::Success;
2132 }
2133
2134 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
2135                                          unsigned Offset,
2136                                          uint64_t Address,
2137                                          const void *Decoder) {
2138   int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2139
2140   Inst.addOperand(MCOperand::createImm(BranchOffset));
2141   return MCDisassembler::Success;
2142 }
2143
2144 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
2145                                            unsigned Offset,
2146                                            uint64_t Address,
2147                                            const void *Decoder) {
2148   int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2149
2150   Inst.addOperand(MCOperand::createImm(BranchOffset));
2151   return MCDisassembler::Success;
2152 }
2153
2154 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
2155                                          unsigned Offset,
2156                                          uint64_t Address,
2157                                          const void *Decoder) {
2158   int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2159
2160   Inst.addOperand(MCOperand::createImm(BranchOffset));
2161   return MCDisassembler::Success;
2162 }
2163
2164 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
2165                                           unsigned Offset,
2166                                           uint64_t Address,
2167                                           const void *Decoder) {
2168   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
2169   Inst.addOperand(MCOperand::createImm(BranchOffset));
2170   return MCDisassembler::Success;
2171 }
2172
2173 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
2174                                            unsigned Offset,
2175                                            uint64_t Address,
2176                                            const void *Decoder) {
2177   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
2178   Inst.addOperand(MCOperand::createImm(BranchOffset));
2179   return MCDisassembler::Success;
2180 }
2181
2182 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
2183                                          unsigned Offset,
2184                                          uint64_t Address,
2185                                          const void *Decoder) {
2186   int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2187   Inst.addOperand(MCOperand::createImm(BranchOffset));
2188   return MCDisassembler::Success;
2189 }
2190
2191 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
2192   unsigned Offset,
2193   uint64_t Address,
2194   const void *Decoder) {
2195   int32_t BranchOffset = SignExtend32<26>(Offset) << 1;
2196
2197   Inst.addOperand(MCOperand::createImm(BranchOffset));
2198   return MCDisassembler::Success;
2199 }
2200
2201 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
2202                                        unsigned Insn,
2203                                        uint64_t Address,
2204                                        const void *Decoder) {
2205   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2206   Inst.addOperand(MCOperand::createImm(JumpOffset));
2207   return MCDisassembler::Success;
2208 }
2209
2210 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
2211                                        unsigned Value,
2212                                        uint64_t Address,
2213                                        const void *Decoder) {
2214   if (Value == 0)
2215     Inst.addOperand(MCOperand::createImm(1));
2216   else if (Value == 0x7)
2217     Inst.addOperand(MCOperand::createImm(-1));
2218   else
2219     Inst.addOperand(MCOperand::createImm(Value << 2));
2220   return MCDisassembler::Success;
2221 }
2222
2223 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
2224                                   unsigned Value,
2225                                   uint64_t Address,
2226                                   const void *Decoder) {
2227   if (Value == 0x7F)
2228     Inst.addOperand(MCOperand::createImm(-1));
2229   else
2230     Inst.addOperand(MCOperand::createImm(Value));
2231   return MCDisassembler::Success;
2232 }
2233
2234 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
2235                                               unsigned Value,
2236                                               uint64_t Address,
2237                                               const void *Decoder) {
2238   Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2239   return MCDisassembler::Success;
2240 }
2241
2242 template <unsigned Bits, int Offset, int Scale>
2243 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2244                                                  uint64_t Address,
2245                                                  const void *Decoder) {
2246   Value &= ((1 << Bits) - 1);
2247   Value *= Scale;
2248   Inst.addOperand(MCOperand::createImm(Value + Offset));
2249   return MCDisassembler::Success;
2250 }
2251
2252 template <unsigned Bits, int Offset, int ScaleBy>
2253 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2254                                                  uint64_t Address,
2255                                                  const void *Decoder) {
2256   int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2257   Inst.addOperand(MCOperand::createImm(Imm + Offset));
2258   return MCDisassembler::Success;
2259 }
2260
2261 static DecodeStatus DecodeInsSize(MCInst &Inst,
2262                                   unsigned Insn,
2263                                   uint64_t Address,
2264                                   const void *Decoder) {
2265   // First we need to grab the pos(lsb) from MCInst.
2266   int Pos = Inst.getOperand(2).getImm();
2267   if (Inst.getOpcode() == Mips::DINSU)
2268     Pos += 32;
2269   int Size;
2270   if (Inst.getOpcode() == Mips::DINSM ||
2271       Inst.getOpcode() == Mips::DINSU)
2272     Size = (int) Insn - Pos + 33;
2273   else
2274     Size = (int) Insn - Pos + 1;
2275   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2276   return MCDisassembler::Success;
2277 }
2278
2279 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2280                                      uint64_t Address, const void *Decoder) {
2281   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2282   return MCDisassembler::Success;
2283 }
2284
2285 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2286                                      uint64_t Address, const void *Decoder) {
2287   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2288   return MCDisassembler::Success;
2289 }
2290
2291 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2292                                   uint64_t Address, const void *Decoder) {
2293   int32_t DecodedValue;
2294   switch (Insn) {
2295   case 0: DecodedValue = 256; break;
2296   case 1: DecodedValue = 257; break;
2297   case 510: DecodedValue = -258; break;
2298   case 511: DecodedValue = -257; break;
2299   default: DecodedValue = SignExtend32<9>(Insn); break;
2300   }
2301   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2302   return MCDisassembler::Success;
2303 }
2304
2305 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2306                                     uint64_t Address, const void *Decoder) {
2307   // Insn must be >= 0, since it is unsigned that condition is always true.
2308   assert(Insn < 16);
2309   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2310                              255, 32768, 65535};
2311   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2312   return MCDisassembler::Success;
2313 }
2314
2315 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2316                                          unsigned Insn,
2317                                          uint64_t Address,
2318                                          const void *Decoder) {
2319   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2320                      Mips::S6, Mips::S7, Mips::FP};
2321   unsigned RegNum;
2322
2323   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2324
2325   // Empty register lists are not allowed.
2326   if (RegLst == 0)
2327     return MCDisassembler::Fail;
2328
2329   RegNum = RegLst & 0xf;
2330
2331   // RegLst values 10-15, and 26-31 are reserved.
2332   if (RegNum > 9)
2333     return MCDisassembler::Fail;
2334
2335   for (unsigned i = 0; i < RegNum; i++)
2336     Inst.addOperand(MCOperand::createReg(Regs[i]));
2337
2338   if (RegLst & 0x10)
2339     Inst.addOperand(MCOperand::createReg(Mips::RA));
2340
2341   return MCDisassembler::Success;
2342 }
2343
2344 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2345                                            uint64_t Address,
2346                                            const void *Decoder) {
2347   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2348   unsigned RegLst;
2349   switch(Inst.getOpcode()) {
2350   default:
2351     RegLst = fieldFromInstruction(Insn, 4, 2);
2352     break;
2353   case Mips::LWM16_MMR6:
2354   case Mips::SWM16_MMR6:
2355     RegLst = fieldFromInstruction(Insn, 8, 2);
2356     break;
2357   }
2358   unsigned RegNum = RegLst & 0x3;
2359
2360   for (unsigned i = 0; i <= RegNum; i++)
2361     Inst.addOperand(MCOperand::createReg(Regs[i]));
2362
2363   Inst.addOperand(MCOperand::createReg(Mips::RA));
2364
2365   return MCDisassembler::Success;
2366 }
2367
2368 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2369                                        uint64_t Address, const void *Decoder) {
2370   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2371
2372   switch (RegPair) {
2373   default:
2374     return MCDisassembler::Fail;
2375   case 0:
2376     Inst.addOperand(MCOperand::createReg(Mips::A1));
2377     Inst.addOperand(MCOperand::createReg(Mips::A2));
2378     break;
2379   case 1:
2380     Inst.addOperand(MCOperand::createReg(Mips::A1));
2381     Inst.addOperand(MCOperand::createReg(Mips::A3));
2382     break;
2383   case 2:
2384     Inst.addOperand(MCOperand::createReg(Mips::A2));
2385     Inst.addOperand(MCOperand::createReg(Mips::A3));
2386     break;
2387   case 3:
2388     Inst.addOperand(MCOperand::createReg(Mips::A0));
2389     Inst.addOperand(MCOperand::createReg(Mips::S5));
2390     break;
2391   case 4:
2392     Inst.addOperand(MCOperand::createReg(Mips::A0));
2393     Inst.addOperand(MCOperand::createReg(Mips::S6));
2394     break;
2395   case 5:
2396     Inst.addOperand(MCOperand::createReg(Mips::A0));
2397     Inst.addOperand(MCOperand::createReg(Mips::A1));
2398     break;
2399   case 6:
2400     Inst.addOperand(MCOperand::createReg(Mips::A0));
2401     Inst.addOperand(MCOperand::createReg(Mips::A2));
2402     break;
2403   case 7:
2404     Inst.addOperand(MCOperand::createReg(Mips::A0));
2405     Inst.addOperand(MCOperand::createReg(Mips::A3));
2406     break;
2407   }
2408
2409   return MCDisassembler::Success;
2410 }
2411
2412 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2413                                      uint64_t Address, const void *Decoder) {
2414   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2415   return MCDisassembler::Success;
2416 }
2417
2418 template <typename InsnType>
2419 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2420   uint64_t Address,
2421   const void *Decoder) {
2422   // We have:
2423   //    0b000111 ttttt sssss iiiiiiiiiiiiiiii
2424   //      Invalid      if rt == 0
2425   //      BGTZALC_MMR6 if rs == 0 && rt != 0
2426   //      BLTZALC_MMR6 if rs != 0 && rs == rt
2427   //      BLTUC_MMR6   if rs != 0 && rs != rt
2428
2429   InsnType Rt = fieldFromInstruction(insn, 21, 5);
2430   InsnType Rs = fieldFromInstruction(insn, 16, 5);
2431   InsnType Imm = 0;
2432   bool HasRs = false;
2433   bool HasRt = false;
2434
2435   if (Rt == 0)
2436     return MCDisassembler::Fail;
2437   else if (Rs == 0) {
2438     MI.setOpcode(Mips::BGTZALC_MMR6);
2439     HasRt = true;
2440     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2441   }
2442   else if (Rs == Rt) {
2443     MI.setOpcode(Mips::BLTZALC_MMR6);
2444     HasRs = true;
2445     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2446   }
2447   else {
2448     MI.setOpcode(Mips::BLTUC_MMR6);
2449     HasRs = true;
2450     HasRt = true;
2451     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2452   }
2453
2454   if (HasRs)
2455     MI.addOperand(
2456     MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2457
2458   if (HasRt)
2459     MI.addOperand(
2460     MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2461
2462   MI.addOperand(MCOperand::createImm(Imm));
2463
2464   return MCDisassembler::Success;
2465 }
2466
2467 template <typename InsnType>
2468 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
2469   uint64_t Address,
2470   const void *Decoder) {
2471   // We have:
2472   //    0b000110 ttttt sssss iiiiiiiiiiiiiiii
2473   //      Invalid        if rt == 0
2474   //      BLEZALC_MMR6   if rs == 0  && rt != 0
2475   //      BGEZALC_MMR6   if rs == rt && rt != 0
2476   //      BGEUC_MMR6     if rs != rt && rs != 0  && rt != 0
2477
2478   InsnType Rt = fieldFromInstruction(insn, 21, 5);
2479   InsnType Rs = fieldFromInstruction(insn, 16, 5);
2480   InsnType Imm = 0;
2481   bool HasRs = false;
2482
2483   if (Rt == 0)
2484     return MCDisassembler::Fail;
2485   else if (Rs == 0) {
2486     MI.setOpcode(Mips::BLEZALC_MMR6);
2487     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2488   }
2489   else if (Rs == Rt) {
2490     MI.setOpcode(Mips::BGEZALC_MMR6);
2491     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2492   }
2493   else {
2494     HasRs = true;
2495     MI.setOpcode(Mips::BGEUC_MMR6);
2496     Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2497   }
2498
2499   if (HasRs)
2500     MI.addOperand(
2501     MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2502   MI.addOperand(
2503     MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2504
2505   MI.addOperand(MCOperand::createImm(Imm));
2506
2507   return MCDisassembler::Success;
2508 }