1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Mips MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstPrinter.h"
15 #include "MCTargetDesc/MipsMCExpr.h"
16 #include "MipsInstrInfo.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define PRINT_ALIAS_INSTR
29 #include "MipsGenAsmWriter.inc"
32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34 return MI.getOperand(OpNo).getReg() == R;
37 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
40 case FCOND_T: return "f";
42 case FCOND_OR: return "un";
44 case FCOND_UNE: return "eq";
46 case FCOND_ONE: return "ueq";
48 case FCOND_UGE: return "olt";
50 case FCOND_OGE: return "ult";
52 case FCOND_UGT: return "ole";
54 case FCOND_OGT: return "ule";
56 case FCOND_ST: return "sf";
58 case FCOND_GLE: return "ngle";
60 case FCOND_SNE: return "seq";
62 case FCOND_GL: return "ngl";
64 case FCOND_NLT: return "lt";
66 case FCOND_GE: return "nge";
68 case FCOND_NLE: return "le";
70 case FCOND_GT: return "ngt";
72 llvm_unreachable("Impossible condition code!");
75 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
76 OS << '$' << StringRef(getRegisterName(RegNo)).lower();
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
80 StringRef Annot, const MCSubtargetInfo &STI) {
81 switch (MI->getOpcode()) {
86 O << "\t.set\tpush\n";
87 O << "\t.set\tmips32r2\n";
91 printSaveRestore(MI, O);
92 O << " # 16 bit inst\n";
96 printSaveRestore(MI, O);
101 printSaveRestore(MI, O);
102 O << " # 16 bit inst\n";
104 case Mips::RestoreX16:
106 printSaveRestore(MI, O);
111 // Try to print any aliases first.
112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
113 printInstruction(MI, O);
114 printAnnotation(O, Annot);
116 switch (MI->getOpcode()) {
121 O << "\n\t.set\tpop";
125 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
127 const MCOperand &Op = MI->getOperand(OpNo);
129 printRegName(O, Op.getReg());
134 O << formatImm(Op.getImm());
138 assert(Op.isExpr() && "unknown operand kind in printOperand");
139 Op.getExpr()->print(O, &MAI, true);
142 template <unsigned Bits, unsigned Offset>
143 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
144 const MCOperand &MO = MI->getOperand(opNum);
146 uint64_t Imm = MO.getImm();
148 Imm &= (1 << Bits) - 1;
154 printOperand(MI, opNum, O);
157 void MipsInstPrinter::
158 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
159 // Load/Store memory operands -- imm($reg)
160 // If PIC target the target is loaded as the
161 // pattern lw $25,%call16($28)
163 // opNum can be invalid if instruction had reglist as operand.
164 // MemOperand is always last operand of instruction (base + offset).
165 switch (MI->getOpcode()) {
171 case Mips::SWM16_MMR6:
173 case Mips::LWM16_MMR6:
174 opNum = MI->getNumOperands() - 2;
178 printOperand(MI, opNum+1, O);
180 printOperand(MI, opNum, O);
184 void MipsInstPrinter::
185 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
186 // when using stack locations for not load/store instructions
187 // print the same way as all normal 3 operand instructions.
188 printOperand(MI, opNum, O);
190 printOperand(MI, opNum+1, O);
193 void MipsInstPrinter::
194 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
195 const MCOperand& MO = MI->getOperand(opNum);
196 O << MipsFCCToString((Mips::CondCode)MO.getImm());
199 void MipsInstPrinter::
200 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
201 llvm_unreachable("TODO");
204 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
205 unsigned OpNo, raw_ostream &OS) {
206 OS << "\t" << Str << "\t";
207 printOperand(&MI, OpNo, OS);
211 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
212 unsigned OpNo0, unsigned OpNo1,
214 printAlias(Str, MI, OpNo0, OS);
216 printOperand(&MI, OpNo1, OS);
220 bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
221 switch (MI.getOpcode()) {
224 // beq $zero, $zero, $L2 => b $L2
225 // beq $r0, $zero, $L2 => beqz $r0, $L2
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
227 printAlias("b", MI, 2, OS)) ||
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
230 // beq $r0, $zero, $L2 => beqz $r0, $L2
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
234 // bne $r0, $zero, $L2 => bnez $r0, $L2
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
237 // bne $r0, $zero, $L2 => bnez $r0, $L2
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
240 // bgezal $zero, $L1 => bal $L1
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
243 // bc1t $fcc0, $L1 => bc1t $L1
244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
246 // bc1f $fcc0, $L1 => bc1f $L1
247 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
249 // jalr $ra, $r1 => jalr $r1
250 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
252 // jalr $ra, $r1 => jalr $r1
253 return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
257 // nor $r0, $r1, $zero => not $r0, $r1
258 return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
260 // nor $r0, $r1, $zero => not $r0, $r1
261 return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
263 // or $r0, $r1, $zero => move $r0, $r1
264 return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
265 default: return false;
269 void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
270 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
271 if (i != 0) O << ", ";
272 if (MI->getOperand(i).isReg())
273 printRegName(O, MI->getOperand(i).getReg());
275 printUImm<16>(MI, i, O);
279 void MipsInstPrinter::
280 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
281 // - 2 because register List is always first operand of instruction and it is
282 // always followed by memory operand (base + offset).
283 for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
286 printRegName(O, MI->getOperand(i).getReg());