1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MipsABIInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringRef.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/MC/MCTargetOptions.h"
18 // Note: this option is defined here to be visible from libLLVMMipsAsmParser
19 // and libLLVMMipsCodeGen
21 EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
22 cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
28 static const MCPhysReg Mips64IntRegs[8] = {
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
33 ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
35 return makeArrayRef(O32IntRegs);
36 if (IsN32() || IsN64())
37 return makeArrayRef(Mips64IntRegs);
38 llvm_unreachable("Unhandled ABI");
41 ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
43 return makeArrayRef(O32IntRegs);
44 if (IsN32() || IsN64())
45 return makeArrayRef(Mips64IntRegs);
46 llvm_unreachable("Unhandled ABI");
49 unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
51 return CC != CallingConv::Fast ? 16 : 0;
52 if (IsN32() || IsN64())
54 llvm_unreachable("Unhandled ABI");
57 MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
58 const MCTargetOptions &Options) {
59 if (Options.getABIName().startswith("o32"))
60 return MipsABIInfo::O32();
61 if (Options.getABIName().startswith("n32"))
62 return MipsABIInfo::N32();
63 if (Options.getABIName().startswith("n64"))
64 return MipsABIInfo::N64();
65 if (TT.getEnvironment() == llvm::Triple::GNUABIN32)
66 return MipsABIInfo::N32();
67 assert(Options.getABIName().empty() && "Unknown ABI option for MIPS");
70 return MipsABIInfo::N64();
71 return MipsABIInfo::O32();
74 unsigned MipsABIInfo::GetStackPtr() const {
75 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
78 unsigned MipsABIInfo::GetFramePtr() const {
79 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
82 unsigned MipsABIInfo::GetBasePtr() const {
83 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
86 unsigned MipsABIInfo::GetGlobalPtr() const {
87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
90 unsigned MipsABIInfo::GetNullPtr() const {
91 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
94 unsigned MipsABIInfo::GetZeroReg() const {
95 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
98 unsigned MipsABIInfo::GetPtrAdduOp() const {
99 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
102 unsigned MipsABIInfo::GetPtrAddiuOp() const {
103 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
106 unsigned MipsABIInfo::GetPtrSubuOp() const {
107 return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
110 unsigned MipsABIInfo::GetPtrAndOp() const {
111 return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
114 unsigned MipsABIInfo::GetGPRMoveOp() const {
115 return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
118 unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
119 static const unsigned EhDataReg[] = {
120 Mips::A0, Mips::A1, Mips::A2, Mips::A3
122 static const unsigned EhDataReg64[] = {
123 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
126 return IsN64() ? EhDataReg64[I] : EhDataReg[I];