contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

   1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Mips specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18
  19 namespace llvm {
  20 class MCAsmBackend;
  21 class MCCodeEmitter;
  22 class MCContext;
  23 class MCInstrInfo;
  24 class MCObjectWriter;
  25 class MCRegisterInfo;
  26 class MCSubtargetInfo;
  27 class MCTargetOptions;
  28 class StringRef;
  29 class Target;
  30 class Triple;
  31 class raw_ostream;
  32 class raw_pwrite_stream;
  33
  34 Target &getTheMipsTarget();
  35 Target &getTheMipselTarget();
  36 Target &getTheMips64Target();
  37 Target &getTheMips64elTarget();
  38
  39 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
  40                                          const MCRegisterInfo &MRI,
  41                                          MCContext &Ctx);
  42 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
  43                                          const MCRegisterInfo &MRI,
  44                                          MCContext &Ctx);
  45
  46 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
  47                                        const MCRegisterInfo &MRI,
  48                                        const Triple &TT, StringRef CPU,
  49                                        const MCTargetOptions &Options);
  50 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
  51                                        const MCRegisterInfo &MRI,
  52                                        const Triple &TT, StringRef CPU,
  53                                        const MCTargetOptions &Options);
  54 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
  55                                        const MCRegisterInfo &MRI,
  56                                        const Triple &TT, StringRef CPU,
  57                                        const MCTargetOptions &Options);
  58 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
  59                                        const MCRegisterInfo &MRI,
  60                                        const Triple &TT, StringRef CPU,
  61                                        const MCTargetOptions &Options);
  62
  63 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
  64                                           bool IsLittleEndian, bool Is64Bit);
  65
  66 namespace MIPS_MC {
  67 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
  68 }
  69
  70 } // End llvm namespace
  71
  72 // Defines symbolic names for Mips registers.  This defines a mapping from
  73 // register name to register number.
  74 #define GET_REGINFO_ENUM
  75 #include "MipsGenRegisterInfo.inc"
  76
  77 // Defines symbolic names for the Mips instructions.
  78 #define GET_INSTRINFO_ENUM
  79 #include "MipsGenInstrInfo.inc"
  80
  81 #define GET_SUBTARGETINFO_ENUM
  82 #include "MipsGenSubtargetInfo.inc"
  83
  84 #endif