1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target streamer methods.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCExpr.h"
19 #include "MipsMCTargetDesc.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
33 static cl::opt<bool> RoundSectionSizes(
34 "mips-round-section-sizes", cl::init(false),
35 cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
39 : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
44 void MipsTargetStreamer::setUsesMicroMips() {}
45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetMt() {}
54 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
56 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
57 forbidModuleDirective();
59 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
60 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
61 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
62 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
63 void MipsTargetStreamer::emitDirectiveNaN2008() {}
64 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
65 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
66 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
67 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
68 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
69 unsigned ReturnReg) {}
70 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
71 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
73 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
74 forbidModuleDirective();
76 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
95 forbidModuleDirective();
97 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
98 forbidModuleDirective();
100 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
101 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
102 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
103 bool MipsTargetStreamer::emitDirectiveCpRestore(
104 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
105 const MCSubtargetInfo *STI) {
106 forbidModuleDirective();
109 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
110 const MCSymbol &Sym, bool IsReg) {
112 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
113 bool SaveLocationIsRegister) {}
115 void MipsTargetStreamer::emitDirectiveModuleFP() {}
117 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
118 if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
119 report_fatal_error("+nooddspreg is only valid for O32");
121 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
122 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
123 void MipsTargetStreamer::emitDirectiveModuleMT() {}
124 void MipsTargetStreamer::emitDirectiveSetFp(
125 MipsABIFlagsSection::FpABIKind Value) {
126 forbidModuleDirective();
128 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
129 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
130 forbidModuleDirective();
133 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
134 const MCSubtargetInfo *STI) {
136 TmpInst.setOpcode(Opcode);
137 TmpInst.addOperand(MCOperand::createReg(Reg0));
138 TmpInst.setLoc(IDLoc);
139 getStreamer().EmitInstruction(TmpInst, *STI);
142 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
143 SMLoc IDLoc, const MCSubtargetInfo *STI) {
145 TmpInst.setOpcode(Opcode);
146 TmpInst.addOperand(MCOperand::createReg(Reg0));
147 TmpInst.addOperand(Op1);
148 TmpInst.setLoc(IDLoc);
149 getStreamer().EmitInstruction(TmpInst, *STI);
152 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
153 SMLoc IDLoc, const MCSubtargetInfo *STI) {
154 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
157 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
158 SMLoc IDLoc, const MCSubtargetInfo *STI) {
159 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
162 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
163 SMLoc IDLoc, const MCSubtargetInfo *STI) {
165 TmpInst.setOpcode(Opcode);
166 TmpInst.addOperand(MCOperand::createImm(Imm1));
167 TmpInst.addOperand(MCOperand::createImm(Imm2));
168 TmpInst.setLoc(IDLoc);
169 getStreamer().EmitInstruction(TmpInst, *STI);
172 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
173 MCOperand Op2, SMLoc IDLoc,
174 const MCSubtargetInfo *STI) {
176 TmpInst.setOpcode(Opcode);
177 TmpInst.addOperand(MCOperand::createReg(Reg0));
178 TmpInst.addOperand(MCOperand::createReg(Reg1));
179 TmpInst.addOperand(Op2);
180 TmpInst.setLoc(IDLoc);
181 getStreamer().EmitInstruction(TmpInst, *STI);
184 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
185 unsigned Reg2, SMLoc IDLoc,
186 const MCSubtargetInfo *STI) {
187 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
190 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
191 int16_t Imm, SMLoc IDLoc,
192 const MCSubtargetInfo *STI) {
193 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
196 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
197 unsigned Reg1, int16_t Imm0, int16_t Imm1,
198 int16_t Imm2, SMLoc IDLoc,
199 const MCSubtargetInfo *STI) {
201 TmpInst.setOpcode(Opcode);
202 TmpInst.addOperand(MCOperand::createReg(Reg0));
203 TmpInst.addOperand(MCOperand::createReg(Reg1));
204 TmpInst.addOperand(MCOperand::createImm(Imm0));
205 TmpInst.addOperand(MCOperand::createImm(Imm1));
206 TmpInst.addOperand(MCOperand::createImm(Imm2));
207 TmpInst.setLoc(IDLoc);
208 getStreamer().EmitInstruction(TmpInst, *STI);
211 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
212 unsigned TrgReg, bool Is64Bit,
213 const MCSubtargetInfo *STI) {
214 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
218 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
219 int16_t ShiftAmount, SMLoc IDLoc,
220 const MCSubtargetInfo *STI) {
221 if (ShiftAmount >= 32) {
222 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
226 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
229 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
230 const MCSubtargetInfo *STI) {
231 if (hasShortDelaySlot)
232 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
234 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
237 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
238 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
241 /// Emit the $gp restore operation for .cprestore.
242 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
243 const MCSubtargetInfo *STI) {
244 emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
248 /// Emit a store instruction with an immediate offset.
249 void MipsTargetStreamer::emitStoreWithImmOffset(
250 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
251 function_ref<unsigned()> GetATReg, SMLoc IDLoc,
252 const MCSubtargetInfo *STI) {
253 if (isInt<16>(Offset)) {
254 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
258 // sw $8, offset($8) => lui $at, %hi(offset)
260 // sw $8, %lo(offset)($at)
262 unsigned ATReg = GetATReg();
266 unsigned LoOffset = Offset & 0x0000ffff;
267 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
269 // If msb of LoOffset is 1(negative number) we must increment HiOffset
270 // to account for the sign-extension of the low part.
271 if (LoOffset & 0x8000)
274 // Generate the base address in ATReg.
275 emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
276 if (BaseReg != Mips::ZERO)
277 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
278 // Emit the store with the adjusted base and offset.
279 emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
282 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
283 /// out of range for a simm16 will be expanded to appropriate instructions.
284 void MipsTargetStreamer::emitStoreWithSymOffset(
285 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
286 MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
287 const MCSubtargetInfo *STI) {
288 // sw $8, sym => lui $at, %hi(sym)
289 // sw $8, %lo(sym)($at)
291 // Generate the base address in ATReg.
292 emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
293 if (BaseReg != Mips::ZERO)
294 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
295 // Emit the store with the adjusted base and offset.
296 emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
299 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
300 /// permitted to be the same register iff DstReg is distinct from BaseReg and
301 /// DstReg is a GPR. It is the callers responsibility to identify such cases
302 /// and pass the appropriate register in TmpReg.
303 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
304 unsigned BaseReg, int64_t Offset,
305 unsigned TmpReg, SMLoc IDLoc,
306 const MCSubtargetInfo *STI) {
307 if (isInt<16>(Offset)) {
308 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
312 // 1) lw $8, offset($9) => lui $8, %hi(offset)
314 // lw $8, %lo(offset)($9)
315 // 2) lw $8, offset($8) => lui $at, %hi(offset)
317 // lw $8, %lo(offset)($at)
319 unsigned LoOffset = Offset & 0x0000ffff;
320 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
322 // If msb of LoOffset is 1(negative number) we must increment HiOffset
323 // to account for the sign-extension of the low part.
324 if (LoOffset & 0x8000)
327 // Generate the base address in TmpReg.
328 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
329 if (BaseReg != Mips::ZERO)
330 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
331 // Emit the load with the adjusted base and offset.
332 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
335 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
336 /// out of range for a simm16 will be expanded to appropriate instructions.
337 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
338 /// GPR. It is the callers responsibility to identify such cases and pass the
339 /// appropriate register in TmpReg.
340 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
342 MCOperand &HiOperand,
343 MCOperand &LoOperand,
344 unsigned TmpReg, SMLoc IDLoc,
345 const MCSubtargetInfo *STI) {
346 // 1) lw $8, sym => lui $8, %hi(sym)
347 // lw $8, %lo(sym)($8)
348 // 2) ldc1 $f0, sym => lui $at, %hi(sym)
349 // ldc1 $f0, %lo(sym)($at)
351 // Generate the base address in TmpReg.
352 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
353 if (BaseReg != Mips::ZERO)
354 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
355 // Emit the load with the adjusted base and offset.
356 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
359 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
360 formatted_raw_ostream &OS)
361 : MipsTargetStreamer(S), OS(OS) {}
363 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
364 OS << "\t.set\tmicromips\n";
365 forbidModuleDirective();
368 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
369 OS << "\t.set\tnomicromips\n";
370 forbidModuleDirective();
373 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
374 OS << "\t.set\tmips16\n";
375 forbidModuleDirective();
378 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
379 OS << "\t.set\tnomips16\n";
380 MipsTargetStreamer::emitDirectiveSetNoMips16();
383 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
384 OS << "\t.set\treorder\n";
385 MipsTargetStreamer::emitDirectiveSetReorder();
388 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
389 OS << "\t.set\tnoreorder\n";
390 forbidModuleDirective();
393 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
394 OS << "\t.set\tmacro\n";
395 MipsTargetStreamer::emitDirectiveSetMacro();
398 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
399 OS << "\t.set\tnomacro\n";
400 MipsTargetStreamer::emitDirectiveSetNoMacro();
403 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
404 OS << "\t.set\tmsa\n";
405 MipsTargetStreamer::emitDirectiveSetMsa();
408 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
409 OS << "\t.set\tnomsa\n";
410 MipsTargetStreamer::emitDirectiveSetNoMsa();
413 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
414 OS << "\t.set\tmt\n";
415 MipsTargetStreamer::emitDirectiveSetMt();
418 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
419 OS << "\t.set\tnomt\n";
420 MipsTargetStreamer::emitDirectiveSetNoMt();
423 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
424 OS << "\t.set\tat\n";
425 MipsTargetStreamer::emitDirectiveSetAt();
428 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
429 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
430 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
433 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
434 OS << "\t.set\tnoat\n";
435 MipsTargetStreamer::emitDirectiveSetNoAt();
438 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
439 OS << "\t.end\t" << Name << '\n';
442 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
443 OS << "\t.ent\t" << Symbol.getName() << '\n';
446 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
448 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
450 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
451 OS << "\t.nan\tlegacy\n";
454 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
455 OS << "\t.option\tpic0\n";
458 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
459 OS << "\t.option\tpic2\n";
462 void MipsTargetAsmStreamer::emitDirectiveInsn() {
463 MipsTargetStreamer::emitDirectiveInsn();
467 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
468 unsigned ReturnReg) {
470 << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
472 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
475 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
476 OS << "\t.set arch=" << Arch << "\n";
477 MipsTargetStreamer::emitDirectiveSetArch(Arch);
480 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
481 OS << "\t.set\tmips0\n";
482 MipsTargetStreamer::emitDirectiveSetMips0();
485 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
486 OS << "\t.set\tmips1\n";
487 MipsTargetStreamer::emitDirectiveSetMips1();
490 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
491 OS << "\t.set\tmips2\n";
492 MipsTargetStreamer::emitDirectiveSetMips2();
495 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
496 OS << "\t.set\tmips3\n";
497 MipsTargetStreamer::emitDirectiveSetMips3();
500 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
501 OS << "\t.set\tmips4\n";
502 MipsTargetStreamer::emitDirectiveSetMips4();
505 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
506 OS << "\t.set\tmips5\n";
507 MipsTargetStreamer::emitDirectiveSetMips5();
510 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
511 OS << "\t.set\tmips32\n";
512 MipsTargetStreamer::emitDirectiveSetMips32();
515 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
516 OS << "\t.set\tmips32r2\n";
517 MipsTargetStreamer::emitDirectiveSetMips32R2();
520 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
521 OS << "\t.set\tmips32r3\n";
522 MipsTargetStreamer::emitDirectiveSetMips32R3();
525 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
526 OS << "\t.set\tmips32r5\n";
527 MipsTargetStreamer::emitDirectiveSetMips32R5();
530 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
531 OS << "\t.set\tmips32r6\n";
532 MipsTargetStreamer::emitDirectiveSetMips32R6();
535 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
536 OS << "\t.set\tmips64\n";
537 MipsTargetStreamer::emitDirectiveSetMips64();
540 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
541 OS << "\t.set\tmips64r2\n";
542 MipsTargetStreamer::emitDirectiveSetMips64R2();
545 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
546 OS << "\t.set\tmips64r3\n";
547 MipsTargetStreamer::emitDirectiveSetMips64R3();
550 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
551 OS << "\t.set\tmips64r5\n";
552 MipsTargetStreamer::emitDirectiveSetMips64R5();
555 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
556 OS << "\t.set\tmips64r6\n";
557 MipsTargetStreamer::emitDirectiveSetMips64R6();
560 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
561 OS << "\t.set\tdsp\n";
562 MipsTargetStreamer::emitDirectiveSetDsp();
565 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
566 OS << "\t.set\tnodsp\n";
567 MipsTargetStreamer::emitDirectiveSetNoDsp();
570 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
571 OS << "\t.set\tpop\n";
572 MipsTargetStreamer::emitDirectiveSetPop();
575 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
576 OS << "\t.set\tpush\n";
577 MipsTargetStreamer::emitDirectiveSetPush();
580 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
581 OS << "\t.set\tsoftfloat\n";
582 MipsTargetStreamer::emitDirectiveSetSoftFloat();
585 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
586 OS << "\t.set\thardfloat\n";
587 MipsTargetStreamer::emitDirectiveSetHardFloat();
590 // Print a 32 bit hex number with all numbers.
591 static void printHex32(unsigned Value, raw_ostream &OS) {
593 for (int i = 7; i >= 0; i--)
594 OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
597 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
598 int CPUTopSavedRegOff) {
600 printHex32(CPUBitmask, OS);
601 OS << ',' << CPUTopSavedRegOff << '\n';
604 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
605 int FPUTopSavedRegOff) {
607 printHex32(FPUBitmask, OS);
608 OS << "," << FPUTopSavedRegOff << '\n';
611 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
613 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
614 forbidModuleDirective();
617 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
618 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
619 const MCSubtargetInfo *STI) {
620 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
621 OS << "\t.cprestore\t" << Offset << "\n";
625 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
629 OS << "\t.cpsetup\t$"
630 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
634 << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
641 forbidModuleDirective();
644 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
645 bool SaveLocationIsRegister) {
647 forbidModuleDirective();
650 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
651 OS << "\t.module\tfp=";
652 OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
655 void MipsTargetAsmStreamer::emitDirectiveSetFp(
656 MipsABIFlagsSection::FpABIKind Value) {
657 MipsTargetStreamer::emitDirectiveSetFp(Value);
660 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
663 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
664 MipsTargetStreamer::emitDirectiveModuleOddSPReg();
666 OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
669 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
670 MipsTargetStreamer::emitDirectiveSetOddSPReg();
671 OS << "\t.set\toddspreg\n";
674 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
675 MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
676 OS << "\t.set\tnooddspreg\n";
679 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
680 OS << "\t.module\tsoftfloat\n";
683 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
684 OS << "\t.module\thardfloat\n";
687 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
688 OS << "\t.module\tmt\n";
691 // This part is for ELF object output.
692 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
693 const MCSubtargetInfo &STI)
694 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
695 MCAssembler &MCA = getStreamer().getAssembler();
697 // It's possible that MCObjectFileInfo isn't fully initialized at this point
698 // due to an initialization order problem where LLVMTargetMachine creates the
699 // target streamer before TargetLoweringObjectFile calls
700 // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
701 // covers all cases so this statement covers most cases and direct object
702 // emission must call setPic() once MCObjectFileInfo has been initialized. The
703 // cases we don't handle here are covered by MipsAsmPrinter.
704 Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
706 const FeatureBitset &Features = STI.getFeatureBits();
708 // Set the header flags that we can in the constructor.
709 // FIXME: This is a fairly terrible hack. We set the rest
710 // of these in the destructor. The problem here is two-fold:
712 // a: Some of the eflags can be set/reset by directives.
713 // b: There aren't any usage paths that initialize the ABI
714 // pointer until after we initialize either an assembler
715 // or the target machine.
716 // We can fix this by making the target streamer construct
717 // the ABI, but this is fraught with wide ranging dependency
719 unsigned EFlags = MCA.getELFHeaderEFlags();
721 // FIXME: Fix a dependency issue by instantiating the ABI object to some
722 // default based off the triple. The triple doesn't describe the target
723 // fully, but any external user of the API that uses the MCTargetStreamer
724 // would otherwise crash on assertion failure.
727 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
728 STI.getTargetTriple().getArch() == Triple::ArchType::mips
730 : MipsABIInfo::N64());
733 if (Features[Mips::FeatureMips64r6])
734 EFlags |= ELF::EF_MIPS_ARCH_64R6;
735 else if (Features[Mips::FeatureMips64r2] ||
736 Features[Mips::FeatureMips64r3] ||
737 Features[Mips::FeatureMips64r5])
738 EFlags |= ELF::EF_MIPS_ARCH_64R2;
739 else if (Features[Mips::FeatureMips64])
740 EFlags |= ELF::EF_MIPS_ARCH_64;
741 else if (Features[Mips::FeatureMips5])
742 EFlags |= ELF::EF_MIPS_ARCH_5;
743 else if (Features[Mips::FeatureMips4])
744 EFlags |= ELF::EF_MIPS_ARCH_4;
745 else if (Features[Mips::FeatureMips3])
746 EFlags |= ELF::EF_MIPS_ARCH_3;
747 else if (Features[Mips::FeatureMips32r6])
748 EFlags |= ELF::EF_MIPS_ARCH_32R6;
749 else if (Features[Mips::FeatureMips32r2] ||
750 Features[Mips::FeatureMips32r3] ||
751 Features[Mips::FeatureMips32r5])
752 EFlags |= ELF::EF_MIPS_ARCH_32R2;
753 else if (Features[Mips::FeatureMips32])
754 EFlags |= ELF::EF_MIPS_ARCH_32;
755 else if (Features[Mips::FeatureMips2])
756 EFlags |= ELF::EF_MIPS_ARCH_2;
758 EFlags |= ELF::EF_MIPS_ARCH_1;
761 if (Features[Mips::FeatureCnMips])
762 EFlags |= ELF::EF_MIPS_MACH_OCTEON;
765 if (Features[Mips::FeatureNaN2008])
766 EFlags |= ELF::EF_MIPS_NAN2008;
768 MCA.setELFHeaderEFlags(EFlags);
771 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
772 auto *Symbol = cast<MCSymbolELF>(S);
773 getStreamer().getAssembler().registerSymbol(*Symbol);
774 uint8_t Type = Symbol->getType();
775 if (Type != ELF::STT_FUNC)
778 if (isMicroMipsEnabled())
779 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
782 void MipsTargetELFStreamer::finish() {
783 MCAssembler &MCA = getStreamer().getAssembler();
784 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
786 // .bss, .text and .data are always at least 16-byte aligned.
787 MCSection &TextSection = *OFI.getTextSection();
788 MCA.registerSection(TextSection);
789 MCSection &DataSection = *OFI.getDataSection();
790 MCA.registerSection(DataSection);
791 MCSection &BSSSection = *OFI.getBSSSection();
792 MCA.registerSection(BSSSection);
794 TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
795 DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
796 BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
798 if (RoundSectionSizes) {
799 // Make sections sizes a multiple of the alignment. This is useful for
800 // verifying the output of IAS against the output of other assemblers but
801 // it's not necessary to produce a correct object and increases section
803 MCStreamer &OS = getStreamer();
804 for (MCSection &S : MCA) {
805 MCSectionELF &Section = static_cast<MCSectionELF &>(S);
807 unsigned Alignment = Section.getAlignment();
809 OS.SwitchSection(&Section);
810 if (Section.UseCodeAlign())
811 OS.EmitCodeAlignment(Alignment, Alignment);
813 OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
818 const FeatureBitset &Features = STI.getFeatureBits();
820 // Update e_header flags. See the FIXME and comment above in
821 // the constructor for a full rundown on this.
822 unsigned EFlags = MCA.getELFHeaderEFlags();
825 // N64 does not require any ABI bits.
826 if (getABI().IsO32())
827 EFlags |= ELF::EF_MIPS_ABI_O32;
828 else if (getABI().IsN32())
829 EFlags |= ELF::EF_MIPS_ABI2;
831 if (Features[Mips::FeatureGP64Bit]) {
832 if (getABI().IsO32())
833 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
834 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
835 EFlags |= ELF::EF_MIPS_32BITMODE;
837 // -mplt is not implemented but we should act as if it was
839 if (!Features[Mips::FeatureNoABICalls])
840 EFlags |= ELF::EF_MIPS_CPIC;
843 EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
845 MCA.setELFHeaderEFlags(EFlags);
847 // Emit all the option records.
848 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
850 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
851 MEF.EmitMipsOptionRecords();
856 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
857 auto *Symbol = cast<MCSymbolELF>(S);
858 // If on rhs is micromips symbol then mark Symbol as microMips.
859 if (Value->getKind() != MCExpr::SymbolRef)
861 const auto &RhsSym = cast<MCSymbolELF>(
862 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
864 if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
867 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
870 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
871 return static_cast<MCELFStreamer &>(Streamer);
874 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
875 MicroMipsEnabled = true;
876 forbidModuleDirective();
879 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
880 MicroMipsEnabled = false;
881 forbidModuleDirective();
884 void MipsTargetELFStreamer::setUsesMicroMips() {
885 MCAssembler &MCA = getStreamer().getAssembler();
886 unsigned Flags = MCA.getELFHeaderEFlags();
887 Flags |= ELF::EF_MIPS_MICROMIPS;
888 MCA.setELFHeaderEFlags(Flags);
891 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
892 MCAssembler &MCA = getStreamer().getAssembler();
893 unsigned Flags = MCA.getELFHeaderEFlags();
894 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
895 MCA.setELFHeaderEFlags(Flags);
896 forbidModuleDirective();
899 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
900 MCAssembler &MCA = getStreamer().getAssembler();
901 unsigned Flags = MCA.getELFHeaderEFlags();
902 Flags |= ELF::EF_MIPS_NOREORDER;
903 MCA.setELFHeaderEFlags(Flags);
904 forbidModuleDirective();
907 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
908 MCAssembler &MCA = getStreamer().getAssembler();
909 MCContext &Context = MCA.getContext();
910 MCStreamer &OS = getStreamer();
912 MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
914 MCSymbol *Sym = Context.getOrCreateSymbol(Name);
915 const MCSymbolRefExpr *ExprRef =
916 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
918 MCA.registerSection(*Sec);
919 Sec->setAlignment(4);
923 OS.SwitchSection(Sec);
925 OS.EmitValueImpl(ExprRef, 4);
927 OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
928 OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
930 OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
931 OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
933 OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
934 OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
935 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
937 // The .end directive marks the end of a procedure. Invalidate
938 // the information gathered up until this point.
939 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
943 // .end also implicitly sets the size.
944 MCSymbol *CurPCSym = Context.createTempSymbol();
945 OS.EmitLabel(CurPCSym);
946 const MCExpr *Size = MCBinaryExpr::createSub(
947 MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
950 // The ELFObjectWriter can determine the absolute size as it has access to
951 // the layout information of the assembly file, so a size expression rather
952 // than an absolute value is ok here.
953 static_cast<MCSymbolELF *>(Sym)->setSize(Size);
956 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
957 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
959 // .ent also acts like an implicit '.type symbol, STT_FUNC'
960 static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
963 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
964 MCAssembler &MCA = getStreamer().getAssembler();
965 unsigned Flags = MCA.getELFHeaderEFlags();
966 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
967 MCA.setELFHeaderEFlags(Flags);
970 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
971 MCAssembler &MCA = getStreamer().getAssembler();
972 unsigned Flags = MCA.getELFHeaderEFlags();
973 Flags |= ELF::EF_MIPS_NAN2008;
974 MCA.setELFHeaderEFlags(Flags);
977 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
978 MCAssembler &MCA = getStreamer().getAssembler();
979 unsigned Flags = MCA.getELFHeaderEFlags();
980 Flags &= ~ELF::EF_MIPS_NAN2008;
981 MCA.setELFHeaderEFlags(Flags);
984 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
985 MCAssembler &MCA = getStreamer().getAssembler();
986 unsigned Flags = MCA.getELFHeaderEFlags();
987 // This option overrides other PIC options like -KPIC.
989 Flags &= ~ELF::EF_MIPS_PIC;
990 MCA.setELFHeaderEFlags(Flags);
993 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
994 MCAssembler &MCA = getStreamer().getAssembler();
995 unsigned Flags = MCA.getELFHeaderEFlags();
997 // NOTE: We are following the GAS behaviour here which means the directive
998 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
999 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1000 // EF_MIPS_CPIC to be mutually exclusive.
1001 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1002 MCA.setELFHeaderEFlags(Flags);
1005 void MipsTargetELFStreamer::emitDirectiveInsn() {
1006 MipsTargetStreamer::emitDirectiveInsn();
1007 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1008 MEF.createPendingLabelRelocs();
1011 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1012 unsigned ReturnReg_) {
1013 MCContext &Context = getStreamer().getAssembler().getContext();
1014 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1016 FrameInfoSet = true;
1017 FrameReg = RegInfo->getEncodingValue(StackReg);
1018 FrameOffset = StackSize;
1019 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1022 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1023 int CPUTopSavedRegOff) {
1025 GPRBitMask = CPUBitmask;
1026 GPROffset = CPUTopSavedRegOff;
1029 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1030 int FPUTopSavedRegOff) {
1032 FPRBitMask = FPUBitmask;
1033 FPROffset = FPUTopSavedRegOff;
1036 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1038 // This directive expands to:
1039 // lui $gp, %hi(_gp_disp)
1040 // addui $gp, $gp, %lo(_gp_disp)
1041 // addu $gp, $gp, $reg
1042 // when support for position independent code is enabled.
1043 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1046 // There's a GNU extension controlled by -mno-shared that allows
1047 // locally-binding symbols to be accessed using absolute addresses.
1048 // This is currently not supported. When supported -mno-shared makes
1049 // .cpload expand to:
1050 // lui $gp, %hi(__gnu_local_gp)
1051 // addiu $gp, $gp, %lo(__gnu_local_gp)
1053 StringRef SymName("_gp_disp");
1054 MCAssembler &MCA = getStreamer().getAssembler();
1055 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1056 MCA.registerSymbol(*GP_Disp);
1059 TmpInst.setOpcode(Mips::LUi);
1060 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1061 const MCExpr *HiSym = MipsMCExpr::create(
1063 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1066 TmpInst.addOperand(MCOperand::createExpr(HiSym));
1067 getStreamer().EmitInstruction(TmpInst, STI);
1071 TmpInst.setOpcode(Mips::ADDiu);
1072 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1073 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1074 const MCExpr *LoSym = MipsMCExpr::create(
1076 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1079 TmpInst.addOperand(MCOperand::createExpr(LoSym));
1080 getStreamer().EmitInstruction(TmpInst, STI);
1084 TmpInst.setOpcode(Mips::ADDu);
1085 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1086 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1087 TmpInst.addOperand(MCOperand::createReg(RegNo));
1088 getStreamer().EmitInstruction(TmpInst, STI);
1090 forbidModuleDirective();
1093 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1094 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1095 const MCSubtargetInfo *STI) {
1096 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1097 // .cprestore offset
1098 // When PIC mode is enabled and the O32 ABI is used, this directive expands
1100 // sw $gp, offset($sp)
1101 // and adds a corresponding LW after every JAL.
1103 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1104 // is used in non-PIC mode.
1105 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1108 // Store the $gp on the stack.
1109 emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1114 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1116 const MCSymbol &Sym,
1118 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1119 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1122 forbidModuleDirective();
1124 MCAssembler &MCA = getStreamer().getAssembler();
1127 // Either store the old $gp in a register or on the stack
1129 // move $save, $gpreg
1130 emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1132 // sd $gpreg, offset($sp)
1133 emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1136 if (getABI().IsN32()) {
1137 MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1138 const MipsMCExpr *HiExpr = MipsMCExpr::create(
1139 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1141 const MipsMCExpr *LoExpr = MipsMCExpr::create(
1142 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1145 // lui $gp, %hi(__gnu_local_gp)
1146 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1148 // addiu $gp, $gp, %lo(__gnu_local_gp)
1149 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1155 const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1156 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1158 const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1159 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1162 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1163 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1165 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1166 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1169 // daddu $gp, $gp, $funcreg
1170 emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1173 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1174 bool SaveLocationIsRegister) {
1175 // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1176 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1180 // Either restore the old $gp from a register or on the stack
1181 if (SaveLocationIsRegister) {
1182 Inst.setOpcode(Mips::OR);
1183 Inst.addOperand(MCOperand::createReg(Mips::GP));
1184 Inst.addOperand(MCOperand::createReg(SaveLocation));
1185 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1187 Inst.setOpcode(Mips::LD);
1188 Inst.addOperand(MCOperand::createReg(Mips::GP));
1189 Inst.addOperand(MCOperand::createReg(Mips::SP));
1190 Inst.addOperand(MCOperand::createImm(SaveLocation));
1192 getStreamer().EmitInstruction(Inst, STI);
1194 forbidModuleDirective();
1197 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1198 MCAssembler &MCA = getStreamer().getAssembler();
1199 MCContext &Context = MCA.getContext();
1200 MCStreamer &OS = getStreamer();
1201 MCSectionELF *Sec = Context.getELFSection(
1202 ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1203 MCA.registerSection(*Sec);
1204 Sec->setAlignment(8);
1205 OS.SwitchSection(Sec);
1207 OS << ABIFlagsSection;