1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target streamer methods.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCExpr.h"
19 #include "MipsMCTargetDesc.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
33 static cl::opt<bool> RoundSectionSizes(
34 "mips-round-section-sizes", cl::init(false),
35 cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
39 : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
44 void MipsTargetStreamer::setUsesMicroMips() {}
45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetMt() {}
54 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetCRC() {}
56 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
57 void MipsTargetStreamer::emitDirectiveSetVirt() {}
58 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
59 void MipsTargetStreamer::emitDirectiveSetGINV() {}
60 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
61 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
62 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
63 forbidModuleDirective();
65 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
66 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
67 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
68 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
69 void MipsTargetStreamer::emitDirectiveNaN2008() {}
70 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
71 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
72 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
73 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
74 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
75 unsigned ReturnReg) {}
76 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
77 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
79 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
80 forbidModuleDirective();
82 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
95 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
96 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
97 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
98 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
99 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
100 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
101 forbidModuleDirective();
103 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
104 forbidModuleDirective();
106 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
107 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
108 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
109 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
110 bool MipsTargetStreamer::emitDirectiveCpRestore(
111 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
112 const MCSubtargetInfo *STI) {
113 forbidModuleDirective();
116 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
117 const MCSymbol &Sym, bool IsReg) {
119 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
120 bool SaveLocationIsRegister) {}
122 void MipsTargetStreamer::emitDirectiveModuleFP() {}
124 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
125 if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
126 report_fatal_error("+nooddspreg is only valid for O32");
128 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
129 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
130 void MipsTargetStreamer::emitDirectiveModuleMT() {}
131 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
132 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
133 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
134 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
135 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
136 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
137 void MipsTargetStreamer::emitDirectiveSetFp(
138 MipsABIFlagsSection::FpABIKind Value) {
139 forbidModuleDirective();
141 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
142 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
143 forbidModuleDirective();
146 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
147 const MCSubtargetInfo *STI) {
149 TmpInst.setOpcode(Opcode);
150 TmpInst.addOperand(MCOperand::createReg(Reg0));
151 TmpInst.setLoc(IDLoc);
152 getStreamer().EmitInstruction(TmpInst, *STI);
155 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
156 SMLoc IDLoc, const MCSubtargetInfo *STI) {
158 TmpInst.setOpcode(Opcode);
159 TmpInst.addOperand(MCOperand::createReg(Reg0));
160 TmpInst.addOperand(Op1);
161 TmpInst.setLoc(IDLoc);
162 getStreamer().EmitInstruction(TmpInst, *STI);
165 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
166 SMLoc IDLoc, const MCSubtargetInfo *STI) {
167 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
171 SMLoc IDLoc, const MCSubtargetInfo *STI) {
172 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
175 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
176 SMLoc IDLoc, const MCSubtargetInfo *STI) {
178 TmpInst.setOpcode(Opcode);
179 TmpInst.addOperand(MCOperand::createImm(Imm1));
180 TmpInst.addOperand(MCOperand::createImm(Imm2));
181 TmpInst.setLoc(IDLoc);
182 getStreamer().EmitInstruction(TmpInst, *STI);
185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
186 MCOperand Op2, SMLoc IDLoc,
187 const MCSubtargetInfo *STI) {
189 TmpInst.setOpcode(Opcode);
190 TmpInst.addOperand(MCOperand::createReg(Reg0));
191 TmpInst.addOperand(MCOperand::createReg(Reg1));
192 TmpInst.addOperand(Op2);
193 TmpInst.setLoc(IDLoc);
194 getStreamer().EmitInstruction(TmpInst, *STI);
197 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
198 unsigned Reg2, SMLoc IDLoc,
199 const MCSubtargetInfo *STI) {
200 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
203 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
204 int16_t Imm, SMLoc IDLoc,
205 const MCSubtargetInfo *STI) {
206 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
209 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
210 unsigned Reg1, int16_t Imm0, int16_t Imm1,
211 int16_t Imm2, SMLoc IDLoc,
212 const MCSubtargetInfo *STI) {
214 TmpInst.setOpcode(Opcode);
215 TmpInst.addOperand(MCOperand::createReg(Reg0));
216 TmpInst.addOperand(MCOperand::createReg(Reg1));
217 TmpInst.addOperand(MCOperand::createImm(Imm0));
218 TmpInst.addOperand(MCOperand::createImm(Imm1));
219 TmpInst.addOperand(MCOperand::createImm(Imm2));
220 TmpInst.setLoc(IDLoc);
221 getStreamer().EmitInstruction(TmpInst, *STI);
224 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
225 unsigned TrgReg, bool Is64Bit,
226 const MCSubtargetInfo *STI) {
227 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
231 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
232 int16_t ShiftAmount, SMLoc IDLoc,
233 const MCSubtargetInfo *STI) {
234 if (ShiftAmount >= 32) {
235 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
239 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
242 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
243 const MCSubtargetInfo *STI) {
244 if (hasShortDelaySlot)
245 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
247 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
250 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
251 const FeatureBitset &Features = STI->getFeatureBits();
252 if (Features[Mips::FeatureMicroMips])
253 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
255 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
258 /// Emit the $gp restore operation for .cprestore.
259 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
260 const MCSubtargetInfo *STI) {
261 emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
265 /// Emit a store instruction with an immediate offset.
266 void MipsTargetStreamer::emitStoreWithImmOffset(
267 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
268 function_ref<unsigned()> GetATReg, SMLoc IDLoc,
269 const MCSubtargetInfo *STI) {
270 if (isInt<16>(Offset)) {
271 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
275 // sw $8, offset($8) => lui $at, %hi(offset)
277 // sw $8, %lo(offset)($at)
279 unsigned ATReg = GetATReg();
283 unsigned LoOffset = Offset & 0x0000ffff;
284 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
286 // If msb of LoOffset is 1(negative number) we must increment HiOffset
287 // to account for the sign-extension of the low part.
288 if (LoOffset & 0x8000)
291 // Generate the base address in ATReg.
292 emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
293 if (BaseReg != Mips::ZERO)
294 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
295 // Emit the store with the adjusted base and offset.
296 emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
299 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
300 /// out of range for a simm16 will be expanded to appropriate instructions.
301 void MipsTargetStreamer::emitStoreWithSymOffset(
302 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
303 MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
304 const MCSubtargetInfo *STI) {
305 // sw $8, sym => lui $at, %hi(sym)
306 // sw $8, %lo(sym)($at)
308 // Generate the base address in ATReg.
309 emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
310 if (BaseReg != Mips::ZERO)
311 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
312 // Emit the store with the adjusted base and offset.
313 emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
316 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
317 /// permitted to be the same register iff DstReg is distinct from BaseReg and
318 /// DstReg is a GPR. It is the callers responsibility to identify such cases
319 /// and pass the appropriate register in TmpReg.
320 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
321 unsigned BaseReg, int64_t Offset,
322 unsigned TmpReg, SMLoc IDLoc,
323 const MCSubtargetInfo *STI) {
324 if (isInt<16>(Offset)) {
325 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
329 // 1) lw $8, offset($9) => lui $8, %hi(offset)
331 // lw $8, %lo(offset)($9)
332 // 2) lw $8, offset($8) => lui $at, %hi(offset)
334 // lw $8, %lo(offset)($at)
336 unsigned LoOffset = Offset & 0x0000ffff;
337 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
339 // If msb of LoOffset is 1(negative number) we must increment HiOffset
340 // to account for the sign-extension of the low part.
341 if (LoOffset & 0x8000)
344 // Generate the base address in TmpReg.
345 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
346 if (BaseReg != Mips::ZERO)
347 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
348 // Emit the load with the adjusted base and offset.
349 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
352 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
353 /// out of range for a simm16 will be expanded to appropriate instructions.
354 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
355 /// GPR. It is the callers responsibility to identify such cases and pass the
356 /// appropriate register in TmpReg.
357 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
359 MCOperand &HiOperand,
360 MCOperand &LoOperand,
361 unsigned TmpReg, SMLoc IDLoc,
362 const MCSubtargetInfo *STI) {
363 // 1) lw $8, sym => lui $8, %hi(sym)
364 // lw $8, %lo(sym)($8)
365 // 2) ldc1 $f0, sym => lui $at, %hi(sym)
366 // ldc1 $f0, %lo(sym)($at)
368 // Generate the base address in TmpReg.
369 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
370 if (BaseReg != Mips::ZERO)
371 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
372 // Emit the load with the adjusted base and offset.
373 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
376 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
377 formatted_raw_ostream &OS)
378 : MipsTargetStreamer(S), OS(OS) {}
380 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
381 OS << "\t.set\tmicromips\n";
382 forbidModuleDirective();
385 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
386 OS << "\t.set\tnomicromips\n";
387 forbidModuleDirective();
390 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
391 OS << "\t.set\tmips16\n";
392 forbidModuleDirective();
395 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
396 OS << "\t.set\tnomips16\n";
397 MipsTargetStreamer::emitDirectiveSetNoMips16();
400 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
401 OS << "\t.set\treorder\n";
402 MipsTargetStreamer::emitDirectiveSetReorder();
405 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
406 OS << "\t.set\tnoreorder\n";
407 forbidModuleDirective();
410 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
411 OS << "\t.set\tmacro\n";
412 MipsTargetStreamer::emitDirectiveSetMacro();
415 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
416 OS << "\t.set\tnomacro\n";
417 MipsTargetStreamer::emitDirectiveSetNoMacro();
420 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
421 OS << "\t.set\tmsa\n";
422 MipsTargetStreamer::emitDirectiveSetMsa();
425 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
426 OS << "\t.set\tnomsa\n";
427 MipsTargetStreamer::emitDirectiveSetNoMsa();
430 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
431 OS << "\t.set\tmt\n";
432 MipsTargetStreamer::emitDirectiveSetMt();
435 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
436 OS << "\t.set\tnomt\n";
437 MipsTargetStreamer::emitDirectiveSetNoMt();
440 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
441 OS << "\t.set\tcrc\n";
442 MipsTargetStreamer::emitDirectiveSetCRC();
445 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
446 OS << "\t.set\tnocrc\n";
447 MipsTargetStreamer::emitDirectiveSetNoCRC();
450 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
451 OS << "\t.set\tvirt\n";
452 MipsTargetStreamer::emitDirectiveSetVirt();
455 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
456 OS << "\t.set\tnovirt\n";
457 MipsTargetStreamer::emitDirectiveSetNoVirt();
460 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
461 OS << "\t.set\tginv\n";
462 MipsTargetStreamer::emitDirectiveSetGINV();
465 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
466 OS << "\t.set\tnoginv\n";
467 MipsTargetStreamer::emitDirectiveSetNoGINV();
470 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
471 OS << "\t.set\tat\n";
472 MipsTargetStreamer::emitDirectiveSetAt();
475 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
476 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
477 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
480 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
481 OS << "\t.set\tnoat\n";
482 MipsTargetStreamer::emitDirectiveSetNoAt();
485 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
486 OS << "\t.end\t" << Name << '\n';
489 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
490 OS << "\t.ent\t" << Symbol.getName() << '\n';
493 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
495 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
497 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
498 OS << "\t.nan\tlegacy\n";
501 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
502 OS << "\t.option\tpic0\n";
505 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
506 OS << "\t.option\tpic2\n";
509 void MipsTargetAsmStreamer::emitDirectiveInsn() {
510 MipsTargetStreamer::emitDirectiveInsn();
514 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
515 unsigned ReturnReg) {
517 << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
519 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
522 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
523 OS << "\t.set arch=" << Arch << "\n";
524 MipsTargetStreamer::emitDirectiveSetArch(Arch);
527 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
528 OS << "\t.set\tmips0\n";
529 MipsTargetStreamer::emitDirectiveSetMips0();
532 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
533 OS << "\t.set\tmips1\n";
534 MipsTargetStreamer::emitDirectiveSetMips1();
537 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
538 OS << "\t.set\tmips2\n";
539 MipsTargetStreamer::emitDirectiveSetMips2();
542 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
543 OS << "\t.set\tmips3\n";
544 MipsTargetStreamer::emitDirectiveSetMips3();
547 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
548 OS << "\t.set\tmips4\n";
549 MipsTargetStreamer::emitDirectiveSetMips4();
552 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
553 OS << "\t.set\tmips5\n";
554 MipsTargetStreamer::emitDirectiveSetMips5();
557 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
558 OS << "\t.set\tmips32\n";
559 MipsTargetStreamer::emitDirectiveSetMips32();
562 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
563 OS << "\t.set\tmips32r2\n";
564 MipsTargetStreamer::emitDirectiveSetMips32R2();
567 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
568 OS << "\t.set\tmips32r3\n";
569 MipsTargetStreamer::emitDirectiveSetMips32R3();
572 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
573 OS << "\t.set\tmips32r5\n";
574 MipsTargetStreamer::emitDirectiveSetMips32R5();
577 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
578 OS << "\t.set\tmips32r6\n";
579 MipsTargetStreamer::emitDirectiveSetMips32R6();
582 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
583 OS << "\t.set\tmips64\n";
584 MipsTargetStreamer::emitDirectiveSetMips64();
587 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
588 OS << "\t.set\tmips64r2\n";
589 MipsTargetStreamer::emitDirectiveSetMips64R2();
592 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
593 OS << "\t.set\tmips64r3\n";
594 MipsTargetStreamer::emitDirectiveSetMips64R3();
597 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
598 OS << "\t.set\tmips64r5\n";
599 MipsTargetStreamer::emitDirectiveSetMips64R5();
602 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
603 OS << "\t.set\tmips64r6\n";
604 MipsTargetStreamer::emitDirectiveSetMips64R6();
607 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
608 OS << "\t.set\tdsp\n";
609 MipsTargetStreamer::emitDirectiveSetDsp();
612 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
613 OS << "\t.set\tdspr2\n";
614 MipsTargetStreamer::emitDirectiveSetDspr2();
617 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
618 OS << "\t.set\tnodsp\n";
619 MipsTargetStreamer::emitDirectiveSetNoDsp();
622 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
623 OS << "\t.set\tpop\n";
624 MipsTargetStreamer::emitDirectiveSetPop();
627 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
628 OS << "\t.set\tpush\n";
629 MipsTargetStreamer::emitDirectiveSetPush();
632 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
633 OS << "\t.set\tsoftfloat\n";
634 MipsTargetStreamer::emitDirectiveSetSoftFloat();
637 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
638 OS << "\t.set\thardfloat\n";
639 MipsTargetStreamer::emitDirectiveSetHardFloat();
642 // Print a 32 bit hex number with all numbers.
643 static void printHex32(unsigned Value, raw_ostream &OS) {
645 for (int i = 7; i >= 0; i--)
646 OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
649 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
650 int CPUTopSavedRegOff) {
652 printHex32(CPUBitmask, OS);
653 OS << ',' << CPUTopSavedRegOff << '\n';
656 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
657 int FPUTopSavedRegOff) {
659 printHex32(FPUBitmask, OS);
660 OS << "," << FPUTopSavedRegOff << '\n';
663 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
665 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
666 forbidModuleDirective();
669 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
670 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
671 const MCSubtargetInfo *STI) {
672 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
673 OS << "\t.cprestore\t" << Offset << "\n";
677 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
681 OS << "\t.cpsetup\t$"
682 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
686 << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
693 forbidModuleDirective();
696 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
697 bool SaveLocationIsRegister) {
699 forbidModuleDirective();
702 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
703 OS << "\t.module\tfp=";
704 OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
707 void MipsTargetAsmStreamer::emitDirectiveSetFp(
708 MipsABIFlagsSection::FpABIKind Value) {
709 MipsTargetStreamer::emitDirectiveSetFp(Value);
712 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
715 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
716 MipsTargetStreamer::emitDirectiveModuleOddSPReg();
718 OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
721 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
722 MipsTargetStreamer::emitDirectiveSetOddSPReg();
723 OS << "\t.set\toddspreg\n";
726 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
727 MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
728 OS << "\t.set\tnooddspreg\n";
731 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
732 OS << "\t.module\tsoftfloat\n";
735 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
736 OS << "\t.module\thardfloat\n";
739 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
740 OS << "\t.module\tmt\n";
743 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
744 OS << "\t.module\tcrc\n";
747 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
748 OS << "\t.module\tnocrc\n";
751 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
752 OS << "\t.module\tvirt\n";
755 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
756 OS << "\t.module\tnovirt\n";
759 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
760 OS << "\t.module\tginv\n";
763 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
764 OS << "\t.module\tnoginv\n";
767 // This part is for ELF object output.
768 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
769 const MCSubtargetInfo &STI)
770 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
771 MCAssembler &MCA = getStreamer().getAssembler();
773 // It's possible that MCObjectFileInfo isn't fully initialized at this point
774 // due to an initialization order problem where LLVMTargetMachine creates the
775 // target streamer before TargetLoweringObjectFile calls
776 // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
777 // covers all cases so this statement covers most cases and direct object
778 // emission must call setPic() once MCObjectFileInfo has been initialized. The
779 // cases we don't handle here are covered by MipsAsmPrinter.
780 Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
782 const FeatureBitset &Features = STI.getFeatureBits();
784 // Set the header flags that we can in the constructor.
785 // FIXME: This is a fairly terrible hack. We set the rest
786 // of these in the destructor. The problem here is two-fold:
788 // a: Some of the eflags can be set/reset by directives.
789 // b: There aren't any usage paths that initialize the ABI
790 // pointer until after we initialize either an assembler
791 // or the target machine.
792 // We can fix this by making the target streamer construct
793 // the ABI, but this is fraught with wide ranging dependency
795 unsigned EFlags = MCA.getELFHeaderEFlags();
797 // FIXME: Fix a dependency issue by instantiating the ABI object to some
798 // default based off the triple. The triple doesn't describe the target
799 // fully, but any external user of the API that uses the MCTargetStreamer
800 // would otherwise crash on assertion failure.
803 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
804 STI.getTargetTriple().getArch() == Triple::ArchType::mips
806 : MipsABIInfo::N64());
809 if (Features[Mips::FeatureMips64r6])
810 EFlags |= ELF::EF_MIPS_ARCH_64R6;
811 else if (Features[Mips::FeatureMips64r2] ||
812 Features[Mips::FeatureMips64r3] ||
813 Features[Mips::FeatureMips64r5])
814 EFlags |= ELF::EF_MIPS_ARCH_64R2;
815 else if (Features[Mips::FeatureMips64])
816 EFlags |= ELF::EF_MIPS_ARCH_64;
817 else if (Features[Mips::FeatureMips5])
818 EFlags |= ELF::EF_MIPS_ARCH_5;
819 else if (Features[Mips::FeatureMips4])
820 EFlags |= ELF::EF_MIPS_ARCH_4;
821 else if (Features[Mips::FeatureMips3])
822 EFlags |= ELF::EF_MIPS_ARCH_3;
823 else if (Features[Mips::FeatureMips32r6])
824 EFlags |= ELF::EF_MIPS_ARCH_32R6;
825 else if (Features[Mips::FeatureMips32r2] ||
826 Features[Mips::FeatureMips32r3] ||
827 Features[Mips::FeatureMips32r5])
828 EFlags |= ELF::EF_MIPS_ARCH_32R2;
829 else if (Features[Mips::FeatureMips32])
830 EFlags |= ELF::EF_MIPS_ARCH_32;
831 else if (Features[Mips::FeatureMips2])
832 EFlags |= ELF::EF_MIPS_ARCH_2;
834 EFlags |= ELF::EF_MIPS_ARCH_1;
837 if (Features[Mips::FeatureCnMips])
838 EFlags |= ELF::EF_MIPS_MACH_OCTEON;
841 if (Features[Mips::FeatureNaN2008])
842 EFlags |= ELF::EF_MIPS_NAN2008;
844 MCA.setELFHeaderEFlags(EFlags);
847 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
848 auto *Symbol = cast<MCSymbolELF>(S);
849 getStreamer().getAssembler().registerSymbol(*Symbol);
850 uint8_t Type = Symbol->getType();
851 if (Type != ELF::STT_FUNC)
854 if (isMicroMipsEnabled())
855 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
858 void MipsTargetELFStreamer::finish() {
859 MCAssembler &MCA = getStreamer().getAssembler();
860 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
862 // .bss, .text and .data are always at least 16-byte aligned.
863 MCSection &TextSection = *OFI.getTextSection();
864 MCA.registerSection(TextSection);
865 MCSection &DataSection = *OFI.getDataSection();
866 MCA.registerSection(DataSection);
867 MCSection &BSSSection = *OFI.getBSSSection();
868 MCA.registerSection(BSSSection);
870 TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
871 DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
872 BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
874 if (RoundSectionSizes) {
875 // Make sections sizes a multiple of the alignment. This is useful for
876 // verifying the output of IAS against the output of other assemblers but
877 // it's not necessary to produce a correct object and increases section
879 MCStreamer &OS = getStreamer();
880 for (MCSection &S : MCA) {
881 MCSectionELF &Section = static_cast<MCSectionELF &>(S);
883 unsigned Alignment = Section.getAlignment();
885 OS.SwitchSection(&Section);
886 if (Section.UseCodeAlign())
887 OS.EmitCodeAlignment(Alignment, Alignment);
889 OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
894 const FeatureBitset &Features = STI.getFeatureBits();
896 // Update e_header flags. See the FIXME and comment above in
897 // the constructor for a full rundown on this.
898 unsigned EFlags = MCA.getELFHeaderEFlags();
901 // N64 does not require any ABI bits.
902 if (getABI().IsO32())
903 EFlags |= ELF::EF_MIPS_ABI_O32;
904 else if (getABI().IsN32())
905 EFlags |= ELF::EF_MIPS_ABI2;
907 if (Features[Mips::FeatureGP64Bit]) {
908 if (getABI().IsO32())
909 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
910 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
911 EFlags |= ELF::EF_MIPS_32BITMODE;
913 // -mplt is not implemented but we should act as if it was
915 if (!Features[Mips::FeatureNoABICalls])
916 EFlags |= ELF::EF_MIPS_CPIC;
919 EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
921 MCA.setELFHeaderEFlags(EFlags);
923 // Emit all the option records.
924 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
926 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
927 MEF.EmitMipsOptionRecords();
932 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
933 auto *Symbol = cast<MCSymbolELF>(S);
934 // If on rhs is micromips symbol then mark Symbol as microMips.
935 if (Value->getKind() != MCExpr::SymbolRef)
937 const auto &RhsSym = cast<MCSymbolELF>(
938 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
940 if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
943 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
946 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
947 return static_cast<MCELFStreamer &>(Streamer);
950 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
951 MicroMipsEnabled = true;
952 forbidModuleDirective();
955 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
956 MicroMipsEnabled = false;
957 forbidModuleDirective();
960 void MipsTargetELFStreamer::setUsesMicroMips() {
961 MCAssembler &MCA = getStreamer().getAssembler();
962 unsigned Flags = MCA.getELFHeaderEFlags();
963 Flags |= ELF::EF_MIPS_MICROMIPS;
964 MCA.setELFHeaderEFlags(Flags);
967 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
968 MCAssembler &MCA = getStreamer().getAssembler();
969 unsigned Flags = MCA.getELFHeaderEFlags();
970 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
971 MCA.setELFHeaderEFlags(Flags);
972 forbidModuleDirective();
975 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
976 MCAssembler &MCA = getStreamer().getAssembler();
977 unsigned Flags = MCA.getELFHeaderEFlags();
978 Flags |= ELF::EF_MIPS_NOREORDER;
979 MCA.setELFHeaderEFlags(Flags);
980 forbidModuleDirective();
983 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
984 MCAssembler &MCA = getStreamer().getAssembler();
985 MCContext &Context = MCA.getContext();
986 MCStreamer &OS = getStreamer();
988 MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
990 MCSymbol *Sym = Context.getOrCreateSymbol(Name);
991 const MCSymbolRefExpr *ExprRef =
992 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
994 MCA.registerSection(*Sec);
995 Sec->setAlignment(4);
999 OS.SwitchSection(Sec);
1001 OS.EmitValueImpl(ExprRef, 4);
1003 OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1004 OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
1006 OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1007 OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
1009 OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1010 OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
1011 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
1013 // The .end directive marks the end of a procedure. Invalidate
1014 // the information gathered up until this point.
1015 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1019 // .end also implicitly sets the size.
1020 MCSymbol *CurPCSym = Context.createTempSymbol();
1021 OS.EmitLabel(CurPCSym);
1022 const MCExpr *Size = MCBinaryExpr::createSub(
1023 MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1026 // The ELFObjectWriter can determine the absolute size as it has access to
1027 // the layout information of the assembly file, so a size expression rather
1028 // than an absolute value is ok here.
1029 static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1032 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1033 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1035 // .ent also acts like an implicit '.type symbol, STT_FUNC'
1036 static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1039 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1040 MCAssembler &MCA = getStreamer().getAssembler();
1041 unsigned Flags = MCA.getELFHeaderEFlags();
1042 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1043 MCA.setELFHeaderEFlags(Flags);
1046 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1047 MCAssembler &MCA = getStreamer().getAssembler();
1048 unsigned Flags = MCA.getELFHeaderEFlags();
1049 Flags |= ELF::EF_MIPS_NAN2008;
1050 MCA.setELFHeaderEFlags(Flags);
1053 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1054 MCAssembler &MCA = getStreamer().getAssembler();
1055 unsigned Flags = MCA.getELFHeaderEFlags();
1056 Flags &= ~ELF::EF_MIPS_NAN2008;
1057 MCA.setELFHeaderEFlags(Flags);
1060 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1061 MCAssembler &MCA = getStreamer().getAssembler();
1062 unsigned Flags = MCA.getELFHeaderEFlags();
1063 // This option overrides other PIC options like -KPIC.
1065 Flags &= ~ELF::EF_MIPS_PIC;
1066 MCA.setELFHeaderEFlags(Flags);
1069 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1070 MCAssembler &MCA = getStreamer().getAssembler();
1071 unsigned Flags = MCA.getELFHeaderEFlags();
1073 // NOTE: We are following the GAS behaviour here which means the directive
1074 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1075 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1076 // EF_MIPS_CPIC to be mutually exclusive.
1077 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1078 MCA.setELFHeaderEFlags(Flags);
1081 void MipsTargetELFStreamer::emitDirectiveInsn() {
1082 MipsTargetStreamer::emitDirectiveInsn();
1083 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1084 MEF.createPendingLabelRelocs();
1087 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1088 unsigned ReturnReg_) {
1089 MCContext &Context = getStreamer().getAssembler().getContext();
1090 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1092 FrameInfoSet = true;
1093 FrameReg = RegInfo->getEncodingValue(StackReg);
1094 FrameOffset = StackSize;
1095 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1098 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1099 int CPUTopSavedRegOff) {
1101 GPRBitMask = CPUBitmask;
1102 GPROffset = CPUTopSavedRegOff;
1105 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1106 int FPUTopSavedRegOff) {
1108 FPRBitMask = FPUBitmask;
1109 FPROffset = FPUTopSavedRegOff;
1112 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1114 // This directive expands to:
1115 // lui $gp, %hi(_gp_disp)
1116 // addui $gp, $gp, %lo(_gp_disp)
1117 // addu $gp, $gp, $reg
1118 // when support for position independent code is enabled.
1119 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1122 // There's a GNU extension controlled by -mno-shared that allows
1123 // locally-binding symbols to be accessed using absolute addresses.
1124 // This is currently not supported. When supported -mno-shared makes
1125 // .cpload expand to:
1126 // lui $gp, %hi(__gnu_local_gp)
1127 // addiu $gp, $gp, %lo(__gnu_local_gp)
1129 StringRef SymName("_gp_disp");
1130 MCAssembler &MCA = getStreamer().getAssembler();
1131 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1132 MCA.registerSymbol(*GP_Disp);
1135 TmpInst.setOpcode(Mips::LUi);
1136 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1137 const MCExpr *HiSym = MipsMCExpr::create(
1139 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1142 TmpInst.addOperand(MCOperand::createExpr(HiSym));
1143 getStreamer().EmitInstruction(TmpInst, STI);
1147 TmpInst.setOpcode(Mips::ADDiu);
1148 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1149 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1150 const MCExpr *LoSym = MipsMCExpr::create(
1152 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1155 TmpInst.addOperand(MCOperand::createExpr(LoSym));
1156 getStreamer().EmitInstruction(TmpInst, STI);
1160 TmpInst.setOpcode(Mips::ADDu);
1161 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1162 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1163 TmpInst.addOperand(MCOperand::createReg(RegNo));
1164 getStreamer().EmitInstruction(TmpInst, STI);
1166 forbidModuleDirective();
1169 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1170 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1171 const MCSubtargetInfo *STI) {
1172 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1173 // .cprestore offset
1174 // When PIC mode is enabled and the O32 ABI is used, this directive expands
1176 // sw $gp, offset($sp)
1177 // and adds a corresponding LW after every JAL.
1179 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1180 // is used in non-PIC mode.
1181 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1184 // Store the $gp on the stack.
1185 emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1190 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1192 const MCSymbol &Sym,
1194 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1195 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1198 forbidModuleDirective();
1200 MCAssembler &MCA = getStreamer().getAssembler();
1203 // Either store the old $gp in a register or on the stack
1205 // move $save, $gpreg
1206 emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1208 // sd $gpreg, offset($sp)
1209 emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1212 if (getABI().IsN32()) {
1213 MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1214 const MipsMCExpr *HiExpr = MipsMCExpr::create(
1215 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1217 const MipsMCExpr *LoExpr = MipsMCExpr::create(
1218 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1221 // lui $gp, %hi(__gnu_local_gp)
1222 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1224 // addiu $gp, $gp, %lo(__gnu_local_gp)
1225 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1231 const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1232 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1234 const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1235 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1238 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1239 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1241 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1242 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1245 // daddu $gp, $gp, $funcreg
1246 emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1249 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1250 bool SaveLocationIsRegister) {
1251 // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1252 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1256 // Either restore the old $gp from a register or on the stack
1257 if (SaveLocationIsRegister) {
1258 Inst.setOpcode(Mips::OR);
1259 Inst.addOperand(MCOperand::createReg(Mips::GP));
1260 Inst.addOperand(MCOperand::createReg(SaveLocation));
1261 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1263 Inst.setOpcode(Mips::LD);
1264 Inst.addOperand(MCOperand::createReg(Mips::GP));
1265 Inst.addOperand(MCOperand::createReg(Mips::SP));
1266 Inst.addOperand(MCOperand::createImm(SaveLocation));
1268 getStreamer().EmitInstruction(Inst, STI);
1270 forbidModuleDirective();
1273 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1274 MCAssembler &MCA = getStreamer().getAssembler();
1275 MCContext &Context = MCA.getContext();
1276 MCStreamer &OS = getStreamer();
1277 MCSectionELF *Sec = Context.getELFSection(
1278 ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1279 MCA.registerSection(*Sec);
1280 Sec->setAlignment(8);
1281 OS.SwitchSection(Sec);
1283 OS << ABIFlagsSection;