1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
17 string DecoderNamespace = "MicroMipsR6";
20 // Class used for microMIPS32r6 instructions.
21 class MicroMipsR6Inst16 : PredicateControl {
22 string DecoderNamespace = "MicroMipsR6";
23 let InsnPredicates = [HasMicroMips32r6];
26 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 // Some encodings are ambiguous except by comparing field values.
34 class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {
35 string DecoderNamespace = "MicroMipsR6_Ambiguous";
38 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 class BC16_FM_MM16R6 {
49 let Inst{15-10} = 0x33;
50 let Inst{9-0} = offset;
53 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
61 let Inst{6-0} = offset;
64 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
69 let Inst{15-10} = 0x11;
74 class POP35_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
81 let Inst{31-26} = 0b011101;
84 let Inst{15-0} = offset;
87 class POP37_BNVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
94 let Inst{31-26} = 0b011111;
97 let Inst{15-0} = offset;
100 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
105 let Inst{15-10} = 0x11;
110 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
116 let Inst{15-10} = 0x11;
118 let Inst{7-4} = addr;
119 let Inst{3-0} = funct;
122 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
128 let Inst{31-26} = 0b000000;
129 let Inst{25-21} = rt;
130 let Inst{20-16} = rd;
131 let Inst{15-12} = 0b0000;
132 let Inst{11-6} = funct;
133 let Inst{5-0} = 0b111100;
136 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
142 let Inst{31-26} = opgroup;
143 let Inst{25-21} = hint;
144 let Inst{20-16} = addr{20-16};
145 let Inst{15-12} = funct;
146 let Inst{11-0} = addr{11-0};
149 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
157 let Inst{25-21} = rt;
158 let Inst{20-16} = rs;
159 let Inst{15-11} = rd;
161 let Inst{9-0} = funct;
164 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
171 let Inst{31-26} = op;
172 let Inst{25-21} = rt;
173 let Inst{20-16} = rs;
174 let Inst{15-0} = imm16;
177 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
180 bits<5> base = addr{20-16};
181 bits<9> offset = addr{8-0};
185 let Inst{31-26} = op;
186 let Inst{25-21} = hint;
187 let Inst{20-16} = base;
188 let Inst{15-12} = 0b1010;
189 let Inst{11-9} = funct;
190 let Inst{8-0} = offset;
193 class LB32_FM_MMR6 : MipsR6Inst {
196 bits<5> base = addr{20-16};
197 bits<16> offset = addr{15-0};
201 let Inst{31-26} = 0b000111;
202 let Inst{25-21} = rt;
203 let Inst{20-16} = base;
204 let Inst{15-0} = offset;
207 class LBU32_FM_MMR6 : MipsR6Inst {
210 bits<5> base = addr{20-16};
211 bits<16> offset = addr{15-0};
215 let Inst{31-26} = 0b000101;
216 let Inst{25-21} = rt;
217 let Inst{20-16} = base;
218 let Inst{15-0} = offset;
221 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
227 let Inst{31-26} = 0b011000;
228 let Inst{25-21} = rt;
229 let Inst{20-16} = addr{20-16};
230 let Inst{15-12} = 0b0110;
231 let Inst{11-9} = funct;
232 let Inst{8-0} = addr{8-0};
235 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
236 : MMR6Arch<instr_asm> {
242 let Inst{31-26} = 0b000000;
243 let Inst{25-21} = rd;
244 let Inst{20-16} = rt;
245 let Inst{15-6} = funct;
246 let Inst{5-0} = 0b111100;
249 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
255 let Inst{31-26} = 0b011110;
256 let Inst{25-21} = rt;
257 let Inst{20-19} = funct;
258 let Inst{18-0} = imm;
261 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
267 let Inst{31-26} = 0b011110;
268 let Inst{25-21} = rt;
269 let Inst{20-16} = funct;
270 let Inst{15-0} = imm;
273 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
280 let Inst{31-26} = 0b000000;
281 let Inst{25-21} = rt;
282 let Inst{20-16} = rs;
283 let Inst{15-11} = rd;
285 let Inst{9-0} = funct;
288 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
294 let Inst{15-11} = op;
299 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
305 let Inst{25-21} = rt;
306 let Inst{20-16} = rd;
307 let Inst{15-6} = funct;
308 let Inst{5-0} = 0b111100;
311 class POOL32A_RDHWR_FM_MMR6 {
318 let Inst{25-21} = rt;
319 let Inst{20-16} = rs;
321 let Inst{13-11} = sel;
323 let Inst{9-0} = 0b0111000000;
326 class POOL32A_SYNC_FM_MMR6 {
333 let Inst{20-16} = stype;
334 let Inst{15-6} = 0b0110101101;
335 let Inst{5-0} = 0b111100;
338 class POOL32I_SYNCI_FM_MMR6 {
340 bits<5> base = addr{20-16};
341 bits<16> immediate = addr{15-0};
345 let Inst{31-26} = 0b010000;
346 let Inst{25-21} = 0b01100;
347 let Inst{20-16} = base;
348 let Inst{15-0} = immediate;
351 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
357 let Inst{31-26} = 0b000000;
358 let Inst{25-21} = rt;
359 let Inst{20-16} = rs;
360 let Inst{15-6} = funct;
361 let Inst{5-0} = 0b111100;
364 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
370 let Inst{31-26} = 0b000000;
371 let Inst{25-21} = rs;
372 let Inst{20-16} = 0b00000;
373 let Inst{15-11} = rt;
374 let Inst{10-6} = 0b00001;
375 let Inst{5-0} = funct;
378 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
386 let Inst{31-26} = 0b000000;
387 let Inst{25-21} = rs;
388 let Inst{20-16} = rt;
389 let Inst{15-11} = rd;
391 let Inst{8-6} = 0b000;
392 let Inst{5-0} = funct;
395 class AUI_FM_MMR6 : MipsR6Inst {
402 let Inst{31-26} = 0b000100;
403 let Inst{25-21} = rt;
404 let Inst{20-16} = rs;
405 let Inst{15-0} = imm;
408 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
416 let Inst{31-26} = 0b000000;
417 let Inst{25-21} = rt;
418 let Inst{20-16} = rs;
419 let Inst{15-11} = rd;
420 let Inst{10-9} = imm2;
421 let Inst{8-6} = 0b000;
422 let Inst{5-0} = funct;
425 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
428 bits<5> base = addr{20-16};
429 bits<16> offset = addr{15-0};
433 let Inst{31-26} = op;
434 let Inst{25-21} = rt;
435 let Inst{20-16} = base;
436 let Inst{15-0} = offset;
439 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
442 bits<5> base = addr{20-16};
443 bits<9> offset = addr{8-0};
447 let Inst{31-26} = 0b011000;
448 let Inst{25-21} = rt;
449 let Inst{20-16} = base;
450 let Inst{15-12} = 0b1010;
451 let Inst{11-9} = funct;
452 let Inst{8-0} = offset;
455 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
458 bits<5> base = addr{20-16};
459 bits<9> offset = addr{8-0};
463 let Inst{31-26} = 0b011000;
464 let Inst{25-21} = rt;
465 let Inst{20-16} = base;
466 let Inst{15-12} = 0b0110;
467 let Inst{11-9} = funct;
468 let Inst{8-0} = offset;
471 class LOAD_WORD_FM_MMR6 {
474 bits<5> base = addr{20-16};
475 bits<16> offset = addr{15-0};
479 let Inst{31-26} = 0b111111;
480 let Inst{25-21} = rt;
481 let Inst{20-16} = base;
482 let Inst{15-0} = offset;
485 class LOAD_UPPER_IMM_FM_MMR6 {
491 let Inst{31-26} = 0b000100;
492 let Inst{25-21} = rt;
494 let Inst{15-0} = imm16;
497 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
498 : MMR6Arch<instr_asm>, MipsR6Inst {
504 let Inst{31-26} = funct;
505 let Inst{25-21} = rt;
506 let Inst{20-16} = 0b00000;
507 let Inst{15-0} = offset;
510 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
511 : MMR6Arch<instr_asm>, MipsR6Inst {
517 let Inst{31-26} = funct;
518 let Inst{25-21} = rt;
519 let Inst{20-16} = rt;
520 let Inst{15-0} = offset;
523 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
524 : MipsR6Inst, MMR6Arch<instr_asm> {
531 let Inst{25-21} = rt;
532 let Inst{20-16} = rs;
533 let Inst{15-6} = funct;
534 let Inst{5-0} = 0b111100;
537 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>
538 : MMR6Arch<instr_asm>, MipsR6Inst {
547 let Inst{25-21} = rt;
548 let Inst{20-16} = rs;
549 let Inst{15-11} = size;
550 let Inst{10-6} = pos;
551 let Inst{5-0} = funct;
554 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
555 : MMR6Arch<instr_asm> {
558 let Inst{31-26} = 0x00;
559 let Inst{25-16} = 0x00;
560 let Inst{15-6} = funct;
561 let Inst{5-0} = 0x3c;
564 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
567 let Inst{31-26} = 0x00;
568 let Inst{25-17} = 0x00;
569 let Inst{16-16} = 0x01;
570 let Inst{15-6} = 0x3cd;
571 let Inst{5-0} = 0x3c;
574 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
578 let Inst{31-26} = 0x0;
579 let Inst{25-16} = code_1;
580 let Inst{15-6} = code_2;
581 let Inst{5-0} = 0x07;
584 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
587 let Inst{31-26} = 0x0;
588 let Inst{25-21} = 0x0;
589 let Inst{20-16} = 0x0;
590 let Inst{15-11} = op;
591 let Inst{10-6} = 0x0;
595 class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
596 : MMR6Arch<instr_asm> {
598 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
600 let Inst{31-26} = 0x00;
601 let Inst{25-21} = 0x00;
602 let Inst{20-16} = rt;
603 let Inst{15-6} = funct;
604 let Inst{5-0} = 0x3c;
607 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
615 let Inst{25-21} = rd;
616 let Inst{20-16} = rt;
617 let Inst{15-11} = shamt;
618 let Inst{10} = rotate;
619 let Inst{9-0} = funct;
622 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
628 let Inst{31-26} = op;
629 let Inst{25-21} = rt;
630 let Inst{20-16} = addr{20-16};
631 let Inst{15-0} = addr{15-0};
634 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
635 bits<3> funct> : MMR6Arch<instr_asm> {
638 bits<5> base = addr{20-16};
639 bits<9> offset = addr{8-0};
643 let Inst{31-26} = op;
644 let Inst{25-21} = rt;
645 let Inst{20-16} = base;
646 let Inst{15-12} = fmt;
647 let Inst{11-9} = funct;
648 let Inst{8-0} = offset;
651 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
652 : MMR6Arch<instr_asm>, MipsR6Inst {
659 let Inst{31-26} = 0b010101;
660 let Inst{25-21} = ft;
661 let Inst{20-16} = fs;
662 let Inst{15-11} = fd;
665 let Inst{7-0} = funct;
668 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
669 : MMR6Arch<instr_asm>, MipsR6Inst {
676 let Inst{31-26} = 0b010101;
677 let Inst{25-21} = ft;
678 let Inst{20-16} = fs;
679 let Inst{15-11} = fd;
680 let Inst{10-9} = fmt;
681 let Inst{8-0} = funct;
684 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
685 : MMR6Arch<instr_asm>, MipsR6Inst {
691 let Inst{31-26} = 0b010101;
692 let Inst{25-21} = ft;
693 let Inst{20-16} = fs;
695 let Inst{14-13} = fmt;
696 let Inst{12-6} = funct;
697 let Inst{5-0} = 0b111011;
700 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
701 : MMR6Arch<instr_asm>, MipsR6Inst {
708 let Inst{31-26} = 0b010101;
709 let Inst{25-21} = ft;
710 let Inst{20-16} = fs;
711 let Inst{15-11} = fd;
712 let Inst{10-9} = fmt;
713 let Inst{8-0} = funct;
716 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
717 : MMR6Arch<instr_asm>, MipsR6Inst {
724 let Inst{31-26} = 0b010101;
725 let Inst{25-21} = ft;
726 let Inst{20-16} = fs;
727 let Inst{15-11} = fd;
728 let Inst{10-6} = Cond.Value;
729 let Inst{5-0} = format;
732 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
733 : MMR6Arch<instr_asm>, MipsR6Inst {
738 let Inst{31-26} = 0b010101;
739 let Inst{25-21} = ft;
740 let Inst{20-16} = fs;
743 let Inst{13-6} = funct;
744 let Inst{5-0} = 0b111011;
747 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
748 : MMR6Arch<instr_asm>, MipsR6Inst {
753 let Inst{31-26} = 0b010101;
754 let Inst{25-21} = ft;
755 let Inst{20-16} = fs;
757 let Inst{14-13} = fmt;
758 let Inst{12-6} = funct;
759 let Inst{5-0} = 0b111011;
762 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
763 : MMR6Arch<instr_asm>, MipsR6Inst {
769 let Inst{31-26} = 0b010101;
770 let Inst{25-21} = ft;
771 let Inst{20-16} = fs;
773 let Inst{14-13} = fmt;
774 let Inst{12-6} = funct;
775 let Inst{5-0} = 0b111011;
778 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
779 : MMR6Arch<instr_asm>, MipsR6Inst {
785 let Inst{31-26} = 0b010101;
786 let Inst{25-21} = ft;
787 let Inst{20-16} = fs;
790 let Inst{13-6} = funct;
791 let Inst{5-0} = 0b111011;
794 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
801 let Inst{15-10} = 0b000001;
808 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
814 let Inst{15-10} = 0b010001;
817 let Inst{3-0} = 0b0001;
820 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
826 let Inst{15-10} = 0x11;
829 let Inst{3-0} = 0b0000;
832 class POOL16C_MOVEP16_FM_MMR6 : MicroMipsR6Inst16 {
839 let Inst{15-10} = 0b010001;
840 let Inst{9-7} = dst_regs;
844 let Inst{1-0} = rs{1-0};
847 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
853 let Inst{15-10} = 0b010001;
859 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
863 let Inst{15-10} = 0b010001;
864 let Inst{9-6} = code_;
868 class POOL16A_SUBU16_FM_MMR6 {
875 let Inst{15-10} = 0b000001;
882 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
888 let Inst{31-26} = 0x00;
889 let Inst{25-21} = rt;
890 let Inst{20-16} = rs;
891 let Inst{15-6} = funct;
892 let Inst{5-0} = 0x3c;
895 class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
896 : MMR6Arch<instr_asm>, MipsR6Inst {
902 let Inst{31-26} = 0b010101;
903 let Inst{25-21} = ft;
904 let Inst{20-16} = fs;
907 let Inst{13-6} = funct;
908 let Inst{5-0} = 0b111011;
911 class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
912 : MMR6Arch<instr_asm>, MipsR6Inst {
918 let Inst{31-26} = 0b010101;
919 let Inst{25-21} = fs;
920 let Inst{20-16} = fd;
922 let Inst{10-9} = fmt;
923 let Inst{8-0} = 0b000100000;
926 class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
927 : MMR6Arch<instr_asm>, MipsR6Inst {
934 let Inst{31-26} = 0b010101;
935 let Inst{25-21} = ft;
936 let Inst{20-16} = fs;
937 let Inst{15-11} = fd;
938 let Inst{10-9} = fmt;
939 let Inst{8-0} = funct;
942 class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
943 : MMR6Arch<instr_asm>, MipsR6Inst {
949 let Inst{31-26} = 0b010101;
950 let Inst{25-21} = fs;
951 let Inst{20-16} = fd;
952 let Inst{15-11} = 0b00000;
953 let Inst{10-9} = fmt;
954 let Inst{8-0} = funct;
957 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
958 : MMR6Arch<instr_asm>, MipsR6Inst {
961 let Inst{31-26} = 0x0;
962 let Inst{25-16} = 0x0;
963 let Inst{15-6} = funct;
964 let Inst{5-0} = 0b111100;
967 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
968 : MMR6Arch<instr_asm>, MipsR6Inst {
975 let Inst{31-26} = 0b000000;
976 let Inst{25-21} = rt;
977 let Inst{20-16} = rs;
979 let Inst{13-11} = sel;
980 let Inst{10-6} = funct;
981 let Inst{5-0} = opcode;
984 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
985 : MMR6Arch<instr_asm> {
991 let Inst{31-26} = 0b010101;
992 let Inst{25-21} = rt;
993 let Inst{20-16} = fs;
995 let Inst{13-6} = funct;
996 let Inst{5-0} = 0b111011;
999 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
1000 : MMR6Arch<instr_asm>, MipsR6Inst {
1006 let Inst{31-26} = 0b000000;
1007 let Inst{25-21} = rt;
1008 let Inst{20-16} = impl;
1009 let Inst{15-6} = funct;
1010 let Inst{5-0} = 0b111100;
1013 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
1014 : MipsR6Inst, MMR6Arch<opstr> {
1021 let Inst{31-26} = funct;
1022 let Inst{25-21} = rt;
1023 let Inst{20-16} = rs;
1024 let Inst{15-0} = offset;
1027 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
1028 : MMR6Arch<instr_asm>, MipsR6Inst {
1033 let Inst{31-26} = 0b000000;
1034 let Inst{25-21} = 0b00000;
1035 let Inst{20-16} = rs;
1036 let Inst{15-6} = funct;
1037 let Inst{5-0} = 0b111100;
1040 class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
1043 bits<5> base = addr{20-16};
1044 bits<12> offset = addr{11-0};
1048 let Inst{31-26} = 0x8;
1049 let Inst{25-21} = rd;
1050 let Inst{20-16} = base;
1051 let Inst{15-12} = funct;
1052 let Inst{11-0} = offset;
1055 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
1061 let Inst{31-26} = funct;
1062 let Inst{25-21} = rs;
1063 let Inst{20-0} = offset;
1066 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
1067 : MMR6Arch<instr_asm> {
1073 let Inst{31-26} = 0b010000;
1074 let Inst{25-21} = funct;
1075 let Inst{20-16} = rt;
1076 let Inst{15-0} = offset;
1079 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
1080 : MMR6Arch<instr_asm> {
1083 bits<5> base = addr{20-16};
1084 bits<16> offset = addr{15-0};
1088 let Inst{31-26} = funct;
1089 let Inst{25-21} = ft;
1090 let Inst{20-16} = base;
1091 let Inst{15-0} = offset;
1094 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
1095 : MMR6Arch<instr_asm>, MipsR6Inst {
1098 bits<5> base = addr{20-16};
1099 bits<11> offset = addr{10-0};
1103 let Inst{31-26} = 0b001000;
1104 let Inst{25-21} = rt;
1105 let Inst{20-16} = base;
1106 let Inst{15-12} = funct;
1108 let Inst{10-0} = offset;