contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def brtarget21_mm : Operand<OtherVT> {
  15   let EncoderMethod = "getBranchTarget21OpValueMM";
  16   let OperandType = "OPERAND_PCREL";
  17   let DecoderMethod = "DecodeBranchTarget21MM";
  18   let ParserMatchClass = MipsJumpTargetAsmOperand;
  19 }
  20
  21 def brtarget26_mm : Operand<OtherVT> {
  22   let EncoderMethod = "getBranchTarget26OpValueMM";
  23   let OperandType = "OPERAND_PCREL";
  24   let DecoderMethod = "DecodeBranchTarget26MM";
  25   let ParserMatchClass = MipsJumpTargetAsmOperand;
  26 }
  27
  28 def brtargetr6 : Operand<OtherVT> {
  29   let EncoderMethod = "getBranchTargetOpValueMMR6";
  30   let OperandType = "OPERAND_PCREL";
  31   let DecoderMethod = "DecodeBranchTargetMM";
  32   let ParserMatchClass = MipsJumpTargetAsmOperand;
  33 }
  34
  35 def brtarget_lsl2_mm : Operand<OtherVT> {
  36   let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
  37   let OperandType = "OPERAND_PCREL";
  38   // Instructions that use this operand have their decoder method
  39   // set with DecodeDisambiguates
  40   let DecoderMethod = "";
  41   let ParserMatchClass = MipsJumpTargetAsmOperand;
  42 }
  43
  44 //===----------------------------------------------------------------------===//
  45 //
  46 // Instruction Encodings
  47 //
  48 //===----------------------------------------------------------------------===//
  49 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  50 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  51 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  52 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  53 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  54 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  55 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  56 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  57 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  58 class AUI_MMR6_ENC : AUI_FM_MMR6;
  59 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  60 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  61 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  62 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  63 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  64 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  65 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  66 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
  67 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
  68 class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
  69                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
  70 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
  71                        DecodeDisambiguates<"BlezGroupBranchMMR6">;
  72 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
  73                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
  74 class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
  75                        DecodeDisambiguates<"BgtzGroupBranchMMR6">;
  76 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
  77 class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
  78 class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
  79                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  80 class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
  81                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  82 class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
  83                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  84 class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
  85                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  86 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
  87                          DecodeDisambiguates<"POP35GroupBranchMMR6">;
  88 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
  89                          DecodeDisambiguates<"POP37GroupBranchMMR6">;
  90 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
  91                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  92 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
  93                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  94 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
  95                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  96 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
  97                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  98 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  99 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
 100 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 101 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
 102 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
 103 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
 104 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
 105 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
 106 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
 107 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
 108 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
 109 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
 110 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 111 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 112 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 113 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
 114 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 115 class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
 116 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 117 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
 118 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
 119 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
 120 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
 121 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
 122 class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>;
 123 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
 124 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
 125 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
 126 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
 127 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
 128 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
 129 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
 130 class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
 131 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
 132 class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
 133 class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
 134 class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>;
 135 class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
 136 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
 137 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
 138 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
 139 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
 140 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
 141 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
 142 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
 143 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 144 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 145 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
 146 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 147 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 148 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 149 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
 150 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
 151 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
 152 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
 153 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
 154 class SWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x9>;
 155 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
 156 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
 157 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
 158 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
 159 class LB_MMR6_ENC : LB32_FM_MMR6;
 160 class LBU_MMR6_ENC : LBU32_FM_MMR6;
 161 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
 162 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
 163 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
 164 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 165 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 166 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 167 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 168 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 169 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 170 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 171 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 172 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 173 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 174 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 175 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 176 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 177 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 178 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 179 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 180 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 181 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 182 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 183 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 184 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 185 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 186 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 187 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 188 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 189 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 190 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 191 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 192 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 193 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 194 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 195 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 196 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 197 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 198 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
 199 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 200 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 201 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 202                                                        0b11001100>;
 203 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 204                                                        0b11001100>;
 205 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 206                                                        0b11101100>;
 207 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 208                                                        0b11101100>;
 209 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 210 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 211 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 212 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 213 class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
 214 class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
 215 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 216 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 217 class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
 218 class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
 219 class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
 220 class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
 221 class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
 222 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 223 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 224 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 225 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 226 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 227 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 228 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 229 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 230 class LI16_MMR6_ENC : LI_FM_MM16;
 231 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 232 class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
 233 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 234 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 235 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 236 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 237 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
 238 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
 239 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
 240 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
 241 class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
 242 class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
 243 class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
 244 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
 245 class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
 246 class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
 247 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
 248 class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
 249 class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
 250
 251 /// Floating Point Instructions
 252 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 253 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 254 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 255 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 256 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 257 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 258 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 259 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 260 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 261 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 262 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 263 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 264 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 265 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 266 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 267 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 268 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 269 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 270 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 271 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 272 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 273 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 274 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 275 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 276
 277 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 278 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 279 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 280 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 281 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 282 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 283 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 284 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 285 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 286 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 287
 288 //===----------------------------------------------------------------------===//
 289 //
 290 // Instruction Descriptions
 291 //
 292 //===----------------------------------------------------------------------===//
 293
 294 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 295                                   RegisterOperand GPROpnd>
 296     : BRANCH_DESC_BASE {
 297   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 298   dag OutOperandList = (outs);
 299   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 300   list<Register> Defs = [AT];
 301   InstrItinClass Itinerary = II_BCCZC;
 302 }
 303
 304 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 305                                                       GPR32Opnd> {
 306   list<Register> Defs = [RA];
 307 }
 308
 309 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 310                                                       GPR32Opnd> {
 311   list<Register> Defs = [RA];
 312 }
 313
 314 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 315                                                       GPR32Opnd> {
 316   list<Register> Defs = [RA];
 317 }
 318
 319 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 320                                                       GPR32Opnd> {
 321   list<Register> Defs = [RA];
 322 }
 323
 324 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 325                                                       GPR32Opnd> {
 326   list<Register> Defs = [RA];
 327 }
 328
 329 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 330                                                       GPR32Opnd> {
 331   list<Register> Defs = [RA];
 332 }
 333
 334 class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
 335                                                     GPR32Opnd>;
 336 class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
 337                                                     GPR32Opnd>;
 338 class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
 339                                                     GPR32Opnd>;
 340 class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
 341                                                     GPR32Opnd>;
 342
 343 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 344                                 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
 345   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
 346   dag OutOperandList = (outs);
 347   string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
 348   list<Register> Defs = [AT];
 349   InstrItinClass Itinerary = II_BCCC;
 350 }
 351
 352 class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
 353                                                  GPR32Opnd>;
 354 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
 355                                                  GPR32Opnd>;
 356 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
 357                                                  GPR32Opnd>;
 358 class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
 359                                                  GPR32Opnd>;
 360 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
 361                                                  GPR32Opnd>;
 362 class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
 363                                                  GPR32Opnd>;
 364
 365 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
 366 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 367 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
 368 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
 369 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
 370 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
 371 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
 372
 373 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
 374     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 375   dag InOperandList = (ins opnd:$offset);
 376   dag OutOperandList = (outs);
 377   string AsmString = !strconcat(instr_asm, "\t$offset");
 378   bit isBarrier = 1;
 379   InstrItinClass Itinerary = Itin;
 380 }
 381
 382 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
 383   bit isCall = 1;
 384   list<Register> Defs = [RA];
 385 }
 386 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
 387   list<dag> Pattern = [(br bb:$offset)];
 388 }
 389
 390 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 391                                        !strconcat("bc16", "\t$offset"), [],
 392                                        II_BC, FrmI>,
 393                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 394   let isBranch = 1;
 395   let isTerminator = 1;
 396   let isBarrier = 1;
 397   let hasDelaySlot = 0;
 398   let AdditionalPredicates = [RelocPIC];
 399   let Defs = [AT];
 400 }
 401
 402 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 403     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 404   let isBranch = 1;
 405   let isTerminator = 1;
 406   let hasDelaySlot = 0;
 407   let Defs = [AT];
 408 }
 409 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 410 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 411
 412 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
 413 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
 414
 415 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 416     : MMR6Arch<instr_asm> {
 417   dag OutOperandList = (outs GPROpnd:$rd);
 418   dag InOperandList = (ins GPROpnd:$rt);
 419   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 420   list<dag> Pattern = [];
 421   InstrItinClass Itinerary = II_BITSWAP;
 422 }
 423
 424 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 425
 426 class BRK_MMR6_DESC : BRK_FT<"break">;
 427
 428 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 429                            RegisterOperand GPROpnd, InstrItinClass Itin>
 430       : MMR6Arch<instr_asm> {
 431   dag OutOperandList = (outs);
 432   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 433   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 434   list<dag> Pattern = [];
 435   string DecoderMethod = "DecodeCacheOpMM";
 436   InstrItinClass Itinerary = Itin;
 437 }
 438
 439 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
 440                                              II_CACHE>;
 441 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
 442                                              II_PREF>;
 443
 444 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 445                                   RegisterOperand GPROpnd, InstrItinClass Itin>
 446     : CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd, Itin> {
 447   string DecoderMethod = "DecodePrefeOpMM";
 448 }
 449
 450 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9,
 451                                                     GPR32Opnd, II_PREFE>;
 452 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9,
 453                                                      GPR32Opnd, II_CACHEE>;
 454
 455 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 456                             RegisterOperand GPROpnd, InstrItinClass Itin>
 457     : MMR6Arch<instr_asm> {
 458   dag OutOperandList = (outs GPROpnd:$rt);
 459   dag InOperandList = (ins MemOpnd:$addr);
 460   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 461   string DecoderMethod = "DecodeLoadByte15";
 462   bit mayLoad = 1;
 463   InstrItinClass Itinerary = Itin;
 464 }
 465 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
 466 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
 467                                             II_LBU>;
 468
 469 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 470                               RegisterOperand GPROpnd, InstrItinClass Itin>
 471     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd, Itin> {
 472   let DecoderMethod = "DecodeLoadByte9";
 473 }
 474 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd,
 475                                               II_LBE>;
 476 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd,
 477                                                II_LBUE>;
 478
 479 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 480                              InstrItinClass Itin> : MMR6Arch<instr_asm> {
 481   dag OutOperandList = (outs GPROpnd:$rt);
 482   dag InOperandList = (ins GPROpnd:$rs);
 483   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 484   InstrItinClass Itinerary = Itin;
 485 }
 486
 487 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
 488 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
 489
 490 class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
 491 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
 492 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
 493
 494 class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
 495 class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
 496 class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
 497
 498 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 499     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 500                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 501       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 502   let isCall = 1;
 503   let hasDelaySlot = 0;
 504   let Defs = [RA];
 505 }
 506 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 507
 508 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 509                                      RegisterOperand GPROpnd,
 510                                      InstrItinClass Itin>
 511     : MMR6Arch<opstr> {
 512   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 513   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 514   list<dag> Pattern = [];
 515   bit isTerminator = 1;
 516   bit hasDelaySlot = 0;
 517   InstrItinClass Itinerary = Itin;
 518 }
 519
 520 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 521                                                        GPR32Opnd, II_JIALC> {
 522   bit isCall = 1;
 523   list<Register> Defs = [RA];
 524 }
 525
 526 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 527                                                      GPR32Opnd, II_JIC> {
 528   bit isBarrier = 1;
 529   list<Register> Defs = [AT];
 530 }
 531
 532 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 533     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 534                       [], II_JR, FrmR>,
 535       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 536   let hasDelaySlot = 0;
 537   let isBranch = 1;
 538   let isIndirectBranch = 1;
 539 }
 540 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 541
 542 class JRCADDIUSP_MMR6_DESC
 543     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 544                       [], II_JRADDIUSP, FrmR>,
 545       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
 546   let hasDelaySlot = 0;
 547   let isTerminator = 1;
 548   let isBarrier = 1;
 549   let isBranch = 1;
 550   let isIndirectBranch = 1;
 551 }
 552
 553 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 554                       Operand ImmOpnd, InstrItinClass Itin>
 555     : MMR6Arch<instr_asm> {
 556   dag OutOperandList = (outs GPROpnd:$rd);
 557   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 558   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 559   list<dag> Pattern = [];
 560   InstrItinClass Itinerary = Itin;
 561 }
 562
 563 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
 564                                              II_ALIGN>;
 565
 566 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 567                          InstrItinClass Itin> : MMR6Arch<instr_asm> {
 568   dag OutOperandList = (outs GPROpnd:$rt);
 569   dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
 570   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 571   list<dag> Pattern = [];
 572   InstrItinClass Itinerary = Itin;
 573 }
 574
 575 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
 576
 577 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 578 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 579 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 580                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
 581   dag OutOperandList = (outs GPROpnd:$rt);
 582   dag InOperandList = (ins simm16:$imm);
 583   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 584   list<dag> Pattern = [];
 585   InstrItinClass Itinerary = Itin;
 586 }
 587
 588 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
 589 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
 590
 591 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 592                          Operand ImmOpnd, InstrItinClass Itin>
 593     : MMR6Arch<instr_asm> {
 594   dag OutOperandList = (outs GPROpnd:$rd);
 595   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 596   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 597   list<dag> Pattern = [];
 598   InstrItinClass Itinerary = Itin;
 599 }
 600
 601 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
 602
 603 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 604                            Operand ImmOpnd, InstrItinClass Itin>
 605     : MMR6Arch<instr_asm> {
 606   dag OutOperandList = (outs GPROpnd:$rt);
 607   dag InOperandList = (ins ImmOpnd:$imm);
 608   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 609   list<dag> Pattern = [];
 610   InstrItinClass Itinerary = Itin;
 611 }
 612
 613 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
 614                                                simm19_lsl2, II_ADDIUPC>;
 615 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
 616                                            II_LWPC>;
 617
 618 class LWP_MMR6_DESC : MMR6Arch<"lwp"> {
 619   dag OutOperandList = (outs regpair:$rd);
 620   dag InOperandList = (ins mem_simm12:$addr);
 621   string AsmString = !strconcat("lwp", "\t$rd, $addr");
 622   list<dag> Pattern = [];
 623   InstrItinClass Itinerary = II_LWP;
 624   ComplexPattern Addr = addr;
 625   Format f = FrmI;
 626   string BaseOpcode = "lwp";
 627   string DecoderMethod = "DecodeMemMMImm12";
 628   bit mayLoad = 1;
 629 }
 630
 631 class SWP_MMR6_DESC : MMR6Arch<"swp"> {
 632   dag OutOperandList = (outs);
 633   dag InOperandList = (ins regpair:$rd, mem_simm12:$addr);
 634   string AsmString = !strconcat("swp", "\t$rd, $addr");
 635   list<dag> Pattern = [];
 636   InstrItinClass Itinerary = II_SWP;
 637   ComplexPattern Addr = addr;
 638   Format f = FrmI;
 639   string BaseOpcode = "swp";
 640   string DecoderMethod = "DecodeMemMMImm12";
 641   bit mayStore = 1;
 642 }
 643
 644 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 645                                InstrItinClass Itin> : MMR6Arch<instr_asm> {
 646   dag OutOperandList = (outs GPROpnd:$rd);
 647   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 648   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 649   list<dag> Pattern = [];
 650   InstrItinClass Itinerary = Itin;
 651 }
 652
 653 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
 654                                                   II_SELCCZ>;
 655 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
 656                                                   II_SELCCZ>;
 657 class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
 658 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 659   dag OutOperandList = (outs GPR32Opnd:$rt);
 660   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 661   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 662   list<dag> Pattern = [];
 663   InstrItinClass Itinerary = II_RDHWR;
 664   Format Form = FrmR;
 665 }
 666
 667 class WAIT_MMR6_DESC : WaitMM<"wait">;
 668 // FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
 669 //        Assemblers targeting specifically Release 6 should reject the SSNOP
 670 //        instruction with an error.
 671 class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
 672 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 673
 674 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
 675                             InstrItinClass Itin,
 676                             SDPatternOperator OpNode=null_frag>
 677     : MipsR6Inst {
 678   dag OutOperandList = (outs GPROpnd:$rd);
 679   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 680   string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
 681   list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
 682   string BaseOpcode = opstr;
 683   Format f = FrmR;
 684   let isCommutable = 0;
 685   let isReMaterializable = 1;
 686   InstrItinClass Itinerary = Itin;
 687
 688   // This instruction doesn't trap division by zero itself. We must insert
 689   // teq instructions as well.
 690   bit usesCustomInserter = 1;
 691 }
 692 class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
 693 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
 694 class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
 695 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
 696 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
 697 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
 698 class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
 699 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
 700 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
 701                                   or> {
 702   int AddedComplexity = 1;
 703 }
 704 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
 705 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
 706                                    immZExt16, xor>;
 707
 708 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 709                   InstrItinClass Itin = NoItinerary,
 710                   SDPatternOperator OpNode = null_frag,
 711                   ComplexPattern Addr = addr> :
 712   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 713          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 714   let DecoderMethod = "DecodeMem";
 715   let mayStore = 1;
 716 }
 717 class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
 718   InstrItinClass Itinerary = II_SW;
 719 }
 720 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9, II_SWE>;
 721
 722 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
 723                                  InstrItinClass Itin> : MMR6Arch<instr_asm> {
 724   dag InOperandList = (ins RO:$rs);
 725   dag OutOperandList = (outs RO:$rt);
 726   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 727   list<dag> Pattern = [];
 728   Format f = FrmR;
 729   string BaseOpcode = instr_asm;
 730   bit hasSideEffects = 0;
 731   InstrItinClass Itinerary = Itin;
 732 }
 733 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
 734                                                     II_WRPGPR>;
 735 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
 736
 737 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 738                          RegisterOperand SrcRC, InstrItinClass Itin> {
 739   dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
 740   dag OutOperandList = (outs DstRC:$rs);
 741   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 742   list<dag> Pattern = [];
 743   Format f = FrmFR;
 744   string BaseOpcode = opstr;
 745   InstrItinClass Itinerary = Itin;
 746 }
 747 class MTC1_MMR6_DESC_BASE<
 748       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 749       InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
 750       : MipsR6Inst {
 751   dag InOperandList = (ins SrcRC:$rt);
 752   dag OutOperandList = (outs DstRC:$fs);
 753   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 754   list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
 755   Format f = FrmFR;
 756   InstrItinClass Itinerary = Itin;
 757   string BaseOpcode = opstr;
 758 }
 759 class MTC1_64_MMR6_DESC_BASE<
 760       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 761       InstrItinClass Itin = NoItinerary> : MipsR6Inst {
 762   dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
 763   dag OutOperandList = (outs DstRC:$fs);
 764   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 765   list<dag> Pattern = [];
 766   Format f = FrmFR;
 767   InstrItinClass Itinerary = Itin;
 768   string BaseOpcode = opstr;
 769   // $fs_in is part of a white lie to work around a widespread bug in the FPU
 770   // implementation. See expandBuildPairF64 for details.
 771   let Constraints = "$fs = $fs_in";
 772 }
 773 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 774                          RegisterOperand SrcRC, InstrItinClass Itin> {
 775   dag InOperandList = (ins SrcRC:$rt);
 776   dag OutOperandList = (outs DstRC:$impl);
 777   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 778   list<dag> Pattern = [];
 779   Format f = FrmFR;
 780   string BaseOpcode = opstr;
 781   InstrItinClass Itinerary = Itin;
 782 }
 783
 784 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
 785                                            II_MTC0>;
 786 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
 787                                            II_MTC1, bitconvert>, HARDFLOAT;
 788 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
 789                                            II_MTC2>;
 790 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
 791                                             II_MTHC0>;
 792 class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
 793                                                    GPR32Opnd, II_MTC1>,
 794                             HARDFLOAT, FGR_32;
 795 class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd,
 796                                                    GPR32Opnd, II_MTC1>,
 797                             HARDFLOAT, FGR_64;
 798 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
 799                                             II_MTC2>;
 800
 801 class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 802                           RegisterOperand SrcRC, InstrItinClass Itin> {
 803   dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
 804   dag OutOperandList = (outs DstRC:$rt);
 805   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 806   list<dag> Pattern = [];
 807   Format f = FrmFR;
 808   string BaseOpcode = opstr;
 809   InstrItinClass Itinerary = Itin;
 810 }
 811 class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 812                           RegisterOperand SrcRC,
 813                           InstrItinClass Itin = NoItinerary,
 814                           SDPatternOperator OpNode = null_frag> : MipsR6Inst {
 815   dag InOperandList = (ins SrcRC:$fs);
 816   dag OutOperandList = (outs DstRC:$rt);
 817   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 818   list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
 819   Format f = FrmFR;
 820   InstrItinClass Itinerary = Itin;
 821   string BaseOpcode = opstr;
 822 }
 823 class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 824                           RegisterOperand SrcRC, InstrItinClass Itin> {
 825   dag InOperandList = (ins SrcRC:$impl);
 826   dag OutOperandList = (outs DstRC:$rt);
 827   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 828   list<dag> Pattern = [];
 829   Format f = FrmFR;
 830   string BaseOpcode = opstr;
 831   InstrItinClass Itinerary = Itin;
 832 }
 833 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
 834                                            II_MFC0>;
 835 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
 836                                            II_MFC1, bitconvert>, HARDFLOAT;
 837 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
 838                                            II_MFC2>;
 839 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
 840                                             II_MFHC0>;
 841 class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
 842                                                 II_MFHC1>, HARDFLOAT, FGR_32;
 843 class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
 844                                                 II_MFHC1>, HARDFLOAT, FGR_64;
 845 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
 846                                             II_MFC2>;
 847
 848 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 849   dag InOperandList = (ins mem_mm_16:$addr);
 850   dag OutOperandList = (outs FGR64Opnd:$ft);
 851   string AsmString = !strconcat("ldc1", "\t$ft, $addr");
 852   list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
 853   Format f = FrmFI;
 854   InstrItinClass Itinerary = II_LDC1;
 855   string BaseOpcode = "ldc1";
 856   bit mayLoad = 1;
 857   let DecoderMethod = "DecodeFMemMMR2";
 858 }
 859
 860 class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 861   dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
 862   dag OutOperandList = (outs);
 863   string AsmString = !strconcat("sdc1", "\t$ft, $addr");
 864   list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
 865   Format f = FrmFI;
 866   InstrItinClass Itinerary = II_SDC1;
 867   string BaseOpcode = "sdc1";
 868   bit mayStore = 1;
 869   let DecoderMethod = "DecodeFMemMMR2";
 870 }
 871
 872 class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 873   dag OutOperandList = (outs COP2Opnd:$rt);
 874   dag InOperandList = (ins mem_mm_11:$addr);
 875   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 876   list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
 877   Format f = FrmFI;
 878   InstrItinClass Itinerary = itin;
 879   string BaseOpcode = opstr;
 880   bit mayLoad = 1;
 881   string DecoderMethod = "DecodeFMemCop2MMR6";
 882 }
 883 class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
 884 class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
 885
 886 class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 887   dag OutOperandList = (outs);
 888   dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
 889   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 890   list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
 891   Format f = FrmFI;
 892   InstrItinClass Itinerary = itin;
 893   string BaseOpcode = opstr;
 894   bit mayStore = 1;
 895   string DecoderMethod = "DecodeFMemCop2MMR6";
 896 }
 897 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
 898 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
 899
 900 /// Floating Point Instructions
 901 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 902                             InstrItinClass Itin, bit isComm,
 903                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 904   dag OutOperandList = (outs RC:$fd);
 905   dag InOperandList = (ins RC:$ft, RC:$fs);
 906   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 907   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 908   InstrItinClass Itinerary = Itin;
 909   bit isCommutable = isComm;
 910 }
 911 class FADD_S_MMR6_DESC
 912   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 913 class FADD_D_MMR6_DESC
 914   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 915 class FSUB_S_MMR6_DESC
 916   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 917 class FSUB_D_MMR6_DESC
 918   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 919 class FMUL_S_MMR6_DESC
 920   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 921 class FMUL_D_MMR6_DESC
 922   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 923 class FDIV_S_MMR6_DESC
 924   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 925 class FDIV_D_MMR6_DESC
 926   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 927 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
 928                                             II_MADDF_S>, HARDFLOAT;
 929 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
 930                                             II_MADDF_D>, HARDFLOAT;
 931 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
 932                                             II_MSUBF_S>, HARDFLOAT;
 933 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
 934                                             II_MSUBF_D>, HARDFLOAT;
 935
 936 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 937                                RegisterOperand SrcRC, InstrItinClass Itin,
 938                                SDPatternOperator OpNode = null_frag>
 939                                : HARDFLOAT, NeverHasSideEffects {
 940   dag OutOperandList = (outs DstRC:$ft);
 941   dag InOperandList = (ins SrcRC:$fs);
 942   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 943   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 944   InstrItinClass Itinerary = Itin;
 945   Format Form = FrmFR;
 946 }
 947 class FMOV_S_MMR6_DESC
 948   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 949 class FMOV_D_MMR6_DESC
 950   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 951 class FNEG_S_MMR6_DESC
 952   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 953 class FNEG_D_MMR6_DESC
 954   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 955
 956 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
 957                         HARDFLOAT;
 958 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
 959                         HARDFLOAT;
 960 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
 961                         HARDFLOAT;
 962 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
 963                         HARDFLOAT;
 964
 965 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
 966                          HARDFLOAT;
 967 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
 968                          HARDFLOAT;
 969 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
 970                          HARDFLOAT;
 971 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
 972                          HARDFLOAT;
 973
 974 class CVT_MMR6_DESC_BASE<
 975     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 976     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 977     : HARDFLOAT, NeverHasSideEffects {
 978   dag OutOperandList = (outs DstRC:$ft);
 979   dag InOperandList = (ins SrcRC:$fs);
 980   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 981   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 982   InstrItinClass Itinerary = Itin;
 983   Format Form = FrmFR;
 984 }
 985
 986 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 987                                              II_CVT>;
 988 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 989                                              II_CVT>;
 990 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 991                                              II_CVT>;
 992 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 993                                              II_CVT>;
 994 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 995                                              II_CVT>;
 996 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 997                                              II_CVT>;
 998 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 999                                              II_CVT>, FGR_64;
1000 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
1001                                              II_CVT>;
1002 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
1003                                              II_CVT>;
1004 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
1005                                              II_CVT>, FGR_64;
1006
1007 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
1008                        RegisterOperand FGROpnd, InstrItinClass Itin> {
1009   def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1010       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
1011       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
1012       ISA_MICROMIPS32R6;
1013   def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1014       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
1015       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
1016       ISA_MICROMIPS32R6;
1017   def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1018       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
1019       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
1020       ISA_MICROMIPS32R6;
1021   def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1022       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
1023       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
1024       ISA_MICROMIPS32R6;
1025   def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1026       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
1027       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
1028       ISA_MICROMIPS32R6;
1029   def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1030       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
1031       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
1032       ISA_MICROMIPS32R6;
1033   def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1034       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
1035       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
1036       ISA_MICROMIPS32R6;
1037   def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1038       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
1039       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
1040       ISA_MICROMIPS32R6;
1041   def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1042       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
1043       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
1044       ISA_MICROMIPS32R6;
1045   def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1046       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
1047       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
1048       ISA_MICROMIPS32R6;
1049   def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1050       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
1051       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
1052       ISA_MICROMIPS32R6;
1053   def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1054       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
1055       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
1056       ISA_MICROMIPS32R6;
1057   def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1058       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
1059       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
1060       ISA_MICROMIPS32R6;
1061   def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1062       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
1063       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
1064       ISA_MICROMIPS32R6;
1065   def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1066       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1067       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1068       ISA_MICROMIPS32R6;
1069   def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1070       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1071       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1072       ISA_MICROMIPS32R6;
1073 }
1074
1075 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1076                              RegisterOperand SrcRC, InstrItinClass Itin,
1077                              SDPatternOperator OpNode = null_frag>
1078     : HARDFLOAT, NeverHasSideEffects {
1079   dag OutOperandList = (outs DstRC:$ft);
1080   dag InOperandList  = (ins SrcRC:$fs);
1081   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1082   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1083   InstrItinClass Itinerary = Itin;
1084   Format Form = FrmFR;
1085   list<Predicate> EncodingPredicates = [HasStdEnc];
1086 }
1087
1088 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
1089                                                 II_ABS, fabs>;
1090 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
1091                                                 II_ABS, fabs>;
1092 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1093                                                     FGR32Opnd, II_FLOOR>;
1094 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1095                                                     FGR64Opnd, II_FLOOR>;
1096 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1097                                                     FGR32Opnd, II_FLOOR>;
1098 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1099                                                     AFGR64Opnd, II_FLOOR>;
1100 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1101                                                    FGR32Opnd, II_CEIL>;
1102 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1103                                                    FGR64Opnd, II_CEIL>;
1104 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1105                                                    FGR32Opnd, II_CEIL>;
1106 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1107                                                    AFGR64Opnd, II_CEIL>;
1108 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1109                                                     FGR32Opnd, II_TRUNC>;
1110 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1111                                                     FGR64Opnd, II_TRUNC>;
1112 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1113                                                     FGR32Opnd, II_TRUNC>;
1114 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1115                                                     AFGR64Opnd, II_TRUNC>;
1116 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1117                                                  II_SQRT_S, fsqrt>;
1118 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
1119                                                  II_SQRT_D, fsqrt>;
1120 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1121                                                    FGR32Opnd, II_ROUND>;
1122 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1123                                                    FGR64Opnd, II_ROUND>;
1124 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1125                                                    FGR32Opnd, II_ROUND>;
1126 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1127                                                    FGR64Opnd, II_ROUND>;
1128
1129 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1130 class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1131
1132 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1133                                               II_SELCCZ_S>;
1134 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1135                                               II_SELCCZ_D>;
1136 class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1137                                               II_SELCCZ_S>;
1138 class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1139                                               II_SELCCZ_D>;
1140 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1141                                               II_RINT_S>;
1142 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1143                                               II_RINT_S>;
1144 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1145                                               II_CLASS_S>;
1146 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1147                                               II_CLASS_S>;
1148
1149 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1150                            InstrItinClass Itin>
1151     : Store<opstr, RO>, MMR6Arch<opstr> {
1152   let DecoderMethod = "DecodeMemMMImm16";
1153   InstrItinClass Itinerary = Itin;
1154 }
1155 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1156
1157 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
1158                                InstrItinClass Itin>
1159     : MMR6Arch<instr_asm>, MipsR6Inst {
1160   dag OutOperandList = (outs);
1161   dag InOperandList = (ins RO:$rt, mem_simm9:$addr);
1162   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
1163   string DecoderMethod = "DecodeStoreEvaOpMM";
1164   bit mayStore = 1;
1165   InstrItinClass Itinerary = Itin;
1166 }
1167 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, II_SBE>;
1168 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
1169 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1170 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, II_SHE>;
1171 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
1172                                    InstrItinClass Itin>
1173     : MMR6Arch<instr_asm>, MipsR6Inst {
1174   dag OutOperandList = (outs RO:$rt);
1175   dag InOperandList = (ins mem_simm9:$addr);
1176   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
1177   string DecoderMethod = "DecodeMemMMImm9";
1178   bit mayLoad = 1;
1179   InstrItinClass Itinerary = Itin;
1180 }
1181 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
1182 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
1183 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1184       MMR6Arch<"addu16"> {
1185   int AddedComplexity = 1;
1186 }
1187 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
1188       MMR6Arch<"and16"> {
1189   int AddedComplexity = 1;
1190 }
1191 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1192       MMR6Arch<"andi16">;
1193 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1194   int AddedComplexity = 1;
1195 }
1196 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
1197       MMR6Arch<"or16"> {
1198   int AddedComplexity = 1;
1199 }
1200 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1201       MMR6Arch<"sll16">;
1202 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1203       MMR6Arch<"srl16">;
1204 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">,
1205       MicroMipsR6Inst16;
1206 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1207       MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
1208 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
1209       MicroMipsR6Inst16;
1210 class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">;
1211 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
1212       MicroMipsR6Inst16;
1213 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1214       MMR6Arch<"subu16">, MicroMipsR6Inst16 {
1215   int AddedComplexity = 1;
1216 }
1217 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
1218       MMR6Arch<"xor16"> {
1219   int AddedComplexity = 1;
1220 }
1221
1222 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1223   dag OutOperandList = (outs GPR32Opnd:$rt);
1224   dag InOperandList = (ins mem:$addr);
1225   string AsmString = "lw\t$rt, $addr";
1226   let DecoderMethod = "DecodeMemMMImm16";
1227   let canFoldAsLoad = 1;
1228   let mayLoad = 1;
1229   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1230   InstrItinClass Itinerary = II_LW;
1231 }
1232
1233 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1234   dag OutOperandList = (outs GPR32Opnd:$rt);
1235   dag InOperandList = (ins uimm16:$imm16);
1236   string AsmString = "lui\t$rt, $imm16";
1237   list<dag> Pattern = [];
1238   bit hasSideEffects = 0;
1239   bit isReMaterializable = 1;
1240   InstrItinClass Itinerary = II_LUI;
1241   Format Form = FrmI;
1242 }
1243
1244 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1245   dag OutOperandList = (outs);
1246   dag InOperandList = (ins uimm5:$stype);
1247   string AsmString = !strconcat("sync", "\t$stype");
1248   list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1249   InstrItinClass Itinerary = II_SYNC;
1250   bit HasSideEffects = 1;
1251 }
1252
1253 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
1254   let DecoderMethod = "DecodeSynciR6";
1255 }
1256
1257 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1258   dag OutOperandList = (outs GPR32Opnd:$rt);
1259   dag InOperandList = (ins GPR32Opnd:$rd);
1260   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1261   InstrItinClass Itinerary = II_RDPGPR;
1262 }
1263
1264 class SDBBP_MMR6_DESC : MipsR6Inst {
1265   dag OutOperandList = (outs);
1266   dag InOperandList = (ins uimm20:$code_);
1267   string AsmString = !strconcat("sdbbp", "\t$code_");
1268   list<dag> Pattern = [];
1269   InstrItinClass Itinerary = II_SDBBP;
1270 }
1271
1272 class LWM16_MMR6_DESC
1273     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1274                       !strconcat("lwm16", "\t$rt, $addr"), [],
1275                       II_LWM, FrmI>,
1276       MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
1277   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1278   let mayLoad = 1;
1279   ComplexPattern Addr = addr;
1280 }
1281
1282 class SWM16_MMR6_DESC
1283     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1284                       !strconcat("swm16", "\t$rt, $addr"), [],
1285                       II_SWM, FrmI>,
1286       MMR6Arch<"swm16">, MicroMipsR6Inst16 {
1287   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1288   let mayStore = 1;
1289   ComplexPattern Addr = addr;
1290 }
1291
1292 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1293                           SDPatternOperator OpNode, InstrItinClass Itin,
1294                           Operand MemOpnd>
1295     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1296                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1297       MMR6Arch<opstr>, MicroMipsR6Inst16 {
1298   let DecoderMethod = "DecodeMemMMImm4";
1299   let mayStore = 1;
1300 }
1301 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1302                                            truncstorei8, II_SB, mem_mm_4>;
1303 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1304                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
1305 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1306                                            store, II_SW, mem_mm_4_lsl2>;
1307
1308 class SWSP_MMR6_DESC
1309     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1310                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1311       MMR6Arch<"sw">, MicroMipsR6Inst16 {
1312   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1313   let mayStore = 1;
1314 }
1315
1316 class JALRC_HB_MMR6_DESC {
1317   dag OutOperandList = (outs GPR32Opnd:$rt);
1318   dag InOperandList = (ins GPR32Opnd:$rs);
1319   string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1320   list<dag> Pattern = [];
1321   InstrItinClass Itinerary = II_JALR_HB;
1322   Format Form = FrmJ;
1323   bit isIndirectBranch = 1;
1324   bit hasDelaySlot = 0;
1325 }
1326
1327 class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1328   dag OutOperandList = (outs);
1329   dag InOperandList = (ins);
1330   string AsmString = opstr;
1331   list<dag> Pattern = [];
1332   InstrItinClass Itinerary = Itin;
1333 }
1334
1335 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1336 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1337
1338 class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1339   dag OutOperandList = (outs GPR32Opnd:$rs);
1340   dag InOperandList = (ins);
1341   string AsmString = !strconcat(opstr, "\t$rs");
1342   list<dag> Pattern = [];
1343   InstrItinClass Itinerary = Itin;
1344   bit hasUnModeledSideEffects = 1;
1345 }
1346
1347 class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1348 class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1349
1350 class BEQZC_MMR6_DESC
1351     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1352       MMR6Arch<"beqzc">;
1353 class BNEZC_MMR6_DESC
1354     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1355       MMR6Arch<"bnezc">;
1356
1357 class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1358     InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1359            !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1360     HARDFLOAT, BRANCH_DESC_BASE {
1361   list<Register> Defs = [AT];
1362 }
1363
1364 class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1365 class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1366
1367 class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1368     : BRANCH_DESC_BASE {
1369   dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1370   dag OutOperandList = (outs);
1371   string AsmString = !strconcat(opstr, "\t$rt, $offset");
1372   list<Register> Defs = [AT];
1373   InstrItinClass Itinerary = Itin;
1374 }
1375
1376 class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1377 class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1378
1379 class EXT_MMR6_DESC {
1380   dag OutOperandList = (outs GPR32Opnd:$rt);
1381   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1382   string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1383   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1384                        imm:$size))];
1385   InstrItinClass Itinerary = II_EXT;
1386   Format Form = FrmR;
1387   string BaseOpcode = "ext";
1388 }
1389
1390 class INS_MMR6_DESC {
1391   dag OutOperandList = (outs GPR32Opnd:$rt);
1392   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1393                        GPR32Opnd:$src);
1394   string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1395   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1396                        imm:$size, GPR32Opnd:$src))];
1397   InstrItinClass Itinerary = II_INS;
1398   Format Form = FrmR;
1399   string BaseOpcode = "ins";
1400   string Constraints = "$src = $rt";
1401 }
1402
1403 class JALRC_MMR6_DESC {
1404   dag OutOperandList = (outs GPR32Opnd:$rt);
1405   dag InOperandList = (ins GPR32Opnd:$rs);
1406   string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1407   list<dag> Pattern = [];
1408   InstrItinClass Itinerary = II_JALRC;
1409   bit isCall = 1;
1410   bit hasDelaySlot = 0;
1411   list<Register> Defs = [RA];
1412 }
1413
1414 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1415                                RegisterOperand GPROpnd>
1416     : BRANCH_DESC_BASE {
1417   dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1418   dag OutOperandList = (outs);
1419   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1420   list<Register> Defs = [AT];
1421   InstrItinClass Itinerary = II_BCCC;
1422 }
1423
1424 class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1425 class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1426
1427 //===----------------------------------------------------------------------===//
1428 //
1429 // Instruction Definitions
1430 //
1431 //===----------------------------------------------------------------------===//
1432
1433 let DecoderNamespace = "MicroMipsR6" in {
1434 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1435 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1436 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1437 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1438                    ISA_MICROMIPS32R6;
1439 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1440                   ISA_MICROMIPS32R6;
1441 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1442 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1443 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1444 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1445 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1446 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1447 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1448 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1449 def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1450                  ISA_MICROMIPS32R6;
1451 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1452                    ISA_MICROMIPS32R6;
1453 def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1454                  ISA_MICROMIPS32R6;
1455 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1456                    ISA_MICROMIPS32R6;
1457 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1458                    ISA_MICROMIPS32R6;
1459 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1460                    ISA_MICROMIPS32R6;
1461 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1462                    ISA_MICROMIPS32R6;
1463 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1464 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1465 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1466 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1467 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1468 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1469 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1470 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1471 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1472 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1473 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1474 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1475                   ISA_MICROMIPS32R6;
1476 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1477                    ISA_MICROMIPS32R6;
1478 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1479 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1480 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1481 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1482                       ISA_MICROMIPS32R6;
1483 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1484 def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
1485 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1486 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1487 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1488 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1489 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1490 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1491 def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
1492 let DecoderNamespace = "MicroMipsFP64" in {
1493   def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
1494                        ISA_MICROMIPS32R6;
1495 }
1496 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1497 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1498 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1499 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1500 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1501 def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
1502                      ISA_MICROMIPS32R6;
1503 let DecoderNamespace = "MicroMipsFP64" in {
1504   def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
1505                        ISA_MICROMIPS32R6;
1506 }
1507 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1508 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1509 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1510 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1511 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1512 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1513 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1514 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1515 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1516 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1517 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1518 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1519 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
1520 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
1521 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1522                   ISA_MICROMIPS32R6;
1523 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1524                   ISA_MICROMIPS32R6;
1525 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1526 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1527 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1528 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1529 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1530 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1531 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1532 def SWP_MMR6 : StdMMR6Rel, SWP_MMR6_ENC, SWP_MMR6_DESC, ISA_MICROMIPS32R6;
1533 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
1534 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
1535                   ISA_MICROMIPS32R6;
1536 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1537                   ISA_MICROMIPS32R6;
1538 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1539 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1540 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1541 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
1542 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
1543 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1544 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1545 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1546 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1547 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1548 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1549 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1550                   ISA_MICROMIPS32R6;
1551 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1552 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1553 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1554 let DecoderMethod = "DecodeMemMMImm16" in {
1555   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1556 }
1557 let DecoderMethod = "DecodeMemMMImm9" in {
1558   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
1559 }
1560 /// Floating Point Instructions
1561 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1562                   ISA_MICROMIPS32R6;
1563 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
1564                   ISA_MICROMIPS32R6;
1565 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1566                   ISA_MICROMIPS32R6;
1567 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
1568                   ISA_MICROMIPS32R6;
1569 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1570                   ISA_MICROMIPS32R6;
1571 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
1572                   ISA_MICROMIPS32R6;
1573 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1574                   ISA_MICROMIPS32R6;
1575 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
1576                   ISA_MICROMIPS32R6;
1577 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1578                    ISA_MICROMIPS32R6;
1579 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1580                    ISA_MICROMIPS32R6;
1581 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1582                    ISA_MICROMIPS32R6;
1583 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1584                    ISA_MICROMIPS32R6;
1585 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1586                   ISA_MICROMIPS32R6;
1587 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1588                   ISA_MICROMIPS32R6;
1589 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1590                   ISA_MICROMIPS32R6;
1591 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1592                   ISA_MICROMIPS32R6;
1593 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1594 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1595 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1596 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1597 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1598                   ISA_MICROMIPS32R6;
1599 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1600                   ISA_MICROMIPS32R6;
1601 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1602                   ISA_MICROMIPS32R6;
1603 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1604                   ISA_MICROMIPS32R6;
1605 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1606                    ISA_MICROMIPS32R6;
1607 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1608                    ISA_MICROMIPS32R6;
1609 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1610                    ISA_MICROMIPS32R6;
1611 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1612                    ISA_MICROMIPS32R6;
1613 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1614                    ISA_MICROMIPS32R6;
1615 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1616                    ISA_MICROMIPS32R6;
1617 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1618                    ISA_MICROMIPS32R6;
1619 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1620                    ISA_MICROMIPS32R6;
1621 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1622                    ISA_MICROMIPS32R6;
1623 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1624                    ISA_MICROMIPS32R6;
1625 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1626 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1627 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1628 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1629 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1630                      ISA_MICROMIPS32R6;
1631 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1632                      ISA_MICROMIPS32R6;
1633 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1634                      ISA_MICROMIPS32R6;
1635 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1636                      ISA_MICROMIPS32R6;
1637 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1638                     ISA_MICROMIPS32R6;
1639 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1640                     ISA_MICROMIPS32R6;
1641 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1642                     ISA_MICROMIPS32R6;
1643 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1644                     ISA_MICROMIPS32R6;
1645 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1646                      ISA_MICROMIPS32R6;
1647 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1648                      ISA_MICROMIPS32R6;
1649 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1650                      ISA_MICROMIPS32R6;
1651 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1652                      ISA_MICROMIPS32R6;
1653 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1654                   ISA_MICROMIPS32R6;
1655 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1656                   ISA_MICROMIPS32R6;
1657 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1658 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1659 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1660 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1661 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1662 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1663 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1664 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1665 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1666 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1667                   ISA_MICROMIPS32R6;
1668 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1669                   ISA_MICROMIPS32R6;
1670 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1671                   ISA_MICROMIPS32R6;
1672 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1673                   ISA_MICROMIPS32R6;
1674 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1675                   ISA_MICROMIPS32R6;
1676 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1677                   ISA_MICROMIPS32R6;
1678 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1679                   ISA_MICROMIPS32R6;
1680 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1681                    ISA_MICROMIPS32R6;
1682 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1683                 ISA_MICROMIPS32R6;
1684 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1685                   ISA_MICROMIPS32R6;
1686 def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1687                   ISA_MICROMIPS32R6;
1688 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1689                    ISA_MICROMIPS32R6;
1690 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1691                   ISA_MICROMIPS32R6;
1692 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1693                  ISA_MICROMIPS32R6;
1694 def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1695                     ISA_MICROMIPS32R6;
1696 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1697 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1698 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1699 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1700                   ISA_MICROMIPS32R6;
1701 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1702 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1703                      ISA_MICROMIPS32R6;
1704 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1705                      ISA_MICROMIPS32R6;
1706 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1707                      ISA_MICROMIPS32R6;
1708 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1709                      ISA_MICROMIPS32R6;
1710 def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1711 def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1712 def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1713                     ISA_MICROMIPS32R6;
1714 def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1715                     ISA_MICROMIPS32R6;
1716 def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1717                     ISA_MICROMIPS32R6;
1718 def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1719                     ISA_MICROMIPS32R6;
1720 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1721                    ISA_MICROMIPS32R6;
1722 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1723                    ISA_MICROMIPS32R6;
1724 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1725                   ISA_MICROMIPS32R6;
1726 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1727                    ISA_MICROMIPS32R6;
1728 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1729 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1730 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1731                    ISA_MICROMIPS32R6;
1732 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1733                    ISA_MICROMIPS32R6;
1734 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1735                    ISA_MICROMIPS32R6;
1736 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1737                    ISA_MICROMIPS32R6;
1738 let DecoderNamespace = "MicroMipsFP64" in {
1739   def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1740                       ISA_MICROMIPS32R6 {
1741     let BaseOpcode = "LDC164";
1742   }
1743   def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1744                       ISA_MICROMIPS32R6;
1745 }
1746 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1747 def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1748 def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1749 def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1750 }
1751
1752 def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1753                 MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1754 def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1755                 MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1756 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1757 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1758 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1759 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1760 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1761                 DecodeDisambiguates<"POP35GroupBranchMMR6">;
1762 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1763                 DecodeDisambiguates<"POP37GroupBranchMMR6">;
1764 def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1765 def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1766 def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1767 def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1768 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1769                    ISA_MICROMIPS32R6;
1770 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1771                    ISA_MICROMIPS32R6;
1772 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1773                    ISA_MICROMIPS32R6;
1774 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1775                    ISA_MICROMIPS32R6;
1776
1777 //===----------------------------------------------------------------------===//
1778 //
1779 // MicroMips instruction aliases
1780 //
1781 //===----------------------------------------------------------------------===//
1782
1783 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1784 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1785 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1786 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1787                                       !strconcat("b", "\t$offset")> {
1788   string DecoderNamespace = "MicroMipsR6";
1789 }
1790 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1791 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1792 def : MipsInstAlias<"rdhwr $rt, $rs",
1793                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1794                     ISA_MICROMIPS32R6;
1795 def : MipsInstAlias<"mtc0 $rt, $rs",
1796                     (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1797                     ISA_MICROMIPS32R6;
1798 def : MipsInstAlias<"mthc0 $rt, $rs",
1799                     (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1800                     ISA_MICROMIPS32R6;
1801 def : MipsInstAlias<"mfc0 $rt, $rs",
1802                     (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1803                     ISA_MICROMIPS32R6;
1804 def : MipsInstAlias<"mfhc0 $rt, $rs",
1805                     (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1806                     ISA_MICROMIPS32R6;
1807 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1808                     ISA_MICROMIPS32R6;
1809 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1810 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1811 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1812       ISA_MICROMIPS32R6;
1813 def : MipsInstAlias<"and $rs, $rt, $imm",
1814                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1815                     ISA_MICROMIPS32R6;
1816 def : MipsInstAlias<"and $rs, $imm",
1817                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1818                     ISA_MICROMIPS32R6;
1819 def : MipsInstAlias<"or $rs, $rt, $imm",
1820                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1821                     ISA_MICROMIPS32R6;
1822 def : MipsInstAlias<"or $rs, $imm",
1823                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1824                     ISA_MICROMIPS32R6;
1825 def : MipsInstAlias<"xor $rs, $rt, $imm",
1826                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1827                     ISA_MICROMIPS32R6;
1828 def : MipsInstAlias<"xor $rs, $imm",
1829                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1830                     ISA_MICROMIPS32R6;
1831 def : MipsInstAlias<"not $rt, $rs",
1832                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1833                     ISA_MICROMIPS32R6;
1834 def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1835                     ISA_MICROMIPS32R6;
1836 def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1837                     ISA_MICROMIPS32R6;
1838 def : MipsInstAlias<"lapc $rd, $imm",
1839                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1840                     ISA_MICROMIPS32R6;
1841
1842 //===----------------------------------------------------------------------===//
1843 //
1844 // MicroMips arbitrary patterns that map to one or more instructions
1845 //
1846 //===----------------------------------------------------------------------===//
1847
1848 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1849               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1850 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1851               (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1852
1853 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1854               (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1855                      (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1856               ISA_MICROMIPS32R6;
1857 def : MipsPat<(select i32:$cond, i32:$t, immz),
1858               (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1859               ISA_MICROMIPS32R6;
1860 def : MipsPat<(select i32:$cond, immz, i32:$f),
1861               (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1862               ISA_MICROMIPS32R6;
1863
1864 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1865                       SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1866
1867 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1868 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1869
1870 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1871               (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1872               ISA_MICROMIPS32R6;
1873 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1874               (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1875 def : MipsPat<(i32 immZExt16:$imm),
1876               (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1877 def : MipsPat<(not GPRMM16:$in),
1878               (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1879 def : MipsPat<(not GPR32:$in),
1880               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1881 // Patterns for load with a reg+imm operand.
1882 let AddedComplexity = 41 in {
1883   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1884   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1885 }
1886
1887 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1888
1889 def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1890
1891 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1892                                                          GPR32Opnd>,
1893                                 ISA_MICROMIPS32R6;
1894
1895 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1896               (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1897
1898 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1899               (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1900