contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def brtarget21_mm : Operand<OtherVT> {
  15   let EncoderMethod = "getBranchTarget21OpValueMM";
  16   let OperandType = "OPERAND_PCREL";
  17   let DecoderMethod = "DecodeBranchTarget21MM";
  18   let ParserMatchClass = MipsJumpTargetAsmOperand;
  19 }
  20
  21 def brtarget26_mm : Operand<OtherVT> {
  22   let EncoderMethod = "getBranchTarget26OpValueMM";
  23   let OperandType = "OPERAND_PCREL";
  24   let DecoderMethod = "DecodeBranchTarget26MM";
  25   let ParserMatchClass = MipsJumpTargetAsmOperand;
  26 }
  27
  28 def brtargetr6 : Operand<OtherVT> {
  29   let EncoderMethod = "getBranchTargetOpValueMMR6";
  30   let OperandType = "OPERAND_PCREL";
  31   let DecoderMethod = "DecodeBranchTargetMM";
  32   let ParserMatchClass = MipsJumpTargetAsmOperand;
  33 }
  34
  35 def brtarget_lsl2_mm : Operand<OtherVT> {
  36   let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
  37   let OperandType = "OPERAND_PCREL";
  38   // Instructions that use this operand have their decoder method
  39   // set with DecodeDisambiguates
  40   let DecoderMethod = "";
  41   let ParserMatchClass = MipsJumpTargetAsmOperand;
  42 }
  43
  44 //===----------------------------------------------------------------------===//
  45 //
  46 // Instruction Encodings
  47 //
  48 //===----------------------------------------------------------------------===//
  49 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  50 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  51 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  52 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  53 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  54 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  55 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  56 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  57 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  58 class AUI_MMR6_ENC : AUI_FM_MMR6;
  59 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  60 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  61 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  62 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  63 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  64 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  65 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  66 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
  67 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
  68 class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
  69                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
  70 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
  71                        DecodeDisambiguates<"BlezGroupBranchMMR6">;
  72 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
  73                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
  74 class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
  75                        DecodeDisambiguates<"BgtzGroupBranchMMR6">;
  76 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
  77 class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
  78 class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
  79                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  80 class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
  81                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  82 class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
  83                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  84 class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
  85                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  86 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
  87                          DecodeDisambiguates<"POP35GroupBranchMMR6">;
  88 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
  89                          DecodeDisambiguates<"POP37GroupBranchMMR6">;
  90 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
  91                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  92 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
  93                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  94 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
  95                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  96 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
  97                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  98 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  99 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
 100 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 101 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
 102 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
 103 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
 104 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
 105 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
 106 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
 107 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
 108 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
 109 class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
 110 class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
 111 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
 112 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 113 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 114 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 115 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
 116 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 117 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 118 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
 119 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
 120 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
 121 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
 122 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
 123 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
 124 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
 125 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
 126 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
 127 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
 128 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
 129 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
 130 class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
 131 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
 132 class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
 133 class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
 134 class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
 135 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
 136 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
 137 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
 138 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
 139 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
 140 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 141 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 142 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
 143 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 144 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 145 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 146 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
 147 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
 148 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
 149 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
 150 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
 151 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
 152 class LB_MMR6_ENC : LB32_FM_MMR6;
 153 class LBU_MMR6_ENC : LBU32_FM_MMR6;
 154 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
 155 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 156 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 157 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 158 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 159 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 160 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 161 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 162 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 163 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 164 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 165 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 166 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 167 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 168 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 169 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 170 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 171 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 172 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 173 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 174 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 175 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 176 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 177 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 178 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 179 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 180 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 181 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 182 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
 183 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 184 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 185 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 186                                                        0b11001100>;
 187 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 188                                                        0b11001100>;
 189 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 190                                                        0b11101100>;
 191 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 192                                                        0b11101100>;
 193 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 194 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 195 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 196 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 197 class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
 198 class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
 199 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 200 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 201 class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
 202 class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
 203 class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
 204 class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
 205 class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
 206 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 207 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 208 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
 209 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 210 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 211 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
 212 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
 213 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 214 class LI16_MMR6_ENC : LI_FM_MM16;
 215 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 216 class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
 217 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 218 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 219 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 220 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 221 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
 222 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
 223 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
 224 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
 225 class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
 226 class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
 227 class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
 228 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
 229 class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
 230 class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
 231 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
 232 class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
 233 class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
 234
 235 class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
 236 class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
 237
 238 /// Floating Point Instructions
 239 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 240 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 241 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 242 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 243 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 244 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 245 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 246 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 247 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 248 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 249 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 250 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 251 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 252 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 253 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 254 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 255 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 256 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 257
 258 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 259 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 260 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 261 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 262 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 263 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 264
 265 //===----------------------------------------------------------------------===//
 266 //
 267 // Instruction Descriptions
 268 //
 269 //===----------------------------------------------------------------------===//
 270
 271 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 272                                   RegisterOperand GPROpnd>
 273     : BRANCH_DESC_BASE {
 274   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 275   dag OutOperandList = (outs);
 276   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 277   list<Register> Defs = [AT];
 278   InstrItinClass Itinerary = II_BCCZC;
 279 }
 280
 281 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 282                                                       GPR32Opnd> {
 283   list<Register> Defs = [RA];
 284 }
 285
 286 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 287                                                       GPR32Opnd> {
 288   list<Register> Defs = [RA];
 289 }
 290
 291 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 292                                                       GPR32Opnd> {
 293   list<Register> Defs = [RA];
 294 }
 295
 296 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 297                                                       GPR32Opnd> {
 298   list<Register> Defs = [RA];
 299 }
 300
 301 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 302                                                       GPR32Opnd> {
 303   list<Register> Defs = [RA];
 304 }
 305
 306 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 307                                                       GPR32Opnd> {
 308   list<Register> Defs = [RA];
 309 }
 310
 311 class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
 312                                                     GPR32Opnd>;
 313 class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
 314                                                     GPR32Opnd>;
 315 class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
 316                                                     GPR32Opnd>;
 317 class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
 318                                                     GPR32Opnd>;
 319
 320 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 321                                 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
 322   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
 323   dag OutOperandList = (outs);
 324   string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
 325   list<Register> Defs = [AT];
 326   InstrItinClass Itinerary = II_BCCC;
 327 }
 328
 329 class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
 330                                                  GPR32Opnd>;
 331 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
 332                                                  GPR32Opnd>;
 333 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
 334                                                  GPR32Opnd>;
 335 class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
 336                                                  GPR32Opnd>;
 337 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
 338                                                  GPR32Opnd>;
 339 class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
 340                                                  GPR32Opnd>;
 341
 342 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
 343 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 344 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
 345 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
 346 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
 347 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
 348 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
 349
 350 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
 351     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 352   dag InOperandList = (ins opnd:$offset);
 353   dag OutOperandList = (outs);
 354   string AsmString = !strconcat(instr_asm, "\t$offset");
 355   bit isBarrier = 1;
 356   InstrItinClass Itinerary = Itin;
 357 }
 358
 359 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
 360   bit isCall = 1;
 361   list<Register> Defs = [RA];
 362 }
 363 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
 364   list<dag> Pattern = [(br bb:$offset)];
 365 }
 366
 367 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 368                                        !strconcat("bc16", "\t$offset"), [],
 369                                        II_BC, FrmI>,
 370                        MMR6Arch<"bc16"> {
 371   let isBranch = 1;
 372   let isTerminator = 1;
 373   let isBarrier = 1;
 374   let hasDelaySlot = 0;
 375   let AdditionalPredicates = [RelocPIC];
 376   let Defs = [AT];
 377 }
 378
 379 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 380     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
 381       MMR6Arch<instr_asm> {
 382   let isBranch = 1;
 383   let isTerminator = 1;
 384   let hasDelaySlot = 0;
 385   let Defs = [AT];
 386 }
 387 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 388 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 389
 390 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
 391 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
 392
 393 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 394     : MMR6Arch<instr_asm> {
 395   dag OutOperandList = (outs GPROpnd:$rd);
 396   dag InOperandList = (ins GPROpnd:$rt);
 397   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 398   list<dag> Pattern = [];
 399   InstrItinClass Itinerary = II_BITSWAP;
 400 }
 401
 402 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 403
 404 class BRK_MMR6_DESC : BRK_FT<"break">;
 405
 406 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 407                            RegisterOperand GPROpnd, InstrItinClass Itin>
 408       : MMR6Arch<instr_asm> {
 409   dag OutOperandList = (outs);
 410   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 411   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 412   list<dag> Pattern = [];
 413   string DecoderMethod = "DecodeCacheOpMM";
 414   InstrItinClass Itinerary = Itin;
 415 }
 416
 417 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
 418                                              II_CACHE>;
 419 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
 420                                              II_PREF>;
 421
 422 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 423                             RegisterOperand GPROpnd, InstrItinClass Itin>
 424     : MMR6Arch<instr_asm> {
 425   dag OutOperandList = (outs GPROpnd:$rt);
 426   dag InOperandList = (ins MemOpnd:$addr);
 427   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 428   string DecoderMethod = "DecodeLoadByte15";
 429   bit mayLoad = 1;
 430   InstrItinClass Itinerary = Itin;
 431 }
 432 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
 433 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
 434                                             II_LBU>;
 435
 436 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 437                              InstrItinClass Itin> : MMR6Arch<instr_asm> {
 438   dag OutOperandList = (outs GPROpnd:$rt);
 439   dag InOperandList = (ins GPROpnd:$rs);
 440   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 441   InstrItinClass Itinerary = Itin;
 442 }
 443
 444 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
 445 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
 446
 447 class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
 448 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
 449 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
 450
 451 class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
 452 class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
 453 class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
 454
 455 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 456     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 457                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 458       MMR6Arch<opstr> {
 459   let isCall = 1;
 460   let hasDelaySlot = 0;
 461   let Defs = [RA];
 462 }
 463 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 464
 465 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 466                                      RegisterOperand GPROpnd,
 467                                      InstrItinClass Itin>
 468     : MMR6Arch<opstr> {
 469   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 470   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 471   list<dag> Pattern = [];
 472   bit isTerminator = 1;
 473   bit hasDelaySlot = 0;
 474   InstrItinClass Itinerary = Itin;
 475 }
 476
 477 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 478                                                        GPR32Opnd, II_JIALC> {
 479   bit isCall = 1;
 480   list<Register> Defs = [RA];
 481 }
 482
 483 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 484                                                      GPR32Opnd, II_JIC> {
 485   bit isBarrier = 1;
 486   list<Register> Defs = [AT];
 487 }
 488
 489 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 490     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 491                       [], II_JR, FrmR>,
 492       MMR6Arch<opstr> {
 493   let hasDelaySlot = 0;
 494   let isBranch = 1;
 495   let isIndirectBranch = 1;
 496 }
 497 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 498
 499 class JRCADDIUSP_MMR6_DESC
 500     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 501                       [], II_JRADDIUSP, FrmR>,
 502       MMR6Arch<"jrcaddiusp"> {
 503   let hasDelaySlot = 0;
 504   let isTerminator = 1;
 505   let isBarrier = 1;
 506   let isBranch = 1;
 507   let isIndirectBranch = 1;
 508 }
 509
 510 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 511                       Operand ImmOpnd, InstrItinClass Itin>
 512     : MMR6Arch<instr_asm> {
 513   dag OutOperandList = (outs GPROpnd:$rd);
 514   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 515   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 516   list<dag> Pattern = [];
 517   InstrItinClass Itinerary = Itin;
 518 }
 519
 520 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
 521                                              II_ALIGN>;
 522
 523 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 524                          InstrItinClass Itin> : MMR6Arch<instr_asm> {
 525   dag OutOperandList = (outs GPROpnd:$rt);
 526   dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
 527   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 528   list<dag> Pattern = [];
 529   InstrItinClass Itinerary = Itin;
 530 }
 531
 532 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
 533
 534 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 535                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
 536   dag OutOperandList = (outs GPROpnd:$rt);
 537   dag InOperandList = (ins simm16:$imm);
 538   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 539   list<dag> Pattern = [];
 540   InstrItinClass Itinerary = Itin;
 541 }
 542
 543 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
 544 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
 545
 546 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 547                          Operand ImmOpnd, InstrItinClass Itin>
 548     : MMR6Arch<instr_asm> {
 549   dag OutOperandList = (outs GPROpnd:$rd);
 550   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 551   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 552   list<dag> Pattern = [];
 553   InstrItinClass Itinerary = Itin;
 554 }
 555
 556 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
 557
 558 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 559                            Operand ImmOpnd, InstrItinClass Itin>
 560     : MMR6Arch<instr_asm> {
 561   dag OutOperandList = (outs GPROpnd:$rt);
 562   dag InOperandList = (ins ImmOpnd:$imm);
 563   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 564   list<dag> Pattern = [];
 565   InstrItinClass Itinerary = Itin;
 566 }
 567
 568 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
 569                                                simm19_lsl2, II_ADDIUPC>;
 570 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
 571                                            II_LWPC>;
 572
 573 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 574                                InstrItinClass Itin> : MMR6Arch<instr_asm> {
 575   dag OutOperandList = (outs GPROpnd:$rd);
 576   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 577   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 578   list<dag> Pattern = [];
 579   InstrItinClass Itinerary = Itin;
 580 }
 581
 582 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
 583                                                   II_SELCCZ>;
 584 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
 585                                                   II_SELCCZ>;
 586 class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
 587 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 588   dag OutOperandList = (outs GPR32Opnd:$rt);
 589   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 590   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 591   list<dag> Pattern = [];
 592   InstrItinClass Itinerary = II_RDHWR;
 593   Format Form = FrmR;
 594 }
 595
 596 class WAIT_MMR6_DESC : WaitMM<"wait">;
 597 // FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
 598 //        Assemblers targeting specifically Release 6 should reject the SSNOP
 599 //        instruction with an error.
 600 class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
 601 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 602
 603 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
 604                             InstrItinClass Itin,
 605                             SDPatternOperator OpNode=null_frag>
 606     : MipsR6Inst {
 607   dag OutOperandList = (outs GPROpnd:$rd);
 608   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 609   string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
 610   list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
 611   string BaseOpcode = opstr;
 612   Format f = FrmR;
 613   let isCommutable = 0;
 614   let isReMaterializable = 1;
 615   InstrItinClass Itinerary = Itin;
 616
 617   // This instruction doesn't trap division by zero itself. We must insert
 618   // teq instructions as well.
 619   bit usesCustomInserter = 1;
 620 }
 621 class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
 622 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
 623 class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
 624 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
 625 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
 626 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
 627 class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
 628 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
 629 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
 630                                   or> {
 631   int AddedComplexity = 1;
 632 }
 633 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
 634 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
 635                                    immZExt16, xor>;
 636 class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
 637   InstrItinClass Itinerary = II_SW;
 638 }
 639 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
 640                                  InstrItinClass Itin> {
 641   dag InOperandList = (ins RO:$rs);
 642   dag OutOperandList = (outs RO:$rt);
 643   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 644   list<dag> Pattern = [];
 645   Format f = FrmR;
 646   string BaseOpcode = instr_asm;
 647   bit hasSideEffects = 0;
 648   InstrItinClass Itinerary = Itin;
 649 }
 650 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
 651                                                     II_WRPGPR>;
 652 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
 653
 654 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 655                          RegisterOperand SrcRC, InstrItinClass Itin> {
 656   dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
 657   dag OutOperandList = (outs DstRC:$rs);
 658   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 659   list<dag> Pattern = [];
 660   Format f = FrmFR;
 661   string BaseOpcode = opstr;
 662   InstrItinClass Itinerary = Itin;
 663 }
 664 class MTC1_MMR6_DESC_BASE<
 665       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 666       InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
 667       : MipsR6Inst {
 668   dag InOperandList = (ins SrcRC:$rt);
 669   dag OutOperandList = (outs DstRC:$fs);
 670   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 671   list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
 672   Format f = FrmFR;
 673   InstrItinClass Itinerary = Itin;
 674   string BaseOpcode = opstr;
 675 }
 676 class MTC1_64_MMR6_DESC_BASE<
 677       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 678       InstrItinClass Itin = NoItinerary> : MipsR6Inst {
 679   dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
 680   dag OutOperandList = (outs DstRC:$fs);
 681   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 682   list<dag> Pattern = [];
 683   Format f = FrmFR;
 684   InstrItinClass Itinerary = Itin;
 685   string BaseOpcode = opstr;
 686   // $fs_in is part of a white lie to work around a widespread bug in the FPU
 687   // implementation. See expandBuildPairF64 for details.
 688   let Constraints = "$fs = $fs_in";
 689 }
 690 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 691                          RegisterOperand SrcRC, InstrItinClass Itin> {
 692   dag InOperandList = (ins SrcRC:$rt);
 693   dag OutOperandList = (outs DstRC:$impl);
 694   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 695   list<dag> Pattern = [];
 696   Format f = FrmFR;
 697   string BaseOpcode = opstr;
 698   InstrItinClass Itinerary = Itin;
 699 }
 700
 701 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
 702                                            II_MTC0>;
 703 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
 704                                            II_MTC1, bitconvert>, HARDFLOAT;
 705 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
 706                                            II_MTC2>;
 707 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
 708                                             II_MTHC0>;
 709 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
 710                                             II_MTC2>;
 711
 712 class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 713                           RegisterOperand SrcRC, InstrItinClass Itin> {
 714   dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
 715   dag OutOperandList = (outs DstRC:$rt);
 716   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 717   list<dag> Pattern = [];
 718   Format f = FrmFR;
 719   string BaseOpcode = opstr;
 720   InstrItinClass Itinerary = Itin;
 721 }
 722 class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 723                           RegisterOperand SrcRC,
 724                           InstrItinClass Itin = NoItinerary,
 725                           SDPatternOperator OpNode = null_frag> : MipsR6Inst {
 726   dag InOperandList = (ins SrcRC:$fs);
 727   dag OutOperandList = (outs DstRC:$rt);
 728   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 729   list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
 730   Format f = FrmFR;
 731   InstrItinClass Itinerary = Itin;
 732   string BaseOpcode = opstr;
 733 }
 734 class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 735                           RegisterOperand SrcRC, InstrItinClass Itin> {
 736   dag InOperandList = (ins SrcRC:$impl);
 737   dag OutOperandList = (outs DstRC:$rt);
 738   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 739   list<dag> Pattern = [];
 740   Format f = FrmFR;
 741   string BaseOpcode = opstr;
 742   InstrItinClass Itinerary = Itin;
 743 }
 744 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
 745                                            II_MFC0>;
 746 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
 747                                            II_MFC1, bitconvert>, HARDFLOAT;
 748 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
 749                                            II_MFC2>;
 750 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
 751                                             II_MFHC0>;
 752 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
 753                                             II_MFC2>;
 754
 755 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 756   dag InOperandList = (ins mem_mm_16:$addr);
 757   dag OutOperandList = (outs FGR64Opnd:$ft);
 758   string AsmString = !strconcat("ldc1", "\t$ft, $addr");
 759   list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
 760   Format f = FrmFI;
 761   InstrItinClass Itinerary = II_LDC1;
 762   string BaseOpcode = "ldc1";
 763   bit mayLoad = 1;
 764   let DecoderMethod = "DecodeFMemMMR2";
 765 }
 766
 767 class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 768   dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
 769   dag OutOperandList = (outs);
 770   string AsmString = !strconcat("sdc1", "\t$ft, $addr");
 771   list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
 772   Format f = FrmFI;
 773   InstrItinClass Itinerary = II_SDC1;
 774   string BaseOpcode = "sdc1";
 775   bit mayStore = 1;
 776   let DecoderMethod = "DecodeFMemMMR2";
 777 }
 778
 779 class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 780   dag OutOperandList = (outs COP2Opnd:$rt);
 781   dag InOperandList = (ins mem_mm_11:$addr);
 782   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 783   list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
 784   Format f = FrmFI;
 785   InstrItinClass Itinerary = itin;
 786   string BaseOpcode = opstr;
 787   bit mayLoad = 1;
 788   string DecoderMethod = "DecodeFMemCop2MMR6";
 789 }
 790 class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
 791 class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
 792
 793 class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 794   dag OutOperandList = (outs);
 795   dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
 796   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 797   list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
 798   Format f = FrmFI;
 799   InstrItinClass Itinerary = itin;
 800   string BaseOpcode = opstr;
 801   bit mayStore = 1;
 802   string DecoderMethod = "DecodeFMemCop2MMR6";
 803 }
 804 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
 805 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
 806
 807 class GINV_MMR6_DESC_BASE<string opstr,
 808                           RegisterOperand SrcRC, InstrItinClass Itin> {
 809   dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
 810   dag OutOperandList = (outs);
 811   string AsmString = !strconcat(opstr, "\t$rs, $type");
 812   list<dag> Pattern = [];
 813   Format f = FrmFR;
 814   string BaseOpcode = opstr;
 815   InstrItinClass Itinerary = Itin;
 816 }
 817
 818 class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
 819                                             II_GINVI> {
 820   dag InOperandList = (ins GPR32Opnd:$rs);
 821   string AsmString = "ginvi\t$rs";
 822 }
 823 class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
 824                                             II_GINVT>;
 825
 826 class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 827   dag OutOperandList = (outs GPR32Opnd:$dst);
 828   dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
 829   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 830   InstrItinClass Itinerary = itin;
 831   string BaseOpcode = opstr;
 832   bit mayStore = 1;
 833   string Constraints = "$rt = $dst";
 834   string DecoderMethod = "DecodeMemMMImm9";
 835 }
 836
 837 class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 838   dag OutOperandList = (outs GPR32Opnd:$rt);
 839   dag InOperandList = (ins mem_mm_9:$addr);
 840   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 841   InstrItinClass Itinerary = itin;
 842   string BaseOpcode = opstr;
 843   bit mayLoad = 1;
 844   string DecoderMethod = "DecodeMemMMImm9";
 845 }
 846
 847 class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
 848 class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
 849
 850 /// Floating Point Instructions
 851 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 852                             InstrItinClass Itin, bit isComm,
 853                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 854   dag OutOperandList = (outs RC:$fd);
 855   dag InOperandList = (ins RC:$ft, RC:$fs);
 856   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 857   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 858   InstrItinClass Itinerary = Itin;
 859   bit isCommutable = isComm;
 860 }
 861 class FADD_S_MMR6_DESC
 862   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 863 class FSUB_S_MMR6_DESC
 864   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 865 class FMUL_S_MMR6_DESC
 866   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 867 class FDIV_S_MMR6_DESC
 868   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 869 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
 870                                             II_MADDF_S>, HARDFLOAT;
 871 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
 872                                             II_MADDF_D>, HARDFLOAT;
 873 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
 874                                             II_MSUBF_S>, HARDFLOAT;
 875 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
 876                                             II_MSUBF_D>, HARDFLOAT;
 877
 878 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 879                                RegisterOperand SrcRC, InstrItinClass Itin,
 880                                SDPatternOperator OpNode = null_frag>
 881                                : HARDFLOAT, NeverHasSideEffects {
 882   dag OutOperandList = (outs DstRC:$ft);
 883   dag InOperandList = (ins SrcRC:$fs);
 884   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 885   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 886   InstrItinClass Itinerary = Itin;
 887   Format Form = FrmFR;
 888 }
 889 class FMOV_S_MMR6_DESC
 890   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 891 class FNEG_S_MMR6_DESC
 892   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 893
 894 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
 895                         HARDFLOAT;
 896 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
 897                         HARDFLOAT;
 898 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
 899                         HARDFLOAT;
 900 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
 901                         HARDFLOAT;
 902
 903 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
 904                          HARDFLOAT;
 905 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
 906                          HARDFLOAT;
 907 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
 908                          HARDFLOAT;
 909 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
 910                          HARDFLOAT;
 911
 912 class CVT_MMR6_DESC_BASE<
 913     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 914     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 915     : HARDFLOAT, NeverHasSideEffects {
 916   dag OutOperandList = (outs DstRC:$ft);
 917   dag InOperandList = (ins SrcRC:$fs);
 918   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 919   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 920   InstrItinClass Itinerary = Itin;
 921   Format Form = FrmFR;
 922 }
 923
 924 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 925                                              II_CVT>;
 926 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 927                                              II_CVT>;
 928 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 929                                              II_CVT>;
 930 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 931                                              II_CVT>, FGR_64;
 932 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 933                                              II_CVT>;
 934 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 935                                              II_CVT>, FGR_64;
 936
 937 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 938                        RegisterOperand FGROpnd, InstrItinClass Itin> {
 939   def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 940       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 941       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
 942       ISA_MICROMIPS32R6;
 943   def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 944       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 945       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
 946       ISA_MICROMIPS32R6;
 947   def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 948       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 949       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
 950       ISA_MICROMIPS32R6;
 951   def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 952       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 953       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
 954       ISA_MICROMIPS32R6;
 955   def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 956       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 957       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
 958       ISA_MICROMIPS32R6;
 959   def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 960       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 961       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
 962       ISA_MICROMIPS32R6;
 963   def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 964       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 965       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
 966       ISA_MICROMIPS32R6;
 967   def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 968       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 969       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
 970       ISA_MICROMIPS32R6;
 971   def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 972       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 973       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
 974       ISA_MICROMIPS32R6;
 975   def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 976       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 977       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
 978       ISA_MICROMIPS32R6;
 979   def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 980       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 981       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 982       ISA_MICROMIPS32R6;
 983   def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 984       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 985       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 986       ISA_MICROMIPS32R6;
 987   def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 988       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 989       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
 990       ISA_MICROMIPS32R6;
 991   def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 992       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 993       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
 994       ISA_MICROMIPS32R6;
 995   def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 996       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 997       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
 998       ISA_MICROMIPS32R6;
 999   def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1000       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1001       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1002       ISA_MICROMIPS32R6;
1003 }
1004
1005 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1006                              RegisterOperand SrcRC, InstrItinClass Itin,
1007                              SDPatternOperator OpNode = null_frag>
1008     : HARDFLOAT, NeverHasSideEffects {
1009   dag OutOperandList = (outs DstRC:$ft);
1010   dag InOperandList  = (ins SrcRC:$fs);
1011   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1012   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1013   InstrItinClass Itinerary = Itin;
1014   Format Form = FrmFR;
1015   list<Predicate> EncodingPredicates = [HasStdEnc];
1016 }
1017
1018 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1019                                                     FGR32Opnd, II_FLOOR>;
1020 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1021                                                     FGR64Opnd, II_FLOOR>;
1022 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1023                                                     FGR32Opnd, II_FLOOR>;
1024 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1025                                                     AFGR64Opnd, II_FLOOR>;
1026 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1027                                                    FGR32Opnd, II_CEIL>;
1028 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1029                                                    FGR64Opnd, II_CEIL>;
1030 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1031                                                    FGR32Opnd, II_CEIL>;
1032 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1033                                                    AFGR64Opnd, II_CEIL>;
1034 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1035                                                     FGR32Opnd, II_TRUNC>;
1036 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1037                                                     FGR64Opnd, II_TRUNC>;
1038 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1039                                                     FGR32Opnd, II_TRUNC>;
1040 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1041                                                     AFGR64Opnd, II_TRUNC>;
1042 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1043                                                  II_SQRT_S, fsqrt>;
1044 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
1045                                                  II_SQRT_D, fsqrt>;
1046 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1047                                                    FGR32Opnd, II_ROUND>;
1048 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1049                                                    FGR64Opnd, II_ROUND>;
1050 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1051                                                    FGR32Opnd, II_ROUND>;
1052 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1053                                                    FGR64Opnd, II_ROUND>;
1054
1055 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1056 class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1057
1058 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1059                                               II_SELCCZ_S>;
1060 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1061                                               II_SELCCZ_D>;
1062 class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1063                                               II_SELCCZ_S>;
1064 class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1065                                               II_SELCCZ_D>;
1066 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1067                                               II_RINT_S>;
1068 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1069                                               II_RINT_S>;
1070 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1071                                               II_CLASS_S>;
1072 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1073                                               II_CLASS_S>;
1074
1075 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1076                            InstrItinClass Itin>
1077     : Store<opstr, RO>, MMR6Arch<opstr> {
1078   let DecoderMethod = "DecodeMemMMImm16";
1079   InstrItinClass Itinerary = Itin;
1080 }
1081 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1082
1083 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1084 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1085       MMR6Arch<"addu16"> {
1086   int AddedComplexity = 1;
1087 }
1088 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1089       MMR6Arch<"and16">;
1090 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1091       MMR6Arch<"andi16">;
1092 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1093   int AddedComplexity = 1;
1094 }
1095 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1096 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1097       MMR6Arch<"sll16">;
1098 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1099       MMR6Arch<"srl16">;
1100 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
1101 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1102       MMR6Arch<"li16">, IsAsCheapAsAMove;
1103 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1104 class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">;
1105 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
1106 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1107       MMR6Arch<"subu16"> {
1108   int AddedComplexity = 1;
1109 }
1110 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1111       MMR6Arch<"xor16">;
1112
1113 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1114   dag OutOperandList = (outs GPR32Opnd:$rt);
1115   dag InOperandList = (ins mem:$addr);
1116   string AsmString = "lw\t$rt, $addr";
1117   let DecoderMethod = "DecodeMemMMImm16";
1118   let canFoldAsLoad = 1;
1119   let mayLoad = 1;
1120   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1121   InstrItinClass Itinerary = II_LW;
1122 }
1123
1124 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1125   dag OutOperandList = (outs GPR32Opnd:$rt);
1126   dag InOperandList = (ins uimm16:$imm16);
1127   string AsmString = "lui\t$rt, $imm16";
1128   list<dag> Pattern = [];
1129   bit hasSideEffects = 0;
1130   bit isReMaterializable = 1;
1131   InstrItinClass Itinerary = II_LUI;
1132   Format Form = FrmI;
1133 }
1134
1135 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1136   dag OutOperandList = (outs);
1137   dag InOperandList = (ins uimm5:$stype);
1138   string AsmString = !strconcat("sync", "\t$stype");
1139   list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1140   InstrItinClass Itinerary = II_SYNC;
1141   bit HasSideEffects = 1;
1142 }
1143
1144 class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1145   let DecoderMethod = "DecodeSynciR6";
1146 }
1147
1148 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1149   dag OutOperandList = (outs GPR32Opnd:$rt);
1150   dag InOperandList = (ins GPR32Opnd:$rd);
1151   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1152   InstrItinClass Itinerary = II_RDPGPR;
1153 }
1154
1155 class SDBBP_MMR6_DESC : MipsR6Inst {
1156   dag OutOperandList = (outs);
1157   dag InOperandList = (ins uimm20:$code_);
1158   string AsmString = !strconcat("sdbbp", "\t$code_");
1159   list<dag> Pattern = [];
1160   InstrItinClass Itinerary = II_SDBBP;
1161 }
1162
1163 class LWM16_MMR6_DESC
1164     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1165                       !strconcat("lwm16", "\t$rt, $addr"), [],
1166                       II_LWM, FrmI>,
1167       MMR6Arch<"lwm16"> {
1168   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1169   let mayLoad = 1;
1170   ComplexPattern Addr = addr;
1171 }
1172
1173 class SWM16_MMR6_DESC
1174     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1175                       !strconcat("swm16", "\t$rt, $addr"), [],
1176                       II_SWM, FrmI>,
1177       MMR6Arch<"swm16"> {
1178   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1179   let mayStore = 1;
1180   ComplexPattern Addr = addr;
1181 }
1182
1183 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1184                           SDPatternOperator OpNode, InstrItinClass Itin,
1185                           Operand MemOpnd>
1186     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1187                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1188       MMR6Arch<opstr> {
1189   let DecoderMethod = "DecodeMemMMImm4";
1190   let mayStore = 1;
1191 }
1192 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1193                                            truncstorei8, II_SB, mem_mm_4>;
1194 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1195                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
1196 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1197                                            store, II_SW, mem_mm_4_lsl2>;
1198
1199 class SWSP_MMR6_DESC
1200     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1201                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1202       MMR6Arch<"sw"> {
1203   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1204   let mayStore = 1;
1205 }
1206
1207 class JALRC_HB_MMR6_DESC {
1208   dag OutOperandList = (outs GPR32Opnd:$rt);
1209   dag InOperandList = (ins GPR32Opnd:$rs);
1210   string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1211   list<dag> Pattern = [];
1212   InstrItinClass Itinerary = II_JALR_HB;
1213   Format Form = FrmJ;
1214   bit isIndirectBranch = 1;
1215   bit hasDelaySlot = 0;
1216 }
1217
1218 class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1219   dag OutOperandList = (outs);
1220   dag InOperandList = (ins);
1221   string AsmString = opstr;
1222   list<dag> Pattern = [];
1223   InstrItinClass Itinerary = Itin;
1224 }
1225
1226 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1227 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1228
1229 class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1230   dag OutOperandList = (outs GPR32Opnd:$rs);
1231   dag InOperandList = (ins);
1232   string AsmString = !strconcat(opstr, "\t$rs");
1233   list<dag> Pattern = [];
1234   InstrItinClass Itinerary = Itin;
1235   bit hasUnModeledSideEffects = 1;
1236 }
1237
1238 class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1239 class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1240
1241 class BEQZC_MMR6_DESC
1242     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1243       MMR6Arch<"beqzc">;
1244 class BNEZC_MMR6_DESC
1245     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1246       MMR6Arch<"bnezc">;
1247
1248 class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1249     InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1250            !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1251     HARDFLOAT, BRANCH_DESC_BASE {
1252   list<Register> Defs = [AT];
1253 }
1254
1255 class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1256 class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1257
1258 class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1259     : BRANCH_DESC_BASE {
1260   dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1261   dag OutOperandList = (outs);
1262   string AsmString = !strconcat(opstr, "\t$rt, $offset");
1263   list<Register> Defs = [AT];
1264   InstrItinClass Itinerary = Itin;
1265 }
1266
1267 class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1268 class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1269
1270 class EXT_MMR6_DESC {
1271   dag OutOperandList = (outs GPR32Opnd:$rt);
1272   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1273   string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1274   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1275                        imm:$size))];
1276   InstrItinClass Itinerary = II_EXT;
1277   Format Form = FrmR;
1278   string BaseOpcode = "ext";
1279 }
1280
1281 class INS_MMR6_DESC {
1282   dag OutOperandList = (outs GPR32Opnd:$rt);
1283   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1284                        GPR32Opnd:$src);
1285   string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1286   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1287                        imm:$size, GPR32Opnd:$src))];
1288   InstrItinClass Itinerary = II_INS;
1289   Format Form = FrmR;
1290   string BaseOpcode = "ins";
1291   string Constraints = "$src = $rt";
1292 }
1293
1294 class JALRC_MMR6_DESC {
1295   dag OutOperandList = (outs GPR32Opnd:$rt);
1296   dag InOperandList = (ins GPR32Opnd:$rs);
1297   string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1298   list<dag> Pattern = [];
1299   InstrItinClass Itinerary = II_JALRC;
1300   bit isCall = 1;
1301   bit hasDelaySlot = 0;
1302   list<Register> Defs = [RA];
1303 }
1304
1305 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1306                                RegisterOperand GPROpnd>
1307     : BRANCH_DESC_BASE {
1308   dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1309   dag OutOperandList = (outs);
1310   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1311   list<Register> Defs = [AT];
1312   InstrItinClass Itinerary = II_BCCC;
1313 }
1314
1315 class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1316 class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1317
1318 //===----------------------------------------------------------------------===//
1319 //
1320 // Instruction Definitions
1321 //
1322 //===----------------------------------------------------------------------===//
1323
1324 let DecoderNamespace = "MicroMipsR6" in {
1325 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1326 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1327 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1328 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1329                    ISA_MICROMIPS32R6;
1330 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1331                   ISA_MICROMIPS32R6;
1332 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1333 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1334 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1335 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1336 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1337 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1338 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1339 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1340 def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1341                  ISA_MICROMIPS32R6;
1342 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1343                    ISA_MICROMIPS32R6;
1344 def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1345                  ISA_MICROMIPS32R6;
1346 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1347                    ISA_MICROMIPS32R6;
1348 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1349                    ISA_MICROMIPS32R6;
1350 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1351                    ISA_MICROMIPS32R6;
1352 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1353                    ISA_MICROMIPS32R6;
1354 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1355 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1356 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1357 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1358 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1359 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1360 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1361 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1362 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1363 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1364 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1365 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1366                   ISA_MICROMIPS32R6;
1367 def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1368                  ISA_MICROMIPS32R6, ASE_GINV;
1369 def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1370                  ISA_MICROMIPS32R6, ASE_GINV;
1371 let FastISelShouldIgnore = 1 in
1372 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1373                    ISA_MICROMIPS32R6;
1374 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1375 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1376 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1377 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1378                       ISA_MICROMIPS32R6;
1379 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1380 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1381 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1382 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1383 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1384 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1385 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1386 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1387 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1388 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1389 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1390 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1391 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1392 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1393 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1394 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1395 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1396 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1397 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1398 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1399 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1400 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1401 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1402 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1403 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1404                   ISA_MICROMIPS32R6;
1405 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1406                   ISA_MICROMIPS32R6;
1407 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1408 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1409 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1410 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1411 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1412 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1413 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1414 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1415                   ISA_MICROMIPS32R6;
1416 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1417 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1418 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1419 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1420 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1421 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1422 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1423 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1424 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1425 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1426                   ISA_MICROMIPS32R6;
1427 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1428 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1429 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1430 let DecoderMethod = "DecodeMemMMImm16" in {
1431   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1432 }
1433 /// Floating Point Instructions
1434 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1435                   ISA_MICROMIPS32R6;
1436 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1437                   ISA_MICROMIPS32R6;
1438 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1439                   ISA_MICROMIPS32R6;
1440 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1441                   ISA_MICROMIPS32R6;
1442 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1443                    ISA_MICROMIPS32R6;
1444 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1445                    ISA_MICROMIPS32R6;
1446 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1447                    ISA_MICROMIPS32R6;
1448 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1449                    ISA_MICROMIPS32R6;
1450 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1451                   ISA_MICROMIPS32R6;
1452 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1453                   ISA_MICROMIPS32R6;
1454 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1455 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1456 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1457 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1458 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1459                   ISA_MICROMIPS32R6;
1460 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1461                   ISA_MICROMIPS32R6;
1462 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1463                   ISA_MICROMIPS32R6;
1464 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1465                   ISA_MICROMIPS32R6;
1466 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1467                    ISA_MICROMIPS32R6;
1468 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1469                    ISA_MICROMIPS32R6;
1470 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1471                    ISA_MICROMIPS32R6;
1472 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1473                    ISA_MICROMIPS32R6;
1474 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1475                    ISA_MICROMIPS32R6;
1476 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1477                    ISA_MICROMIPS32R6;
1478 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1479 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1480 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1481                      ISA_MICROMIPS32R6;
1482 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1483                      ISA_MICROMIPS32R6;
1484 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1485                      ISA_MICROMIPS32R6;
1486 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1487                      ISA_MICROMIPS32R6;
1488 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1489                     ISA_MICROMIPS32R6;
1490 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1491                     ISA_MICROMIPS32R6;
1492 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1493                     ISA_MICROMIPS32R6;
1494 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1495                     ISA_MICROMIPS32R6;
1496 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1497                      ISA_MICROMIPS32R6;
1498 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1499                      ISA_MICROMIPS32R6;
1500 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1501                      ISA_MICROMIPS32R6;
1502 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1503                      ISA_MICROMIPS32R6;
1504 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1505 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1506 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1507 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1508 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1509                   ISA_MICROMIPS32R6;
1510 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1511                   ISA_MICROMIPS32R6;
1512 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1513                   ISA_MICROMIPS32R6;
1514 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1515                   ISA_MICROMIPS32R6;
1516 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1517                   ISA_MICROMIPS32R6;
1518 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1519                   ISA_MICROMIPS32R6;
1520 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1521                   ISA_MICROMIPS32R6;
1522 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1523                    ISA_MICROMIPS32R6;
1524 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1525                 ISA_MICROMIPS32R6;
1526 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1527                   ISA_MICROMIPS32R6;
1528 def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1529                   ISA_MICROMIPS32R6;
1530 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1531                    ISA_MICROMIPS32R6;
1532 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1533                   ISA_MICROMIPS32R6;
1534 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1535                  ISA_MICROMIPS32R6;
1536 def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1537                     ISA_MICROMIPS32R6;
1538 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1539 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1540 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1541 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1542                   ISA_MICROMIPS32R6;
1543 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1544 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1545                      ISA_MICROMIPS32R6;
1546 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1547                      ISA_MICROMIPS32R6;
1548 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1549                      ISA_MICROMIPS32R6;
1550 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1551                      ISA_MICROMIPS32R6;
1552 def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1553 def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1554 def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1555                     ISA_MICROMIPS32R6;
1556 def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1557                     ISA_MICROMIPS32R6;
1558 def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1559                     ISA_MICROMIPS32R6;
1560 def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1561                     ISA_MICROMIPS32R6;
1562 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1563                    ISA_MICROMIPS32R6;
1564 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1565                    ISA_MICROMIPS32R6;
1566 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1567                   ISA_MICROMIPS32R6;
1568 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1569                    ISA_MICROMIPS32R6;
1570 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1571 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1572 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1573                    ISA_MICROMIPS32R6;
1574 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1575                    ISA_MICROMIPS32R6;
1576 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1577                    ISA_MICROMIPS32R6;
1578 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1579                    ISA_MICROMIPS32R6;
1580 let DecoderNamespace = "MicroMipsFP64" in {
1581   def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1582                       ISA_MICROMIPS32R6 {
1583     let BaseOpcode = "LDC164";
1584   }
1585   def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1586                       ISA_MICROMIPS32R6;
1587 }
1588 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1589 def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1590 def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1591 def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1592 def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1593 def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1594 }
1595
1596 def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1597                 MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1598 def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1599                 MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1600 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1601 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1602 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1603 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1604 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1605                 DecodeDisambiguates<"POP35GroupBranchMMR6">;
1606 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1607                 DecodeDisambiguates<"POP37GroupBranchMMR6">;
1608 def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1609 def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1610 def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1611 def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1612 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1613                    ISA_MICROMIPS32R6;
1614 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1615                    ISA_MICROMIPS32R6;
1616 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1617                    ISA_MICROMIPS32R6;
1618 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1619                    ISA_MICROMIPS32R6;
1620
1621 //===----------------------------------------------------------------------===//
1622 //
1623 // MicroMips instruction aliases
1624 //
1625 //===----------------------------------------------------------------------===//
1626
1627 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1628 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1629 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1630 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1631                                       !strconcat("b", "\t$offset")> {
1632   string DecoderNamespace = "MicroMipsR6";
1633 }
1634 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1635 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1636 def : MipsInstAlias<"rdhwr $rt, $rs",
1637                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1638                     ISA_MICROMIPS32R6;
1639 def : MipsInstAlias<"mtc0 $rt, $rs",
1640                     (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1641                     ISA_MICROMIPS32R6;
1642 def : MipsInstAlias<"mthc0 $rt, $rs",
1643                     (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1644                     ISA_MICROMIPS32R6;
1645 def : MipsInstAlias<"mfc0 $rt, $rs",
1646                     (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1647                     ISA_MICROMIPS32R6;
1648 def : MipsInstAlias<"mfhc0 $rt, $rs",
1649                     (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1650                     ISA_MICROMIPS32R6;
1651 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1652                     ISA_MICROMIPS32R6;
1653 def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1654                     ISA_MICROMIPS32R6;
1655 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1656 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1657 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1658       ISA_MICROMIPS32R6;
1659 def : MipsInstAlias<"and $rs, $rt, $imm",
1660                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1661                     ISA_MICROMIPS32R6;
1662 def : MipsInstAlias<"and $rs, $imm",
1663                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1664                     ISA_MICROMIPS32R6;
1665 def : MipsInstAlias<"or $rs, $rt, $imm",
1666                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1667                     ISA_MICROMIPS32R6;
1668 def : MipsInstAlias<"or $rs, $imm",
1669                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1670                     ISA_MICROMIPS32R6;
1671 def : MipsInstAlias<"xor $rs, $rt, $imm",
1672                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1673                     ISA_MICROMIPS32R6;
1674 def : MipsInstAlias<"xor $rs, $imm",
1675                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1676                     ISA_MICROMIPS32R6;
1677 def : MipsInstAlias<"not $rt, $rs",
1678                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1679                     ISA_MICROMIPS32R6;
1680 def : MipsInstAlias<"not $rt",
1681                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1682                     ISA_MICROMIPS32R6;
1683 def : MipsInstAlias<"lapc $rd, $imm",
1684                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1685                     ISA_MICROMIPS32R6;
1686 def : MipsInstAlias<"neg $rt, $rs",
1687                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1688       ISA_MICROMIPS32R6;
1689 def : MipsInstAlias<"neg $rt",
1690                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1691       ISA_MICROMIPS32R6;
1692 def : MipsInstAlias<"negu $rt, $rs",
1693                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1694       ISA_MICROMIPS32R6;
1695 def : MipsInstAlias<"negu $rt",
1696                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1697       ISA_MICROMIPS32R6;
1698 def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1699                                                          brtarget7_mm:$offset),
1700                     0>, ISA_MICROMIPS32R6;
1701 def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1702                                                          brtarget7_mm:$offset),
1703                     0>, ISA_MICROMIPS32R6;
1704 def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1705                     ISA_MICROMIPS32R6;
1706
1707 //===----------------------------------------------------------------------===//
1708 //
1709 // MicroMips arbitrary patterns that map to one or more instructions
1710 //
1711 //===----------------------------------------------------------------------===//
1712
1713 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1714               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1715 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1716               (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1717
1718 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1719               (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1720                      (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1721               ISA_MICROMIPS32R6;
1722 def : MipsPat<(select i32:$cond, i32:$t, immz),
1723               (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1724               ISA_MICROMIPS32R6;
1725 def : MipsPat<(select i32:$cond, immz, i32:$f),
1726               (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1727               ISA_MICROMIPS32R6;
1728
1729 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1730                       SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1731
1732 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1733 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1734
1735 def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1736 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
1737 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1738               (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1739
1740 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1741               (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1742               ISA_MICROMIPS32R6;
1743 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1744               (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1745 def : MipsPat<(i32 immZExt16:$imm),
1746               (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1747 def : MipsPat<(not GPRMM16:$in),
1748               (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1749 def : MipsPat<(not GPR32:$in),
1750               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1751 // Patterns for load with a reg+imm operand.
1752 let AddedComplexity = 41 in {
1753   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1754   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1755 }
1756
1757 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1758
1759 def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1760
1761 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1762                                                          GPR32Opnd>,
1763                                 ISA_MICROMIPS32R6;
1764
1765 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1766               (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1767
1768 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1769               (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1770
1771
1772 def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1773               (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1774 def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1775               (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1776
1777 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1778               (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1779       ISA_MICROMIPS32R6;
1780 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1781               (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1782       ISA_MICROMIPS32R6;
1783 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1784               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1785       ISA_MICROMIPS32R6;
1786 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1787               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1788       ISA_MICROMIPS32R6;
1789 def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1790               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1791       ISA_MICROMIPS32R6;
1792 def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1793               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1794       ISA_MICROMIPS32R6;
1795
1796 def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1797               (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1798       ISA_MICROMIPS32R6;
1799 def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1800               (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1801       ISA_MICROMIPS32R6;
1802
1803 def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1804               (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;