1 //=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes MicroMips64r6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
20 class DAUI_MMR6_ENC : DAUI_FM_MMR6;
21 class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
22 class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
23 class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
24 class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
25 class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
26 class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
27 class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
28 class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
29 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
30 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
31 class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
32 class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
33 class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
34 class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
35 class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
36 class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
37 class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
38 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
39 class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
40 class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
41 class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
42 class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
43 class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
44 class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
45 class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
46 class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
47 class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
48 class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
49 class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
50 class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dsbh", 0b0111101100>;
51 class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
52 class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll", 0b000000000>;
53 class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll32", 0b000001000>;
54 class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsllv", 0b000010000>;
55 class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
56 class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra", 0b010000000>;
57 class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra32", 0b010000100>;
58 class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
59 class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
60 class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
61 class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
62 class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
63 class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
64 class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
65 class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
66 class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
67 class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
68 class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
69 class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
70 class DBITSWAP_MM64R6_ENC : POOL32S_DBITSWAP_FM_MMR6<"dbitswap">;
71 class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6<"dlsa">;
72 class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6<"lwupc">;
74 //===----------------------------------------------------------------------===//
76 // Instruction Descriptions
78 //===----------------------------------------------------------------------===//
80 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
82 : MMR6Arch<instr_asm>, MipsR6Inst {
83 dag OutOperandList = (outs GPROpnd:$rt);
84 dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
85 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
86 list<dag> Pattern = [];
87 InstrItinClass Itinerary = Itin;
89 class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
91 class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
93 : MMR6Arch<instr_asm>, MipsR6Inst {
94 dag OutOperandList = (outs GPROpnd:$rs);
95 dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm);
96 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
97 string Constraints = "$rs = $rt";
98 InstrItinClass Itinerary = Itin;
100 class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
101 class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
103 class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
104 Operand SizeOpnd, SDPatternOperator Op = null_frag>
105 : MMR6Arch<instr_asm>, MipsR6Inst {
106 dag OutOperandList = (outs RO:$rt);
107 dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
108 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
109 list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
110 InstrItinClass Itinerary = II_EXT;
112 string BaseOpcode = instr_asm;
114 // TODO: Add 'pos + size' constraint check to dext* instructions
115 // DEXT: 0 < pos + size <= 63
116 // DEXTM, DEXTU: 32 < pos + size <= 64
117 class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
118 uimm5_plus1, MipsExt>;
119 class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
120 uimm5_plus33, MipsExt>;
121 class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
122 uimm5_plus1, MipsExt>;
124 class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
125 Operand ImmOpnd, InstrItinClass itin>
126 : MMR6Arch<instr_asm>, MipsR6Inst {
127 dag OutOperandList = (outs GPROpnd:$rd);
128 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
129 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
130 list<dag> Pattern = [];
131 InstrItinClass Itinerary = itin;
134 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3,
137 class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV,
139 class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, II_DMOD,
141 class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU,
143 class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU,
146 class DCLO_MM64R6_DESC {
147 dag OutOperandList = (outs GPR64Opnd:$rt);
148 dag InOperandList = (ins GPR64Opnd:$rs);
149 string AsmString = !strconcat("dclo", "\t$rt, $rs");
150 list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
151 InstrItinClass Itinerary = II_DCLO;
153 string BaseOpcode = "dclo";
156 class DCLZ_MM64R6_DESC {
157 dag OutOperandList = (outs GPR64Opnd:$rt);
158 dag InOperandList = (ins GPR64Opnd:$rs);
159 string AsmString = !strconcat("dclz", "\t$rt, $rs");
160 list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
161 InstrItinClass Itinerary = II_DCLZ;
163 string BaseOpcode = "dclz";
166 class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
167 uimm5_inssize_plus1, MipsIns>;
168 class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
169 class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
171 class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
173 class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
174 II_DMTC1, bitconvert>;
175 class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd,
177 class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd,
179 class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
180 II_DMFC1, bitconvert>;
181 class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd,
183 class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
184 class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
185 II_DADDIU, immSExt16, add>,
187 class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
189 class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
190 InstrItinClass Itin = NoItinerary,
191 SDPatternOperator OpNode = null_frag>
193 dag OutOperandList = (outs RO:$rd);
194 dag InOperandList = (ins RO:$rs, RO:$rt);
195 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
196 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
197 InstrItinClass Itinerary = Itin;
199 string BaseOpcode = instr_asm;
200 let isCommutable = 0;
201 let isReMaterializable = 1;
202 let TwoOperandAliasConstraint = "$rd = $rs";
204 class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
205 class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
207 class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3,
210 class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
211 InstrItinClass Itin = NoItinerary,
212 SDPatternOperator Op = null_frag> : MipsR6Inst {
213 dag OutOperandList = (outs GPROpnd:$rd);
214 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
215 string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
216 InstrItinClass Itinerary = Itin;
217 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
220 class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
221 class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
223 class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
224 class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
227 class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
228 InstrItinClass Itin> {
229 dag OutOperandList = (outs GPROpnd:$rt);
230 dag InOperandList = (ins GPROpnd:$rs);
231 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
232 bit hasSideEffects = 0;
233 list<dag> Pattern = [];
234 InstrItinClass Itinerary = Itin;
236 string BaseOpcode = instr_asm;
239 class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd, II_DSBH>;
240 class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd, II_DSHD>;
242 class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
244 SDPatternOperator OpNode = null_frag,
245 SDPatternOperator PO = null_frag> {
246 dag OutOperandList = (outs GPR64Opnd:$rt);
247 dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
248 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
249 list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
250 InstrItinClass Itinerary = itin;
252 string TwoOperandAliasConstraint = "$rs = $rt";
253 string BaseOpcode = instr_asm;
256 class SHIFT_ROTATE_REG_MM64R6<string instr_asm, InstrItinClass itin,
257 SDPatternOperator OpNode = null_frag> {
258 dag OutOperandList = (outs GPR64Opnd:$rd);
259 dag InOperandList = (ins GPR64Opnd:$rt, GPR32Opnd:$rs);
260 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
261 list<dag> Pattern = [(set GPR64Opnd:$rd,
262 (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
263 InstrItinClass Itinerary = itin;
265 string BaseOpcode = instr_asm;
268 class DSLL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll", uimm6, II_DSLL, shl,
270 class DSLL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll32", uimm5, II_DSLL32>;
271 class DSLLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsllv", II_DSLLV, shl>;
272 class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
273 class DSRA_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra", uimm6, II_DSRA, sra,
275 class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
276 class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
278 class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
280 class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
281 class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
283 class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
284 class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
286 class Load_MM64R6<string instr_asm, Operand MemOpnd, InstrItinClass itin,
287 SDPatternOperator OpNode = null_frag> {
288 dag OutOperandList = (outs GPR64Opnd:$rt);
289 dag InOperandList = (ins MemOpnd:$addr);
290 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
291 list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
292 InstrItinClass Itinerary = itin;
295 bit canFoldAsLoad = 1;
296 string BaseOpcode = instr_asm;
299 class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
300 string DecoderMethod = "DecodeMemMMImm16";
302 class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
303 string DecoderMethod = "DecodeMemMMImm12";
306 class LLD_MM64R6_DESC {
307 dag OutOperandList = (outs GPR64Opnd:$rt);
308 dag InOperandList = (ins mem_simm12:$addr);
309 string AsmString = "lld\t$rt, $addr";
310 list<dag> Pattern = [];
312 InstrItinClass Itinerary = II_LLD;
313 string BaseOpcode = "lld";
314 string DecoderMethod = "DecodeMemMMImm12";
317 class SD_MM64R6_DESC {
318 dag OutOperandList = (outs);
319 dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
320 string AsmString = "sd\t$rt, $addr";
321 list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
322 InstrItinClass Itinerary = II_SD;
325 string BaseOpcode = "sd";
326 string DecoderMethod = "DecodeMemMMImm16";
329 class DBITSWAP_MM64R6_DESC {
330 dag OutOperandList = (outs GPR64Opnd:$rd);
331 dag InOperandList = (ins GPR64Opnd:$rt);
332 string AsmString = !strconcat("dbitswap", "\t$rd, $rt");
333 list<dag> Pattern = [];
334 InstrItinClass Itinerary = II_DBITSWAP;
337 class DLSA_MM64R6_DESC {
338 dag OutOperandList = (outs GPR64Opnd:$rd);
339 dag InOperandList = (ins GPR64Opnd:$rt, GPR64Opnd:$rs, uimm2_plus1:$sa);
340 string AsmString = "dlsa\t$rt, $rs, $rd, $sa";
341 list<dag> Pattern = [];
342 InstrItinClass Itinerary = II_DLSA;
345 class LWUPC_MM64R6_DESC {
346 dag OutOperandList = (outs GPR64Opnd:$rt);
347 dag InOperandList = (ins simm19_lsl2:$offset);
348 string AsmString = "lwupc\t$rt, $offset";
349 list<dag> Pattern = [];
350 InstrItinClass Itinerary = II_LWUPC;
352 bit IsPCRelativeLoad = 1;
355 //===----------------------------------------------------------------------===//
357 // Instruction Definitions
359 //===----------------------------------------------------------------------===//
361 let DecoderNamespace = "MicroMipsR6" in {
362 def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
363 let DecoderMethod = "DecodeDAHIDATIMMR6" in {
364 def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
365 def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
367 def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
369 def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
371 def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
373 def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
375 def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
377 def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
379 def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
381 def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
383 def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
385 def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
387 def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
389 def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
391 def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
393 def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
395 def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
397 def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
399 def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
401 def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
403 def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
405 def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
407 def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
409 def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
411 def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
413 def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
415 def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
417 def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
419 def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
421 def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_ENC, DSBH_MM64R6_DESC,
423 def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_ENC, DSHD_MM64R6_DESC,
425 def DSLL_MM64R6 : StdMMR6Rel, DSLL_MM64R6_ENC, DSLL_MM64R6_DESC,
427 def DSLL32_MM64R6 : StdMMR6Rel, DSLL32_MM64R6_ENC, DSLL32_MM64R6_DESC,
429 def DSLLV_MM64R6 : StdMMR6Rel, DSLLV_MM64R6_ENC, DSLLV_MM64R6_DESC,
431 def DSRAV_MM64R6 : StdMMR6Rel, DSRAV_MM64R6_ENC, DSRAV_MM64R6_DESC,
433 def DSRA_MM64R6 : StdMMR6Rel, DSRA_MM64R6_ENC, DSRA_MM64R6_DESC,
435 def DSRA32_MM64R6 : StdMMR6Rel, DSRA32_MM64R6_ENC, DSRA32_MM64R6_DESC,
437 def DCLO_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLO_MM64R6_ENC, DCLO_MM64R6_DESC,
439 def DCLZ_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLZ_MM64R6_ENC, DCLZ_MM64R6_DESC,
441 def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_ENC, DROTR_MM64R6_DESC,
443 def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_ENC, DROTR32_MM64R6_DESC,
445 def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
447 def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
449 def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
451 def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
453 def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
455 def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
457 def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
459 def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
461 def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_ENC, DBITSWAP_MM64R6_DESC,
463 def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_ENC, DLSA_MM64R6_DESC,
465 def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_ENC, LWUPC_MM64R6_DESC,
469 let AdditionalPredicates = [InMicroMips] in
470 defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
472 //===----------------------------------------------------------------------===//
474 // Arbitrary patterns that map to one or more instructions
476 //===----------------------------------------------------------------------===//
478 def : MipsPat<(MipsLo tglobaladdr:$in),
479 (DADDIU_MM64R6 ZERO_64, tglobaladdr:$in)>, ISA_MICROMIPS64R6;
480 def : MipsPat<(MipsLo tblockaddress:$in),
481 (DADDIU_MM64R6 ZERO_64, tblockaddress:$in)>, ISA_MICROMIPS64R6;
482 def : MipsPat<(MipsLo tjumptable:$in),
483 (DADDIU_MM64R6 ZERO_64, tjumptable:$in)>, ISA_MICROMIPS64R6;
484 def : MipsPat<(MipsLo tconstpool:$in),
485 (DADDIU_MM64R6 ZERO_64, tconstpool:$in)>, ISA_MICROMIPS64R6;
486 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
487 (DADDIU_MM64R6 ZERO_64, tglobaltlsaddr:$in)>, ISA_MICROMIPS64R6;
488 def : MipsPat<(MipsLo texternalsym:$in),
489 (DADDIU_MM64R6 ZERO_64, texternalsym:$in)>, ISA_MICROMIPS64R6;
491 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
492 (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
493 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
494 (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
495 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
496 (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
497 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
498 (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
499 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
500 (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
502 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
503 (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
504 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
505 (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
508 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
509 (DROTRV_MM64R6 GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
513 def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
514 def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
515 def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
516 def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
517 def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
518 def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
521 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
522 (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
524 def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
526 //===----------------------------------------------------------------------===//
528 // Instruction aliases
530 //===----------------------------------------------------------------------===//
532 def : MipsInstAlias<"dmtc0 $rt, $rd",
533 (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
534 def : MipsInstAlias<"dmfc0 $rt, $rd",
535 (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
537 def : MipsInstAlias<"daddu $rs, $rt, $imm",
538 (DADDIU_MM64R6 GPR64Opnd:$rs,
541 0>, ISA_MICROMIPS64R6;
542 def : MipsInstAlias<"daddu $rs, $imm",
543 (DADDIU_MM64R6 GPR64Opnd:$rs,
546 0>, ISA_MICROMIPS64R6;
547 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
548 (DADDIU_MM64R6 GPR64Opnd:$rt,
550 InvertedImOperand64:$imm),
551 0>, ISA_MICROMIPS64R6;
552 def : MipsInstAlias<"dsubu $rs, $imm",
553 (DADDIU_MM64R6 GPR64Opnd:$rs,
555 InvertedImOperand64:$imm),
556 0>, ISA_MICROMIPS64R6;
557 def : MipsInstAlias<"dneg $rt, $rs",
558 (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
560 def : MipsInstAlias<"dneg $rt",
561 (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
563 def : MipsInstAlias<"dnegu $rt, $rs",
564 (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
566 def : MipsInstAlias<"dnegu $rt",
567 (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,