1 let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
2 def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
4 def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
6 def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
8 def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
11 def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
13 def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
15 def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
17 def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
20 def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
21 LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
22 def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
23 SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
24 def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
25 LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
26 def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
27 SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
29 def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
31 // FIXME: This is a required to work around the fact that these instructions
32 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
33 // fcc register set is used directly.
37 def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
39 // FIXME: This is a required to work around the fact that these instructions
40 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
41 // fcc register set is used directly.
45 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
46 BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
47 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
48 BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
49 def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
50 ROUND_W_FM_MM<0, 0x24>;
51 def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
52 ROUND_W_FM_MM<0, 0xec>;
54 def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
55 ROUND_W_FM_MM<1, 0x6c>;
56 def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
57 ROUND_W_FM_MM<1, 0x24>;
58 def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
59 ROUND_W_FM_MM<1, 0x2c>;
60 def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
61 ROUND_W_FM_MM<1, 0xec>;
62 def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
63 ROUND_W_FM_MM<1, 0xac>;
65 def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
66 fsqrt>, ROUND_W_FM_MM<1, 0x28>;
68 def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
69 ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
70 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
71 ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
73 def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
75 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
77 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
79 def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
81 def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
83 def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
85 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
88 def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
90 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
93 def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
94 ABS_FM_MM<1, 0x1>, FGR_32;
96 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
97 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
98 def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
99 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
100 def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
101 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
102 def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
103 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
105 def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
106 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
107 def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
108 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
109 def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
110 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
111 def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
112 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
113 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
114 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
115 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
116 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
118 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
120 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
122 def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
124 def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
127 def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
129 def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
131 def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
133 def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
137 let AdditionalPredicates = [InMicroMips] in {
138 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
139 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
140 def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
141 FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
142 def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
143 ROUND_W_FM_MM<0, 0x6c>;
144 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
145 fsqrt>, ROUND_W_FM_MM<0, 0x28>;
146 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
147 MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
148 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
149 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
150 let DecoderNamespace = "MicroMips" in {
151 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
153 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
155 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
157 ROUND_W_FM_MM<0b0, 0b01001000>;
158 def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
159 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
160 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
162 ROUND_W_FM_MM<0b0, 0b00001000>;
163 def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
164 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
166 let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
167 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
168 LW_FM_MM<0x2f>, FGR_32 {
169 let BaseOpcode = "LDC132";
171 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
172 LW_FM_MM<0x2e>, FGR_32;
173 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
175 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
179 multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
180 InstrItinClass itin> {
181 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
182 C_COND_FM_MM<fmt, 0> {
183 let BaseOpcode = "c.f."#NAME;
184 let isCommutable = 1;
186 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
187 C_COND_FM_MM<fmt, 1> {
188 let BaseOpcode = "c.un."#NAME;
189 let isCommutable = 1;
191 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
192 C_COND_FM_MM<fmt, 2> {
193 let BaseOpcode = "c.eq."#NAME;
194 let isCommutable = 1;
196 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
197 C_COND_FM_MM<fmt, 3> {
198 let BaseOpcode = "c.ueq."#NAME;
199 let isCommutable = 1;
201 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
202 C_COND_FM_MM<fmt, 4> {
203 let BaseOpcode = "c.olt."#NAME;
205 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
206 C_COND_FM_MM<fmt, 5> {
207 let BaseOpcode = "c.ult."#NAME;
209 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
210 C_COND_FM_MM<fmt, 6> {
211 let BaseOpcode = "c.ole."#NAME;
213 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
214 C_COND_FM_MM<fmt, 7> {
215 let BaseOpcode = "c.ule."#NAME;
217 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
218 C_COND_FM_MM<fmt, 8> {
219 let BaseOpcode = "c.sf."#NAME;
220 let isCommutable = 1;
222 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
223 C_COND_FM_MM<fmt, 9> {
224 let BaseOpcode = "c.ngle."#NAME;
226 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
227 C_COND_FM_MM<fmt, 10> {
228 let BaseOpcode = "c.seq."#NAME;
229 let isCommutable = 1;
231 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
232 C_COND_FM_MM<fmt, 11> {
233 let BaseOpcode = "c.ngl."#NAME;
235 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
236 C_COND_FM_MM<fmt, 12> {
237 let BaseOpcode = "c.lt."#NAME;
239 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
240 C_COND_FM_MM<fmt, 13> {
241 let BaseOpcode = "c.nge."#NAME;
243 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
244 C_COND_FM_MM<fmt, 14> {
245 let BaseOpcode = "c.le."#NAME;
247 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
248 C_COND_FM_MM<fmt, 15> {
249 let BaseOpcode = "c.ngt."#NAME;
253 defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
254 ISA_MIPS1_NOT_32R6_64R6;
255 defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
256 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
257 let DecoderNamespace = "Mips64" in
258 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,
259 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
261 defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
262 ISA_MIPS1_NOT_32R6_64R6;
263 defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
264 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
265 defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
266 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
268 defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">,
269 ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
272 //===----------------------------------------------------------------------===//
273 // Floating Point Patterns
274 //===----------------------------------------------------------------------===//
275 let AdditionalPredicates = [InMicroMips] in {
276 // Patterns for loads/stores with a reg+imm operand.
277 let AddedComplexity = 40 in {
278 def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
279 def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
280 def : LoadRegImmPat<LWC1_MM, f32, load>;
281 def : StoreRegImmPat<SWC1_MM, f32>;