1 def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;
2 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;
3 def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;
4 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
6 def simm9_addiusp : Operand<i32> {
7 let EncoderMethod = "getSImm9AddiuspValue";
8 let DecoderMethod = "DecodeSimm9SP";
11 def uimm3_shift : Operand<i32> {
12 let EncoderMethod = "getUImm3Mod8Encoding";
13 let DecoderMethod = "DecodePOOL16BEncodedField";
16 def simm3_lsa2 : Operand<i32> {
17 let EncoderMethod = "getSImm3Lsa2Value";
18 let DecoderMethod = "DecodeAddiur2Simm7";
21 def uimm4_andi : Operand<i32> {
22 let EncoderMethod = "getUImm4AndValue";
23 let DecoderMethod = "DecodeANDI16Imm";
26 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
28 Imm < 28 && Imm > 0);}]>;
30 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
32 def immZExtAndi16 : ImmLeaf<i32,
33 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
34 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
35 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
37 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
39 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
41 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
42 let Name = "MicroMipsMem";
43 let RenderMethod = "addMicroMipsMemOperands";
44 let ParserMethod = "parseMemOperand";
45 let PredicateMethod = "isMemWithGRPMM16Base";
48 // Define the classes of pointers used by microMIPS.
49 // The numbers must match those in MipsRegisterInfo::MipsPtrClass.
50 def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
51 def ptr_sp_rc : PointerLikeRegClass<2>;
52 def ptr_gp_rc : PointerLikeRegClass<3>;
54 class mem_mm_4_generic : Operand<i32> {
55 let PrintMethod = "printMemOperand";
56 let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
57 let OperandType = "OPERAND_MEMORY";
58 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
61 def mem_mm_4 : mem_mm_4_generic {
62 let EncoderMethod = "getMemEncodingMMImm4";
65 def mem_mm_4_lsl1 : mem_mm_4_generic {
66 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
69 def mem_mm_4_lsl2 : mem_mm_4_generic {
70 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
73 def MicroMipsMemSPAsmOperand : AsmOperandClass {
74 let Name = "MicroMipsMemSP";
75 let RenderMethod = "addMemOperands";
76 let ParserMethod = "parseMemOperand";
77 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
80 def MicroMipsMemGPAsmOperand : AsmOperandClass {
81 let Name = "MicroMipsMemGP";
82 let RenderMethod = "addMemOperands";
83 let ParserMethod = "parseMemOperand";
84 let PredicateMethod = "isMemWithSimmWordAlignedOffsetGP<9>";
87 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
88 let PrintMethod = "printMemOperand";
89 let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);
90 let OperandType = "OPERAND_MEMORY";
91 let ParserMatchClass = MicroMipsMemSPAsmOperand;
92 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
95 def mem_mm_gp_simm7_lsl2 : Operand<i32> {
96 let PrintMethod = "printMemOperand";
97 let MIOperandInfo = (ops ptr_gp_rc:$base, simm7_lsl2:$offset);
98 let OperandType = "OPERAND_MEMORY";
99 let ParserMatchClass = MicroMipsMemGPAsmOperand;
100 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
103 def mem_mm_9 : Operand<i32> {
104 let PrintMethod = "printMemOperand";
105 let MIOperandInfo = (ops ptr_rc, simm9);
106 let EncoderMethod = "getMemEncodingMMImm9";
107 let ParserMatchClass = MipsMemSimm9AsmOperand;
108 let OperandType = "OPERAND_MEMORY";
111 def mem_mm_11 : Operand<i32> {
112 let PrintMethod = "printMemOperand";
113 let MIOperandInfo = (ops GPR32, simm11);
114 let EncoderMethod = "getMemEncodingMMImm11";
115 let ParserMatchClass = MipsMemSimm11AsmOperand;
116 let OperandType = "OPERAND_MEMORY";
119 def mem_mm_12 : Operand<i32> {
120 let PrintMethod = "printMemOperand";
121 let MIOperandInfo = (ops ptr_rc, simm12);
122 let EncoderMethod = "getMemEncodingMMImm12";
123 let ParserMatchClass = MipsMemAsmOperand;
124 let OperandType = "OPERAND_MEMORY";
127 def mem_mm_16 : Operand<i32> {
128 let PrintMethod = "printMemOperand";
129 let MIOperandInfo = (ops ptr_rc, simm16);
130 let EncoderMethod = "getMemEncodingMMImm16";
131 let ParserMatchClass = MipsMemSimm16AsmOperand;
132 let OperandType = "OPERAND_MEMORY";
135 def MipsMemUimm4AsmOperand : AsmOperandClass {
136 let Name = "MemOffsetUimm4";
137 let SuperClasses = [MipsMemAsmOperand];
138 let RenderMethod = "addMemOperands";
139 let ParserMethod = "parseMemOperand";
140 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
143 def mem_mm_4sp : Operand<i32> {
144 let PrintMethod = "printMemOperand";
145 let MIOperandInfo = (ops ptr_sp_rc, uimm8);
146 let EncoderMethod = "getMemEncodingMMImm4sp";
147 let ParserMatchClass = MipsMemUimm4AsmOperand;
148 let OperandType = "OPERAND_MEMORY";
151 def jmptarget_mm : Operand<OtherVT> {
152 let EncoderMethod = "getJumpTargetOpValueMM";
155 def calltarget_mm : Operand<iPTR> {
156 let EncoderMethod = "getJumpTargetOpValueMM";
159 def brtarget7_mm : Operand<OtherVT> {
160 let EncoderMethod = "getBranchTarget7OpValueMM";
161 let OperandType = "OPERAND_PCREL";
162 let DecoderMethod = "DecodeBranchTarget7MM";
163 let ParserMatchClass = MipsJumpTargetAsmOperand;
166 def brtarget10_mm : Operand<OtherVT> {
167 let EncoderMethod = "getBranchTargetOpValueMMPC10";
168 let OperandType = "OPERAND_PCREL";
169 let DecoderMethod = "DecodeBranchTarget10MM";
170 let ParserMatchClass = MipsJumpTargetAsmOperand;
173 def brtarget_mm : Operand<OtherVT> {
174 let EncoderMethod = "getBranchTargetOpValueMM";
175 let OperandType = "OPERAND_PCREL";
176 let DecoderMethod = "DecodeBranchTargetMM";
177 let ParserMatchClass = MipsJumpTargetAsmOperand;
180 def simm23_lsl2 : Operand<i32> {
181 let EncoderMethod = "getSimm23Lsl2Encoding";
182 let DecoderMethod = "DecodeSimm23Lsl2";
185 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
186 RegisterOperand RO> :
187 InstSE<(outs), (ins RO:$rs, opnd:$offset),
188 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
190 let isTerminator = 1;
191 let hasDelaySlot = 0;
195 let canFoldAsLoad = 1 in
196 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
197 Operand MemOpnd, InstrItinClass Itin> :
198 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
199 !strconcat(opstr, "\t$rt, $addr"),
200 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
202 let DecoderMethod = "DecodeMemMMImm12";
203 string Constraints = "$src = $rt";
206 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
207 Operand MemOpnd, InstrItinClass Itin>:
208 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
209 !strconcat(opstr, "\t$rt, $addr"),
210 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
211 let DecoderMethod = "DecodeMemMMImm12";
214 /// A register pair used by movep instruction.
215 def MovePRegPairAsmOperand : AsmOperandClass {
216 let Name = "MovePRegPair";
217 let ParserMethod = "parseMovePRegPair";
218 let PredicateMethod = "isMovePRegPair";
221 def movep_regpair : Operand<i32> {
222 let EncoderMethod = "getMovePRegPairOpValue";
223 let ParserMatchClass = MovePRegPairAsmOperand;
224 let PrintMethod = "printRegisterList";
225 let DecoderMethod = "DecodeMovePRegPair";
226 let MIOperandInfo = (ops ptr_rc, ptr_rc);
229 class MovePMM16<string opstr, RegisterOperand RO> :
230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
231 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
233 let isReMaterializable = 1;
236 /// A register pair used by load/store pair instructions.
237 def RegPairAsmOperand : AsmOperandClass {
238 let Name = "RegPair";
239 let ParserMethod = "parseRegisterPair";
240 let PredicateMethod = "isRegPair";
243 def regpair : Operand<i32> {
244 let EncoderMethod = "getRegisterPairOpValue";
245 let ParserMatchClass = RegPairAsmOperand;
246 let PrintMethod = "printRegisterPair";
247 let DecoderMethod = "DecodeRegPairOperand";
248 let MIOperandInfo = (ops ptr_rc, ptr_rc);
251 class StorePairMM<string opstr, ComplexPattern Addr = addr>
252 : InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr),
253 !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
254 let DecoderMethod = "DecodeMemMMImm12";
258 class LoadPairMM<string opstr, ComplexPattern Addr = addr>
259 : InstSE<(outs regpair:$rt), (ins mem_simm12:$addr),
260 !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
261 let DecoderMethod = "DecodeMemMMImm12";
265 class LLBaseMM<string opstr, RegisterOperand RO> :
266 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
267 !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
268 let DecoderMethod = "DecodeMemMMImm12";
272 class LLEBaseMM<string opstr, RegisterOperand RO> :
273 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
274 !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
275 let DecoderMethod = "DecodeMemMMImm9";
279 class SCBaseMM<string opstr, RegisterOperand RO> :
280 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
281 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
282 let DecoderMethod = "DecodeMemMMImm12";
284 let Constraints = "$rt = $dst";
287 class SCEBaseMM<string opstr, RegisterOperand RO> :
288 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
289 !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
290 let DecoderMethod = "DecodeMemMMImm9";
292 let Constraints = "$rt = $dst";
295 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
296 InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
297 InstSE<(outs RO:$rt), (ins MO:$addr),
298 !strconcat(opstr, "\t$rt, $addr"),
299 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
300 let DecoderMethod = "DecodeMemMMImm12";
301 let canFoldAsLoad = 1;
305 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
306 InstrItinClass Itin = NoItinerary,
307 SDPatternOperator OpNode = null_frag> :
308 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
309 !strconcat(opstr, "\t$rd, $rs, $rt"),
310 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
311 let isCommutable = isComm;
314 class AndImmMM16<string opstr, RegisterOperand RO,
315 InstrItinClass Itin = NoItinerary> :
316 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
317 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
319 class LogicRMM16<string opstr, RegisterOperand RO,
320 InstrItinClass Itin = NoItinerary,
321 SDPatternOperator OpNode = null_frag> :
322 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
323 !strconcat(opstr, "\t$rt, $rs"),
324 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
325 let isCommutable = 1;
326 let Constraints = "$rt = $dst";
329 class NotMM16<string opstr, RegisterOperand RO> :
330 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
331 !strconcat(opstr, "\t$rt, $rs"),
332 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
334 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
335 InstrItinClass Itin = NoItinerary> :
336 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
337 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
339 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
340 InstrItinClass Itin, Operand MemOpnd> :
341 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
342 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
343 let DecoderMethod = "DecodeMemMMImm4";
344 let canFoldAsLoad = 1;
348 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
349 SDPatternOperator OpNode, InstrItinClass Itin,
351 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
352 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
353 let DecoderMethod = "DecodeMemMMImm4";
357 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
359 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
360 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
361 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
362 let canFoldAsLoad = 1;
366 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
368 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
369 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
370 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
374 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
376 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
377 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
378 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
379 let canFoldAsLoad = 1;
383 class AddImmUR2<string opstr, RegisterOperand RO> :
384 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
385 !strconcat(opstr, "\t$rd, $rs, $imm"),
386 [], II_ADDIU, FrmR> {
387 let isCommutable = 1;
390 class AddImmUS5<string opstr, RegisterOperand RO> :
391 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
392 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
393 let Constraints = "$rd = $dst";
396 class AddImmUR1SP<string opstr, RegisterOperand RO> :
397 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
398 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
400 class AddImmUSP<string opstr> :
401 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
402 !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
404 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
405 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
406 [], II_MFHI_MFLO, FrmR> {
408 let hasSideEffects = 0;
411 class MoveMM16<string opstr, RegisterOperand RO>
412 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
413 !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
414 let isReMaterializable = 1;
417 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
418 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
419 !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
420 let isReMaterializable = 1;
423 // 16-bit Jump and Link (Call)
424 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
425 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
426 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
428 let hasDelaySlot = 1;
433 class JumpRegMM16<string opstr, RegisterOperand RO> :
434 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
436 let hasDelaySlot = 1;
438 let isIndirectBranch = 1;
441 // Base class for JRADDIUSP instruction.
442 class JumpRAddiuStackMM16 :
443 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
444 [], II_JRADDIUSP, FrmR> {
445 let isTerminator = 1;
448 let isIndirectBranch = 1;
451 // 16-bit Jump and Link (Call) - Short Delay Slot
452 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
453 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
454 [], II_JALRS, FrmR> {
456 let hasDelaySlot = 1;
460 // 16-bit Jump Register Compact - No delay slot
461 class JumpRegCMM16<string opstr, RegisterOperand RO> :
462 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
464 let isTerminator = 1;
467 let isIndirectBranch = 1;
470 // Break16 and Sdbbp16
471 class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
472 MicroMipsInst16<(outs), (ins uimm4:$code_),
473 !strconcat(opstr, "\t$code_"),
476 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
477 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
478 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
480 let isTerminator = 1;
481 let hasDelaySlot = 1;
485 // MicroMIPS Jump and Link (Call) - Short Delay Slot
486 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
487 class JumpLinkMM<string opstr, DAGOperand opnd> :
488 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
489 [], II_JALS, FrmJ, opstr> {
490 let DecoderMethod = "DecodeJumpTargetMM";
493 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
494 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
497 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
498 RegisterOperand RO> :
499 InstSE<(outs), (ins RO:$rs, opnd:$offset),
500 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
503 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
504 SDPatternOperator OpNode = null_frag> :
505 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
506 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
508 class PrefetchIndexed<string opstr> :
509 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
510 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
512 class AddImmUPC<string opstr, RegisterOperand RO> :
513 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
514 !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
516 /// A list of registers used by load/store multiple instructions.
517 def RegListAsmOperand : AsmOperandClass {
518 let Name = "RegList";
519 let ParserMethod = "parseRegisterList";
522 def reglist : Operand<i32> {
523 let EncoderMethod = "getRegisterListOpValue";
524 let ParserMatchClass = RegListAsmOperand;
525 let PrintMethod = "printRegisterList";
526 let DecoderMethod = "DecodeRegListOperand";
529 def RegList16AsmOperand : AsmOperandClass {
530 let Name = "RegList16";
531 let ParserMethod = "parseRegisterList";
532 let PredicateMethod = "isRegList16";
533 let RenderMethod = "addRegListOperands";
536 def reglist16 : Operand<i32> {
537 let EncoderMethod = "getRegisterListOpValue16";
538 let DecoderMethod = "DecodeRegListOperand16";
539 let PrintMethod = "printRegisterList";
540 let ParserMatchClass = RegList16AsmOperand;
543 class StoreMultMM<string opstr,
544 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
545 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
546 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
547 let DecoderMethod = "DecodeMemMMImm12";
551 class LoadMultMM<string opstr,
552 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
554 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
555 let DecoderMethod = "DecodeMemMMImm12";
559 class StoreMultMM16<string opstr,
560 InstrItinClass Itin = NoItinerary,
561 ComplexPattern Addr = addr> :
562 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
563 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
564 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
568 class LoadMultMM16<string opstr,
569 InstrItinClass Itin = NoItinerary,
570 ComplexPattern Addr = addr> :
571 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
572 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
573 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
577 class UncondBranchMM16<string opstr> :
578 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
579 !strconcat(opstr, "\t$offset"),
582 let isTerminator = 1;
584 let hasDelaySlot = 1;
585 let Predicates = [RelocPIC, InMicroMips];
589 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
590 ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
591 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
592 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
593 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
594 ISA_MICROMIPS_NOT_32R6_64R6;
595 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
596 ISA_MICROMIPS_NOT_32R6_64R6;
597 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
598 ISA_MICROMIPS_NOT_32R6_64R6;
599 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
600 SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
601 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
602 SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
604 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
605 ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
606 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
607 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
608 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
609 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
610 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
611 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
612 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
613 LOAD_STORE_FM_MM16<0x1a>;
614 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
615 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
616 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
617 II_SH, mem_mm_4_lsl1>,
618 LOAD_STORE_FM_MM16<0x2a>;
619 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
620 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
621 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
622 LOAD_GP_FM_MM16<0x19>;
623 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
624 LOAD_STORE_SP_FM_MM16<0x12>;
625 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
626 LOAD_STORE_SP_FM_MM16<0x32>;
627 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
628 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
629 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
630 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
631 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
632 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
633 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
634 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
635 def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
637 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
638 ISA_MICROMIPS32_NOT_MIPS32R6;
639 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
640 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
641 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
642 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
643 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
644 BEQNEZ_FM_MM16<0x23>;
645 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
646 BEQNEZ_FM_MM16<0x2b>;
647 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
648 def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
649 ISA_MICROMIPS_NOT_32R6_64R6;
650 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
651 ISA_MICROMIPS_NOT_32R6_64R6;
653 let DecoderNamespace = "MicroMips" in {
654 /// Load and Store Instructions - multiple
655 def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
656 ISA_MICROMIPS32_NOT_MIPS32R6;
657 def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
658 ISA_MICROMIPS32_NOT_MIPS32R6;
659 let AdditionalPredicates = [InMicroMips] in {
660 def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
661 "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
662 POOL32A_CFTC2_FM_MM<0b1100110100>;
663 def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
664 "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
665 POOL32A_CFTC2_FM_MM<0b1101110100>;
669 class WaitMM<string opstr> :
670 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
671 II_WAIT, FrmOther, opstr>;
673 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
675 /// Compact Branch Instructions
676 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
677 COMPACT_BRANCH_FM_MM<0x7>;
678 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
679 COMPACT_BRANCH_FM_MM<0x5>;
681 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
682 /// Arithmetic Instructions (ALU Immediate)
683 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
685 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
687 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
689 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
691 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
693 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
694 or>, ADDI_FM_MM<0x14>;
695 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
696 immZExt16, xor>, ADDI_FM_MM<0x1c>;
697 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
699 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
702 /// Arithmetic Instructions (3-Operand, R-Type)
703 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
705 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
707 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
709 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
711 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
713 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
714 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
716 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
718 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
720 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
722 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
723 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
725 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
727 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
728 MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
729 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
730 MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
732 /// Arithmetic Instructions with PC and Immediate
733 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
735 /// Shift Instructions
736 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
738 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
740 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
742 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
744 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
746 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
748 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
750 list<dag> Pattern = [(set GPR32Opnd:$rd,
751 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
753 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
754 SRLV_FM_MM<0xd0, 0> {
755 list<dag> Pattern = [(set GPR32Opnd:$rd,
756 (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
759 /// Load and Store Instructions - aligned
760 let DecoderMethod = "DecodeMemMMImm16" in {
761 def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>,
762 MMRel, LW_FM_MM<0x7>;
763 def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>,
764 MMRel, LW_FM_MM<0x5>;
765 def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
766 addrDefault>, MMRel, LW_FM_MM<0xf>;
767 def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
768 MMRel, LW_FM_MM<0xd>;
769 def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>;
770 def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel,
772 def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel,
774 def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
778 let DecoderMethod = "DecodeMemMMImm9" in {
779 def LBE_MM : Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
780 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
781 def LBuE_MM : Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
782 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
783 def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, II_LHE>,
784 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
785 def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>,
786 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
787 def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>,
788 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
789 def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, II_SBE>,
790 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
791 def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag, II_SHE>,
792 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
793 def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag, II_SWE>,
794 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
797 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
799 /// Load and Store Instructions - unaligned
800 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12, II_LWL>,
802 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12, II_LWR>,
804 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12, II_SWL>,
806 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
808 let DecoderMethod = "DecodeMemMMImm9" in {
809 def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
810 II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
811 def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
812 II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
813 def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
815 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
816 def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
818 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
821 /// Load and Store Instructions - multiple
822 def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
823 def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>;
825 /// Load and Store Pair Instructions
826 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
827 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
829 /// Load and Store multiple pseudo Instructions
830 class LoadWordMultMM<string instr_asm > :
831 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
832 !strconcat(instr_asm, "\t$rt, $addr")> ;
834 class StoreWordMultMM<string instr_asm > :
835 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
836 !strconcat(instr_asm, "\t$rt, $addr")> ;
839 def SWM_MM : StoreWordMultMM<"swm">;
840 def LWM_MM : LoadWordMultMM<"lwm">;
843 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
844 NoItinerary>, ADD_FM_MM<0, 0x58>;
845 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
846 NoItinerary>, ADD_FM_MM<0, 0x18>;
847 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
848 CMov_F_I_FM_MM<0x25>;
849 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
852 /// Move to/from HI/LO
853 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
855 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
857 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
859 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
862 /// Multiply Add/Sub Instructions
863 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
864 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
865 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
866 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
869 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
871 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
874 /// Sign Ext In Register Instructions.
875 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
876 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
877 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
878 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
880 /// Word Swap Bytes Within Halfwords
881 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
882 SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
883 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
884 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
885 immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
886 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
887 MipsIns>, EXT_FM_MM<0x0c>;
889 /// Jump Instructions
890 let DecoderMethod = "DecodeJumpTargetMM" in {
891 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
893 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
894 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
896 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
897 ISA_MICROMIPS32_NOT_MIPS32R6;
898 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
900 /// Jump Instructions - Short Delay Slot
901 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
902 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
904 /// Branch Instructions
905 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
907 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
909 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
911 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
913 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
915 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
917 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
919 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
922 /// Branch Instructions - Short Delay Slot
923 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
924 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
925 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
926 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
928 /// Control Instructions
929 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
930 def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM;
931 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
932 def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
933 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
934 def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
935 def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
936 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
938 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
941 /// Trap Instructions
942 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>;
943 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>;
944 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
946 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>;
947 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
949 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>;
951 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>;
952 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>;
953 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
955 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>;
956 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
958 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>;
960 /// Load-linked, Store-conditional
961 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
962 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
964 def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
965 def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
967 let DecoderMethod = "DecodeCacheOpMM" in {
968 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
969 CACHE_PREF_FM_MM<0x08, 0x6>;
970 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
971 CACHE_PREF_FM_MM<0x18, 0x2>;
974 let DecoderMethod = "DecodePrefeOpMM" in {
975 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
976 CACHE_PREFE_FM_MM<0x18, 0x2>;
977 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
978 CACHE_PREFE_FM_MM<0x18, 0x3>;
980 def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
981 def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
982 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
984 def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>;
985 def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>;
986 def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>;
987 def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>;
989 def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM;
991 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
994 def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6;
996 let DecoderNamespace = "MicroMips" in {
997 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
998 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
999 def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
1000 mem_simm12>, LL_FM_MM<0xe>,
1001 ISA_MICROMIPS32_NOT_MIPS32R6;
1004 //===----------------------------------------------------------------------===//
1005 // MicroMips arbitrary patterns that map to one or more instructions
1006 //===----------------------------------------------------------------------===//
1008 def : MipsPat<(i32 immLi16:$imm),
1009 (LI16_MM immLi16:$imm)>;
1011 let AdditionalPredicates = [InMicroMips] in
1012 defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
1014 let Predicates = [InMicroMips] in {
1015 def : MipsPat<(i32 immLi16:$imm),
1016 (LI16_MM immLi16:$imm)>;
1017 def : MipsPat<(i32 immSExt16:$imm),
1018 (ADDiu_MM ZERO, immSExt16:$imm)>;
1019 def : MipsPat<(i32 immZExt16:$imm),
1020 (ORi_MM ZERO, immZExt16:$imm)>;
1022 def : MipsPat<(not GPRMM16:$in),
1023 (NOT16_MM GPRMM16:$in)>;
1024 def : MipsPat<(not GPR32:$in),
1025 (NOR_MM GPR32Opnd:$in, ZERO)>;
1027 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
1028 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
1029 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1030 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
1031 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1032 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
1034 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1035 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
1036 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1037 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
1039 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
1040 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
1041 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1042 (SLL_MM GPR32:$src, immZExt5:$imm)>;
1043 def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1044 (SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
1046 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
1047 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
1048 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
1049 (SRL_MM GPR32:$src, immZExt5:$imm)>;
1050 def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1051 (SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
1053 def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1054 (SRA_MM GPR32:$src, immZExt5:$imm)>;
1055 def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1056 (SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
1058 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1059 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
1060 def : MipsPat<(store GPR32:$src, addr:$addr),
1061 (SW_MM GPR32:$src, addr:$addr)>;
1063 def : MipsPat<(load addrimm4lsl2:$addr),
1064 (LW16_MM addrimm4lsl2:$addr)>;
1065 def : MipsPat<(load addr:$addr),
1066 (LW_MM addr:$addr)>;
1067 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1068 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
1070 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1071 (TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
1072 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1073 (TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
1076 let AddedComplexity = 40 in {
1077 def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
1078 (LH_MM addrRegImm:$a)>;
1080 def : MipsPat<(atomic_load_16 addr:$a),
1082 def : MipsPat<(i32 (extloadi16 addr:$src)),
1083 (LHu_MM addr:$src)>;
1085 defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
1088 defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
1089 defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
1090 defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
1091 defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
1092 defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
1094 //===----------------------------------------------------------------------===//
1095 // MicroMips instruction aliases
1096 //===----------------------------------------------------------------------===//
1098 class UncondBranchMMPseudo<string opstr> :
1099 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1100 !strconcat(opstr, "\t$offset")>;
1102 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1104 let Predicates = [InMicroMips] in {
1105 def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
1106 II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1107 def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
1108 II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1110 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
1111 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
1112 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
1113 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
1114 def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
1115 def : MipsInstAlias<"teq $rs, $rt",
1116 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1117 def : MipsInstAlias<"tge $rs, $rt",
1118 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1119 def : MipsInstAlias<"tgeu $rs, $rt",
1120 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1121 def : MipsInstAlias<"tlt $rs, $rt",
1122 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1123 def : MipsInstAlias<"tltu $rs, $rt",
1124 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1125 def : MipsInstAlias<"tne $rs, $rt",
1126 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1127 def : MipsInstAlias<
1128 "sgt $rd, $rs, $rt",
1129 (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1130 def : MipsInstAlias<
1132 (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1133 def : MipsInstAlias<
1134 "sgtu $rd, $rs, $rt",
1135 (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1136 def : MipsInstAlias<
1138 (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1139 def : MipsInstAlias<"slt $rs, $rt, $imm",
1140 (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
1141 simm32_relaxed:$imm), 0>;
1142 def : MipsInstAlias<"sltu $rs, $rt, $imm",
1143 (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
1144 simm32_relaxed:$imm), 0>;
1145 def : MipsInstAlias<"sll $rd, $rt, $rs",
1146 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1147 def : MipsInstAlias<"sra $rd, $rt, $rs",
1148 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1149 def : MipsInstAlias<"srl $rd, $rt, $rs",
1150 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1151 def : MipsInstAlias<"sll $rd, $rt",
1152 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1153 def : MipsInstAlias<"sra $rd, $rt",
1154 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1155 def : MipsInstAlias<"srl $rd, $rt",
1156 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1157 def : MipsInstAlias<"sll $rd, $shamt",
1158 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1159 def : MipsInstAlias<"sra $rd, $shamt",
1160 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1161 def : MipsInstAlias<"srl $rd, $shamt",
1162 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1163 def : MipsInstAlias<"rotr $rt, $imm",
1164 (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
1165 def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
1166 def : MipsInstAlias<"and $rs, $rt, $imm",
1167 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1168 def : MipsInstAlias<"and $rs, $imm",
1169 (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1170 def : MipsInstAlias<"or $rs, $rt, $imm",
1171 (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1172 def : MipsInstAlias<"or $rs, $imm",
1173 (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1174 def : MipsInstAlias<"xor $rs, $rt, $imm",
1175 (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1176 def : MipsInstAlias<"xor $rs, $imm",
1177 (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1178 def : MipsInstAlias<"not $rt, $rs",
1179 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1180 def : MipsInstAlias<"not $rt",
1181 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
1182 def : MipsInstAlias<"bnez $rs,$offset",
1183 (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1184 def : MipsInstAlias<"beqz $rs,$offset",
1185 (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1186 def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1187 ISA_MIPS32R2_NOT_32R6_64R6;
1188 def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1189 ISA_MIPS32R2_NOT_32R6_64R6;