contrib/llvm/lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 // The overall idea of the PredicateControl class is to chop the Predicates list
  19 // into subsets that are usually overridden independently. This allows
  20 // subclasses to partially override the predicates of their superclasses without
  21 // having to re-add all the existing predicates.
  22 class PredicateControl {
  23   // Predicates for the encoding scheme in use such as HasStdEnc
  24   list<Predicate> EncodingPredicates = [];
  25   // Predicates for the GPR size such as IsGP64bit
  26   list<Predicate> GPRPredicates = [];
  27   // Predicates for the PTR size such as IsPTR64bit
  28   list<Predicate> PTRPredicates = [];
  29   // Predicates for the FGR size and layout such as IsFP64bit
  30   list<Predicate> FGRPredicates = [];
  31   // Predicates for the instruction group membership such as ISA's and ASE's
  32   list<Predicate> InsnPredicates = [];
  33   // Predicate for marking the instruction as usable in hard-float mode only.
  34   list<Predicate> HardFloatPredicate = [];
  35   // Predicates for anything else
  36   list<Predicate> AdditionalPredicates = [];
  37   list<Predicate> Predicates = !listconcat(EncodingPredicates,
  38                                            GPRPredicates,
  39                                            PTRPredicates,
  40                                            FGRPredicates,
  41                                            InsnPredicates,
  42                                            HardFloatPredicate,
  43                                            AdditionalPredicates);
  44 }
  45
  46 // Like Requires<> but for the AdditionalPredicates list
  47 class AdditionalRequires<list<Predicate> preds> {
  48   list<Predicate> AdditionalPredicates = preds;
  49 }
  50
  51 //===----------------------------------------------------------------------===//
  52 // Register File, Calling Conv, Instruction Descriptions
  53 //===----------------------------------------------------------------------===//
  54
  55 include "MipsRegisterInfo.td"
  56 include "MipsSchedule.td"
  57 include "MipsInstrInfo.td"
  58 include "MipsCallingConv.td"
  59
  60 // Avoid forward declaration issues.
  61 include "MipsScheduleP5600.td"
  62 include "MipsScheduleGeneric.td"
  63
  64 def MipsInstrInfo : InstrInfo;
  65
  66 //===----------------------------------------------------------------------===//
  67 // Mips Subtarget features                                                    //
  68 //===----------------------------------------------------------------------===//
  69
  70 def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
  71                                 "Disable SVR4-style position-independent code">;
  72 def FeaturePTR64Bit    : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
  73                                 "Pointers are 64-bit wide">;
  74 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  75                                 "General Purpose Registers are 64-bit wide">;
  76 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  77                                 "Support 64-bit FP registers">;
  78 def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
  79                                 "Support for FPXX">;
  80 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  81                                 "IEEE 754-2008 NaN encoding">;
  82 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  83                                 "true", "Only supports single precision float">;
  84 def FeatureSoftFloat   : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
  85                                 "Does not support floating point instructions">;
  86 def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
  87                               "Disable odd numbered single-precision "
  88                               "registers">;
  89 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  90                                 "true", "Enable vector FPU instructions">;
  91 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
  92                                 "Mips I ISA Support [highly experimental]">;
  93 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
  94                                 "Mips II ISA Support [highly experimental]",
  95                                 [FeatureMips1]>;
  96 def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
  97                                 "Subset of MIPS-III that is also in MIPS32 "
  98                                 "[highly experimental]">;
  99 def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
 100                                 "Subset of MIPS-III that is also in MIPS32r2 "
 101                                 "[highly experimental]">;
 102 def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
 103                                 "MIPS III ISA Support [highly experimental]",
 104                                 [FeatureMips2, FeatureMips3_32,
 105                                  FeatureMips3_32r2, FeatureGP64Bit,
 106                                  FeatureFP64Bit]>;
 107 def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
 108                                 "Subset of MIPS-IV that is also in MIPS32 "
 109                                 "[highly experimental]">;
 110 def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
 111                                 "Subset of MIPS-IV that is also in MIPS32r2 "
 112                                 "[highly experimental]">;
 113 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
 114                                 "Mips4", "MIPS IV ISA Support",
 115                                 [FeatureMips3, FeatureMips4_32,
 116                                  FeatureMips4_32r2]>;
 117 def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
 118                                 "Subset of MIPS-V that is also in MIPS32r2 "
 119                                 "[highly experimental]">;
 120 def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
 121                                 "MIPS V ISA Support [highly experimental]",
 122                                 [FeatureMips4, FeatureMips5_32r2]>;
 123 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
 124                                 "Mips32 ISA Support",
 125                                 [FeatureMips2, FeatureMips3_32,
 126                                  FeatureMips4_32]>;
 127 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
 128                                 "Mips32r2", "Mips32r2 ISA Support",
 129                                 [FeatureMips3_32r2, FeatureMips4_32r2,
 130                                  FeatureMips5_32r2, FeatureMips32]>;
 131 def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
 132                                 "Mips32r3", "Mips32r3 ISA Support",
 133                                 [FeatureMips32r2]>;
 134 def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
 135                                 "Mips32r5", "Mips32r5 ISA Support",
 136                                 [FeatureMips32r3]>;
 137 def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
 138                                 "Mips32r6",
 139                                 "Mips32r6 ISA Support [experimental]",
 140                                 [FeatureMips32r5, FeatureFP64Bit,
 141                                  FeatureNaN2008]>;
 142 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 143                                 "Mips64", "Mips64 ISA Support",
 144                                 [FeatureMips5, FeatureMips32]>;
 145 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
 146                                 "Mips64r2", "Mips64r2 ISA Support",
 147                                 [FeatureMips64, FeatureMips32r2]>;
 148 def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
 149                                 "Mips64r3", "Mips64r3 ISA Support",
 150                                 [FeatureMips64r2, FeatureMips32r3]>;
 151 def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
 152                                 "Mips64r5", "Mips64r5 ISA Support",
 153                                 [FeatureMips64r3, FeatureMips32r5]>;
 154 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
 155                                 "Mips64r6",
 156                                 "Mips64r6 ISA Support [experimental]",
 157                                 [FeatureMips32r6, FeatureMips64r5,
 158                                  FeatureNaN2008]>;
 159 def FeatureSym32       : SubtargetFeature<"sym32", "HasSym32", "true",
 160                                           "Symbols are 32 bit on Mips64">;
 161
 162 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
 163                                       "Mips16 mode">;
 164
 165 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 166 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
 167                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 168 def FeatureDSPR3
 169     : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
 170                        [ FeatureDSP, FeatureDSPR2 ]>;
 171
 172 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 173
 174 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 175
 176 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
 177                                          "microMips mode">;
 178
 179 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
 180                                 "true", "Octeon cnMIPS Support",
 181                                 [FeatureMips64r2]>;
 182
 183 def FeatureUseTCCInDIV : SubtargetFeature<
 184                                "use-tcc-in-div",
 185                                "UseTCCInDIV", "false",
 186                                "Force the assembler to use trapping">;
 187
 188 def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
 189                                     "Disable 4-operand madd.fmt and related instructions">;
 190
 191 def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
 192
 193 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
 194                                         "Disable use of the jal instruction">;
 195
 196 //===----------------------------------------------------------------------===//
 197 // Mips processors supported.
 198 //===----------------------------------------------------------------------===//
 199
 200 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 201                                  "MipsSubtarget::CPU::P5600",
 202                                  "The P5600 Processor", [FeatureMips32r5]>;
 203
 204 class Proc<string Name, list<SubtargetFeature> Features>
 205  : ProcessorModel<Name, MipsGenericModel, Features>;
 206
 207 def : Proc<"mips1", [FeatureMips1]>;
 208 def : Proc<"mips2", [FeatureMips2]>;
 209 def : Proc<"mips32", [FeatureMips32]>;
 210 def : Proc<"mips32r2", [FeatureMips32r2]>;
 211 def : Proc<"mips32r3", [FeatureMips32r3]>;
 212 def : Proc<"mips32r5", [FeatureMips32r5]>;
 213 def : Proc<"mips32r6", [FeatureMips32r6]>;
 214
 215 def : Proc<"mips3", [FeatureMips3]>;
 216 def : Proc<"mips4", [FeatureMips4]>;
 217 def : Proc<"mips5", [FeatureMips5]>;
 218 def : Proc<"mips64", [FeatureMips64]>;
 219 def : Proc<"mips64r2", [FeatureMips64r2]>;
 220 def : Proc<"mips64r3", [FeatureMips64r3]>;
 221 def : Proc<"mips64r5", [FeatureMips64r5]>;
 222 def : Proc<"mips64r6", [FeatureMips64r6]>;
 223 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 224 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 225
 226 def MipsAsmParser : AsmParser {
 227   let ShouldEmitMatchRegisterName = 0;
 228 }
 229
 230 def MipsAsmParserVariant : AsmParserVariant {
 231   int Variant = 0;
 232
 233   // Recognize hard coded registers.
 234   string RegisterPrefix = "$";
 235 }
 236
 237 def Mips : Target {
 238   let InstructionSet = MipsInstrInfo;
 239   let AssemblyParsers = [MipsAsmParser];
 240   let AssemblyParserVariants = [MipsAsmParserVariant];
 241 }