contrib/llvm/lib/Target/Mips/Mips.td

   1 //===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Register File, Calling Conv, Instruction Descriptions
  20 //===----------------------------------------------------------------------===//
  21
  22 include "MipsRegisterInfo.td"
  23 include "MipsSchedule.td"
  24 include "MipsInstrInfo.td"
  25 include "MipsCallingConv.td"
  26
  27 def MipsInstrInfo : InstrInfo;
  28
  29 //===----------------------------------------------------------------------===//
  30 // Mips Subtarget features                                                    //
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  34                                 "General Purpose Registers are 64-bit wide.">;
  35 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  36                                 "Support 64-bit FP registers.">;
  37 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  38                                 "true", "Only supports single precision float">;
  39 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
  40                                 "Mips1 ISA Support">;
  41 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
  42                                 "Mips2 ISA Support">;
  43 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  44                                 "Enable o32 ABI">;
  45 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  46                                 "Enable eabi ABI">;
  47 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  48                                 "true", "Enable vector FPU instructions.">;
  49 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  50                                 "Enable 'signext in register' instructions.">;
  51 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  52                                 "Enable 'conditional move' instructions.">;
  53 def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
  54                                 "Enable 'multiply add/sub' instructions.">;
  55 def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
  56                                 "Enable 'min/max' instructions.">;
  57 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  58                                 "Enable 'byte/half swap' instructions.">;
  59 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  60                                 "Enable 'count leading bits' instructions.">;
  61
  62 //===----------------------------------------------------------------------===//
  63 // Mips processors supported.
  64 //===----------------------------------------------------------------------===//
  65
  66 class Proc<string Name, list<SubtargetFeature> Features>
  67  : Processor<Name, MipsGenericItineraries, Features>;
  68
  69 def : Proc<"mips1", [FeatureMips1]>;
  70 def : Proc<"r2000", [FeatureMips1]>;
  71 def : Proc<"r3000", [FeatureMips1]>;
  72
  73 def : Proc<"mips2", [FeatureMips2]>;
  74 def : Proc<"r6000", [FeatureMips2]>;
  75
  76 // Allegrex is a 32bit subset of r4000, both for interger and fp registers,
  77 // but much more similar to Mips2 than Mips3. It also contains some of
  78 // Mips32/Mips32r2 instructions and a custom vector fpu processor.
  79 def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
  80       FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
  81       FeatureMinMax, FeatureSwap, FeatureBitCount]>;
  82
  83 def Mips : Target {
  84   let InstructionSet = MipsInstrInfo;
  85 }