1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #include "Mips16ISelLowering.h"
14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 #define DEBUG_TYPE "mips-lower"
27 static cl::opt<bool> DontExpandCondPseudos16(
28 "mips16-dont-expand-cond-pseudo",
30 cl::desc("Dont expand conditional move related "
31 "pseudos for Mips 16"),
35 struct Mips16Libcall {
36 RTLIB::Libcall Libcall;
39 bool operator<(const Mips16Libcall &RHS) const {
40 return std::strcmp(Name, RHS.Name) < 0;
44 struct Mips16IntrinsicHelperType{
48 bool operator<(const Mips16IntrinsicHelperType &RHS) const {
49 return std::strcmp(Name, RHS.Name) < 0;
51 bool operator==(const Mips16IntrinsicHelperType &RHS) const {
52 return std::strcmp(Name, RHS.Name) == 0;
57 // Libcalls for which no helper is generated. Sorted by name for binary search.
58 static const Mips16Libcall HardFloatLibCalls[] = {
59 { RTLIB::ADD_F64, "__mips16_adddf3" },
60 { RTLIB::ADD_F32, "__mips16_addsf3" },
61 { RTLIB::DIV_F64, "__mips16_divdf3" },
62 { RTLIB::DIV_F32, "__mips16_divsf3" },
63 { RTLIB::OEQ_F64, "__mips16_eqdf2" },
64 { RTLIB::OEQ_F32, "__mips16_eqsf2" },
65 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
66 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
67 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
68 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
69 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
70 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
71 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
72 { RTLIB::OGE_F64, "__mips16_gedf2" },
73 { RTLIB::OGE_F32, "__mips16_gesf2" },
74 { RTLIB::OGT_F64, "__mips16_gtdf2" },
75 { RTLIB::OGT_F32, "__mips16_gtsf2" },
76 { RTLIB::OLE_F64, "__mips16_ledf2" },
77 { RTLIB::OLE_F32, "__mips16_lesf2" },
78 { RTLIB::OLT_F64, "__mips16_ltdf2" },
79 { RTLIB::OLT_F32, "__mips16_ltsf2" },
80 { RTLIB::MUL_F64, "__mips16_muldf3" },
81 { RTLIB::MUL_F32, "__mips16_mulsf3" },
82 { RTLIB::UNE_F64, "__mips16_nedf2" },
83 { RTLIB::UNE_F32, "__mips16_nesf2" },
84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
85 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
86 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
87 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
88 { RTLIB::SUB_F64, "__mips16_subdf3" },
89 { RTLIB::SUB_F32, "__mips16_subsf3" },
90 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
91 { RTLIB::UO_F64, "__mips16_unorddf2" },
92 { RTLIB::UO_F32, "__mips16_unordsf2" }
95 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
96 {"__fixunsdfsi", "__mips16_call_stub_2" },
97 {"ceil", "__mips16_call_stub_df_2"},
98 {"ceilf", "__mips16_call_stub_sf_1"},
99 {"copysign", "__mips16_call_stub_df_10"},
100 {"copysignf", "__mips16_call_stub_sf_5"},
101 {"cos", "__mips16_call_stub_df_2"},
102 {"cosf", "__mips16_call_stub_sf_1"},
103 {"exp2", "__mips16_call_stub_df_2"},
104 {"exp2f", "__mips16_call_stub_sf_1"},
105 {"floor", "__mips16_call_stub_df_2"},
106 {"floorf", "__mips16_call_stub_sf_1"},
107 {"log2", "__mips16_call_stub_df_2"},
108 {"log2f", "__mips16_call_stub_sf_1"},
109 {"nearbyint", "__mips16_call_stub_df_2"},
110 {"nearbyintf", "__mips16_call_stub_sf_1"},
111 {"rint", "__mips16_call_stub_df_2"},
112 {"rintf", "__mips16_call_stub_sf_1"},
113 {"sin", "__mips16_call_stub_df_2"},
114 {"sinf", "__mips16_call_stub_sf_1"},
115 {"sqrt", "__mips16_call_stub_df_2"},
116 {"sqrtf", "__mips16_call_stub_sf_1"},
117 {"trunc", "__mips16_call_stub_df_2"},
118 {"truncf", "__mips16_call_stub_sf_1"},
121 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
122 const MipsSubtarget &STI)
123 : MipsTargetLowering(TM, STI) {
125 // Set up the register classes
126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
128 if (!TM.Options.UseSoftFloat)
129 setMips16HardFloatLibCalls();
131 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
132 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
133 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
134 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
143 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
145 setOperationAction(ISD::ROTR, MVT::i32, Expand);
146 setOperationAction(ISD::ROTR, MVT::i64, Expand);
147 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
150 computeRegisterProperties();
153 const MipsTargetLowering *
154 llvm::createMips16TargetLowering(MipsTargetMachine &TM,
155 const MipsSubtarget &STI) {
156 return new Mips16TargetLowering(TM, STI);
160 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
167 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *BB) const {
169 switch (MI->getOpcode()) {
171 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
173 return emitSel16(Mips::BeqzRxImm16, MI, BB);
175 return emitSel16(Mips::BnezRxImm16, MI, BB);
176 case Mips::SelTBteqZCmpi:
177 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
178 case Mips::SelTBteqZSlti:
179 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
180 case Mips::SelTBteqZSltiu:
181 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
182 case Mips::SelTBtneZCmpi:
183 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
184 case Mips::SelTBtneZSlti:
185 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
186 case Mips::SelTBtneZSltiu:
187 return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
188 case Mips::SelTBteqZCmp:
189 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
190 case Mips::SelTBteqZSlt:
191 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
192 case Mips::SelTBteqZSltu:
193 return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
194 case Mips::SelTBtneZCmp:
195 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
196 case Mips::SelTBtneZSlt:
197 return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
198 case Mips::SelTBtneZSltu:
199 return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
200 case Mips::BteqzT8CmpX16:
201 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
202 case Mips::BteqzT8SltX16:
203 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
204 case Mips::BteqzT8SltuX16:
205 // TBD: figure out a way to get this or remove the instruction
207 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
208 case Mips::BtnezT8CmpX16:
209 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
210 case Mips::BtnezT8SltX16:
211 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
212 case Mips::BtnezT8SltuX16:
213 // TBD: figure out a way to get this or remove the instruction
215 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
216 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
217 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
218 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
219 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
220 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
221 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
222 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
223 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
224 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
225 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
226 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
227 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
229 case Mips::SltCCRxRy16:
230 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
232 case Mips::SltiCCRxImmX16:
233 return emitFEXT_CCRXI16_ins
234 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
235 case Mips::SltiuCCRxImmX16:
236 return emitFEXT_CCRXI16_ins
237 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
238 case Mips::SltuCCRxRy16:
239 return emitFEXT_CCRX16_ins
240 (Mips::SltuRxRy16, MI, BB);
244 bool Mips16TargetLowering::isEligibleForTailCallOptimization(
245 const CCState &CCInfo, unsigned NextStackOffset,
246 const MipsFunctionInfo &FI) const {
247 // No tail call optimization for mips16.
251 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
252 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
253 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
254 "Array not sorted!");
255 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
256 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
259 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
260 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
264 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
265 // cleaner way to do all of this but it will have to wait until the traditional
266 // gcc mechanism is completed.
268 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
269 // have either arguments or returned values placed in floating point registers,
270 // we use a set of helper functions. (This includes functions which return type
271 // complex which on Mips are returned in a pair of floating point registers).
273 // This is an encoding that we inherited from gcc.
274 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
275 // floating point argument registers 1,2 only when the first and optionally
276 // the second arguments are float (sf) or double (df).
277 // For Mips16 we are only concerned with the situations where floating point
278 // arguments are being passed in floating point registers by the ABI, because
279 // Mips16 mode code cannot execute floating point instructions to load those
280 // values and hence helper functions are needed.
281 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
282 // the helper function suffixs for these are:
283 // 0, 1, 5, 9, 2, 6, 10
284 // this suffix can then be calculated as follows:
285 // for a given argument Arg:
286 // Arg1x, Arg2x = 1 : Arg is sf
288 // 0: Arg is neither sf or df
289 // So this stub is the string for number Arg1x + Arg2x*4.
290 // However not all numbers between 0 and 10 are possible, we check anyway and
291 // assert if the impossible exists.
294 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
295 (ArgListTy &Args) const {
296 unsigned int resultNum = 0;
297 if (Args.size() >= 1) {
298 Type *t = Args[0].Ty;
299 if (t->isFloatTy()) {
302 else if (t->isDoubleTy()) {
307 if (Args.size() >=2) {
308 Type *t = Args[1].Ty;
309 if (t->isFloatTy()) {
312 else if (t->isDoubleTy()) {
321 // prefixs are attached to stub numbers depending on the return type .
322 // return type: float sf_
324 // single complex sc_
325 // double complext dc_
329 // The full name of a helper function is__mips16_call_stub +
330 // return type dependent prefix + stub number
333 // This is something that probably should be in a different source file and
334 // perhaps done differently but my main purpose is to not waste runtime
335 // on something that we can enumerate in the source. Another possibility is
336 // to have a python script to generate these mapping tables. This will do
337 // for now. There are a whole series of helper function mapping arrays, one
338 // for each return type class as outlined above. There there are 11 possible
339 // entries. Ones with 0 are ones which should never be selected
341 // All the arrays are similar except for ones which return neither
342 // sf, df, sc, dc, in which only care about ones which have sf or df as a
345 #define P_ "__mips16_call_stub_"
346 #define MAX_STUB_NUMBER 10
347 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
350 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
354 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
358 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
362 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
366 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
372 const char* Mips16TargetLowering::
373 getMips16HelperFunction
374 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
375 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
377 const unsigned int maxStubNum = 10;
378 assert(stubNum <= maxStubNum);
379 const bool validStubNum[maxStubNum+1] =
380 {true, true, true, false, false, true, true, false, false, true, true};
381 assert(validStubNum[stubNum]);
384 if (RetTy->isFloatTy()) {
385 result = sfMips16Helper[stubNum];
387 else if (RetTy ->isDoubleTy()) {
388 result = dfMips16Helper[stubNum];
390 else if (RetTy->isStructTy()) {
391 // check if it's complex
392 if (RetTy->getNumContainedTypes() == 2) {
393 if ((RetTy->getContainedType(0)->isFloatTy()) &&
394 (RetTy->getContainedType(1)->isFloatTy())) {
395 result = scMips16Helper[stubNum];
397 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
398 (RetTy->getContainedType(1)->isDoubleTy())) {
399 result = dcMips16Helper[stubNum];
402 llvm_unreachable("Uncovered condition");
406 llvm_unreachable("Uncovered condition");
414 result = vMips16Helper[stubNum];
420 void Mips16TargetLowering::
421 getOpndList(SmallVectorImpl<SDValue> &Ops,
422 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
423 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
424 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
425 SelectionDAG &DAG = CLI.DAG;
426 MachineFunction &MF = DAG.getMachineFunction();
427 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
428 const char* Mips16HelperFunction = nullptr;
429 bool NeedMips16Helper = false;
431 if (Subtarget.inMips16HardFloat()) {
433 // currently we don't have symbols tagged with the mips16 or mips32
434 // qualifier so we will assume that we don't know what kind it is.
435 // and generate the helper
437 bool LookupHelper = true;
438 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
439 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
441 if (std::binary_search(std::begin(HardFloatLibCalls),
442 std::end(HardFloatLibCalls), Find))
443 LookupHelper = false;
445 const char *Symbol = S->getSymbol();
446 Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
447 const Mips16HardFloatInfo::FuncSignature *Signature =
448 Mips16HardFloatInfo::findFuncSignature(Symbol);
449 if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
450 FuncInfo->StubsNeeded.end()))) {
451 FuncInfo->StubsNeeded[Symbol] = Signature;
453 // S2 is normally saved if the stub is for a function which
454 // returns a float or double value and is not otherwise. This is
455 // because more work is required after the function the stub
456 // is calling completes, and so the stub cannot directly return
457 // and the stub has no stack space to store the return address so
458 // S2 is used for that purpose.
459 // In order to take advantage of not saving S2, we need to also
460 // optimize the call in the stub and this requires some further
461 // functionality in MipsAsmPrinter which we don't have yet.
462 // So for now we always save S2. The optimization will be done
463 // in a follow-on patch.
465 if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
466 FuncInfo->setSaveS2();
468 // one more look at list of intrinsics
469 const Mips16IntrinsicHelperType *Helper =
470 std::lower_bound(std::begin(Mips16IntrinsicHelper),
471 std::end(Mips16IntrinsicHelper), IntrinsicFind);
472 if (Helper != std::end(Mips16IntrinsicHelper) &&
473 *Helper == IntrinsicFind) {
474 Mips16HelperFunction = Helper->Helper;
475 NeedMips16Helper = true;
476 LookupHelper = false;
480 } else if (GlobalAddressSDNode *G =
481 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
482 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
483 G->getGlobal()->getName().data() };
485 if (std::binary_search(std::begin(HardFloatLibCalls),
486 std::end(HardFloatLibCalls), Find))
487 LookupHelper = false;
490 Mips16HelperFunction =
491 getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
494 SDValue JumpTarget = Callee;
496 // T9 should contain the address of the callee function if
497 // -reloction-model=pic or it is an indirect call.
498 if (IsPICCall || !GlobalOrExternal) {
499 unsigned V0Reg = Mips::V0;
500 if (NeedMips16Helper) {
501 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
502 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
503 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
504 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG,
505 MipsII::MO_GOT, Chain,
506 FuncInfo->callPtrInfo(S->getSymbol()));
508 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
511 Ops.push_back(JumpTarget);
513 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
514 InternalLinkage, CLI, Callee, Chain);
517 MachineBasicBlock *Mips16TargetLowering::
518 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
519 if (DontExpandCondPseudos16)
521 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
522 DebugLoc DL = MI->getDebugLoc();
523 // To "insert" a SELECT_CC instruction, we actually have to insert the
524 // diamond control-flow pattern. The incoming instruction knows the
525 // destination vreg to set, the condition code register to branch on, the
526 // true/false values to select between, and a branch opcode to use.
527 const BasicBlock *LLVM_BB = BB->getBasicBlock();
528 MachineFunction::iterator It = BB;
535 // bNE r1, r0, copy1MBB
536 // fallthrough --> copy0MBB
537 MachineBasicBlock *thisMBB = BB;
538 MachineFunction *F = BB->getParent();
539 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
540 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
541 F->insert(It, copy0MBB);
542 F->insert(It, sinkMBB);
544 // Transfer the remainder of BB and its successor edges to sinkMBB.
545 sinkMBB->splice(sinkMBB->begin(), BB,
546 std::next(MachineBasicBlock::iterator(MI)), BB->end());
547 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
549 // Next, add the true and fallthrough blocks as its successors.
550 BB->addSuccessor(copy0MBB);
551 BB->addSuccessor(sinkMBB);
553 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
558 // # fallthrough to sinkMBB
561 // Update machine-CFG edges
562 BB->addSuccessor(sinkMBB);
565 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
569 BuildMI(*BB, BB->begin(), DL,
570 TII->get(Mips::PHI), MI->getOperand(0).getReg())
571 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
572 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
574 MI->eraseFromParent(); // The pseudo instruction is gone now.
578 MachineBasicBlock *Mips16TargetLowering::emitSelT16
579 (unsigned Opc1, unsigned Opc2,
580 MachineInstr *MI, MachineBasicBlock *BB) const {
581 if (DontExpandCondPseudos16)
583 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
584 DebugLoc DL = MI->getDebugLoc();
585 // To "insert" a SELECT_CC instruction, we actually have to insert the
586 // diamond control-flow pattern. The incoming instruction knows the
587 // destination vreg to set, the condition code register to branch on, the
588 // true/false values to select between, and a branch opcode to use.
589 const BasicBlock *LLVM_BB = BB->getBasicBlock();
590 MachineFunction::iterator It = BB;
597 // bNE r1, r0, copy1MBB
598 // fallthrough --> copy0MBB
599 MachineBasicBlock *thisMBB = BB;
600 MachineFunction *F = BB->getParent();
601 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
602 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
603 F->insert(It, copy0MBB);
604 F->insert(It, sinkMBB);
606 // Transfer the remainder of BB and its successor edges to sinkMBB.
607 sinkMBB->splice(sinkMBB->begin(), BB,
608 std::next(MachineBasicBlock::iterator(MI)), BB->end());
609 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
611 // Next, add the true and fallthrough blocks as its successors.
612 BB->addSuccessor(copy0MBB);
613 BB->addSuccessor(sinkMBB);
615 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
616 .addReg(MI->getOperand(4).getReg());
617 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
621 // # fallthrough to sinkMBB
624 // Update machine-CFG edges
625 BB->addSuccessor(sinkMBB);
628 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
632 BuildMI(*BB, BB->begin(), DL,
633 TII->get(Mips::PHI), MI->getOperand(0).getReg())
634 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
635 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
637 MI->eraseFromParent(); // The pseudo instruction is gone now.
642 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
643 (unsigned Opc1, unsigned Opc2,
644 MachineInstr *MI, MachineBasicBlock *BB) const {
645 if (DontExpandCondPseudos16)
647 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
648 DebugLoc DL = MI->getDebugLoc();
649 // To "insert" a SELECT_CC instruction, we actually have to insert the
650 // diamond control-flow pattern. The incoming instruction knows the
651 // destination vreg to set, the condition code register to branch on, the
652 // true/false values to select between, and a branch opcode to use.
653 const BasicBlock *LLVM_BB = BB->getBasicBlock();
654 MachineFunction::iterator It = BB;
661 // bNE r1, r0, copy1MBB
662 // fallthrough --> copy0MBB
663 MachineBasicBlock *thisMBB = BB;
664 MachineFunction *F = BB->getParent();
665 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
666 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
667 F->insert(It, copy0MBB);
668 F->insert(It, sinkMBB);
670 // Transfer the remainder of BB and its successor edges to sinkMBB.
671 sinkMBB->splice(sinkMBB->begin(), BB,
672 std::next(MachineBasicBlock::iterator(MI)), BB->end());
673 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
675 // Next, add the true and fallthrough blocks as its successors.
676 BB->addSuccessor(copy0MBB);
677 BB->addSuccessor(sinkMBB);
679 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
680 .addImm(MI->getOperand(4).getImm());
681 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
685 // # fallthrough to sinkMBB
688 // Update machine-CFG edges
689 BB->addSuccessor(sinkMBB);
692 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
696 BuildMI(*BB, BB->begin(), DL,
697 TII->get(Mips::PHI), MI->getOperand(0).getReg())
698 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
699 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
701 MI->eraseFromParent(); // The pseudo instruction is gone now.
707 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
709 MachineBasicBlock *BB) const {
710 if (DontExpandCondPseudos16)
712 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
713 unsigned regX = MI->getOperand(0).getReg();
714 unsigned regY = MI->getOperand(1).getReg();
715 MachineBasicBlock *target = MI->getOperand(2).getMBB();
716 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
718 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
719 MI->eraseFromParent(); // The pseudo instruction is gone now.
723 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
724 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
725 MachineInstr *MI, MachineBasicBlock *BB) const {
726 if (DontExpandCondPseudos16)
728 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
729 unsigned regX = MI->getOperand(0).getReg();
730 int64_t imm = MI->getOperand(1).getImm();
731 MachineBasicBlock *target = MI->getOperand(2).getMBB();
735 else if ((!ImmSigned && isUInt<16>(imm)) ||
736 (ImmSigned && isInt<16>(imm)))
739 llvm_unreachable("immediate field not usable");
740 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
742 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
743 MI->eraseFromParent(); // The pseudo instruction is gone now.
747 static unsigned Mips16WhichOp8uOr16simm
748 (unsigned shortOp, unsigned longOp, int64_t Imm) {
751 else if (isInt<16>(Imm))
754 llvm_unreachable("immediate field not usable");
757 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
759 MachineInstr *MI, MachineBasicBlock *BB) const {
760 if (DontExpandCondPseudos16)
762 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
763 unsigned CC = MI->getOperand(0).getReg();
764 unsigned regX = MI->getOperand(1).getReg();
765 unsigned regY = MI->getOperand(2).getReg();
766 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg(
768 BuildMI(*BB, MI, MI->getDebugLoc(),
769 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
770 MI->eraseFromParent(); // The pseudo instruction is gone now.
774 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
775 unsigned SltiOpc, unsigned SltiXOpc,
776 MachineInstr *MI, MachineBasicBlock *BB )const {
777 if (DontExpandCondPseudos16)
779 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
780 unsigned CC = MI->getOperand(0).getReg();
781 unsigned regX = MI->getOperand(1).getReg();
782 int64_t Imm = MI->getOperand(2).getImm();
783 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
784 BuildMI(*BB, MI, MI->getDebugLoc(),
785 TII->get(SltOpc)).addReg(regX).addImm(Imm);
786 BuildMI(*BB, MI, MI->getDebugLoc(),
787 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
788 MI->eraseFromParent(); // The pseudo instruction is gone now.