1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
13 #include "Mips16InstrInfo.h"
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "mips16-instrinfo"
32 Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
33 : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
35 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
45 int &FrameIndex) const {
49 /// isStoreToStackSlot - If the specified machine instruction is a direct
50 /// store to a stack slot, return the virtual or physical register number of
51 /// the source reg along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than storing to the stack slot.
54 unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
55 int &FrameIndex) const {
59 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I,
61 const DebugLoc &DL, unsigned DestReg,
62 unsigned SrcReg, bool KillSrc) const {
65 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
66 Mips::GPR32RegClass.contains(SrcReg))
67 Opc = Mips::MoveR3216;
68 else if (Mips::GPR32RegClass.contains(DestReg) &&
69 Mips::CPU16RegsRegClass.contains(SrcReg))
70 Opc = Mips::Move32R16;
71 else if ((SrcReg == Mips::HI0) &&
72 (Mips::CPU16RegsRegClass.contains(DestReg)))
73 Opc = Mips::Mfhi16, SrcReg = 0;
75 else if ((SrcReg == Mips::LO0) &&
76 (Mips::CPU16RegsRegClass.contains(DestReg)))
77 Opc = Mips::Mflo16, SrcReg = 0;
80 assert(Opc && "Cannot copy registers");
82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
85 MIB.addReg(DestReg, RegState::Define);
88 MIB.addReg(SrcReg, getKillRegState(KillSrc));
91 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I,
93 unsigned SrcReg, bool isKill, int FI,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI,
96 int64_t Offset) const {
98 if (I != MBB.end()) DL = I->getDebugLoc();
99 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
101 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
102 Opc = Mips::SwRxSpImmX16;
103 assert(Opc && "Register class not handled!");
104 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
105 addFrameIndex(FI).addImm(Offset)
109 void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I,
111 unsigned DestReg, int FI,
112 const TargetRegisterClass *RC,
113 const TargetRegisterInfo *TRI,
114 int64_t Offset) const {
116 if (I != MBB.end()) DL = I->getDebugLoc();
117 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
121 Opc = Mips::LwRxSpImmX16;
122 assert(Opc && "Register class not handled!");
123 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
127 bool Mips16InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
128 MachineBasicBlock &MBB = *MI.getParent();
129 switch (MI.getDesc().getOpcode()) {
133 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
137 MBB.erase(MI.getIterator());
141 /// GetOppositeBranchOpc - Return the inverse of the specified
142 /// opcode, e.g. turning BEQ to BNE.
143 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
145 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
146 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
147 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
148 case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
149 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
150 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
151 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
152 case Mips::Btnez16: return Mips::Bteqz16;
153 case Mips::BtnezX16: return Mips::BteqzX16;
154 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
155 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
156 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
157 case Mips::Bteqz16: return Mips::Btnez16;
158 case Mips::BteqzX16: return Mips::BtnezX16;
159 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
160 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
161 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
162 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
163 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
164 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
166 llvm_unreachable("Illegal opcode!");
169 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
170 const std::vector<CalleeSavedInfo> &CSI,
171 unsigned Flags = 0) {
172 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
173 // Add the callee-saved register as live-in. Do not add if the register is
174 // RA and return address is taken, because it has already been added in
175 // method MipsTargetLowering::lowerRETURNADDR.
176 // It's killed at the spill, unless the register is RA and return address
178 unsigned Reg = CSI[e-i-1].getReg();
183 MIB.addReg(Reg, Flags);
188 llvm_unreachable("unexpected mips16 callee saved register");
193 // Adjust SP by FrameSize bytes. Save RA, S0, S1
194 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
195 MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator I) const {
198 MachineFunction &MF = *MBB.getParent();
199 MachineFrameInfo &MFI = MF.getFrameInfo();
200 const BitVector Reserved = RI.getReservedRegs(MF);
201 bool SaveS2 = Reserved[Mips::S2];
202 MachineInstrBuilder MIB;
203 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
204 MIB = BuildMI(MBB, I, DL, get(Opc));
205 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
206 addSaveRestoreRegs(MIB, CSI);
208 MIB.addReg(Mips::S2);
209 if (isUInt<11>(FrameSize))
210 MIB.addImm(FrameSize);
212 int Base = 2040; // should create template function like isUInt that
213 // returns largest possible n bit unsigned integer
214 int64_t Remainder = FrameSize - Base;
216 if (isInt<16>(-Remainder))
217 BuildAddiuSpImm(MBB, I, -Remainder);
219 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
223 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
224 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
225 MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator I) const {
227 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
228 MachineFunction *MF = MBB.getParent();
229 MachineFrameInfo &MFI = MF->getFrameInfo();
230 const BitVector Reserved = RI.getReservedRegs(*MF);
231 bool SaveS2 = Reserved[Mips::S2];
232 MachineInstrBuilder MIB;
233 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
234 Mips::Restore16:Mips::RestoreX16;
236 if (!isUInt<11>(FrameSize)) {
237 unsigned Base = 2040;
238 int64_t Remainder = FrameSize - Base;
239 FrameSize = Base; // should create template function like isUInt that
240 // returns largest possible n bit unsigned integer
242 if (isInt<16>(Remainder))
243 BuildAddiuSpImm(MBB, I, Remainder);
245 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
247 MIB = BuildMI(MBB, I, DL, get(Opc));
248 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
249 addSaveRestoreRegs(MIB, CSI, RegState::Define);
251 MIB.addReg(Mips::S2, RegState::Define);
252 MIB.addImm(FrameSize);
255 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
256 // This can only be called at times that we know that there is at least one free
258 // This is clearly safe at prologue and epilogue.
260 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
261 MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator I,
263 unsigned Reg1, unsigned Reg2) const {
268 // add reg1, reg1, reg2
272 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
273 MIB1.addImm(Amount).addImm(-1);
274 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
275 MIB2.addReg(Mips::SP, RegState::Kill);
276 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
278 MIB3.addReg(Reg2, RegState::Kill);
279 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
281 MIB4.addReg(Reg1, RegState::Kill);
284 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
285 unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator I) const {
287 llvm_unreachable("adjust stack pointer amount exceeded");
290 /// Adjust SP by Amount bytes.
291 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
292 MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator I) const {
297 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
298 BuildAddiuSpImm(MBB, I, Amount);
300 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
303 /// This function generates the sequence of instructions needed to get the
304 /// result of adding register REG and immediate IMM.
305 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
306 MachineBasicBlock &MBB,
307 MachineBasicBlock::iterator II,
309 unsigned &NewImm) const {
311 // given original instruction is:
312 // Instr rx, T[offset] where offset is too big.
314 // lo = offset & 0xFFFF
315 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
317 // let T = temporary register
323 int32_t lo = Imm & 0xFFFF;
328 rs.enterBasicBlock(MBB);
331 // We need to know which registers can be used, in the case where there
332 // are not enough free registers. We exclude all registers that
333 // are used in the instruction that we are helping.
334 // // Consider all allocatable registers in the register class initially
335 BitVector Candidates =
337 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
338 // Exclude all the registers being used by the instruction.
339 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
340 MachineOperand &MO = II->getOperand(i);
341 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
342 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
343 Candidates.reset(MO.getReg());
346 // If the same register was used and defined in an instruction, then
347 // it will not be in the list of candidates.
349 // we need to analyze the instruction that we are helping.
350 // we need to know if it defines register x but register x is not
351 // present as an operand of the instruction. this tells
352 // whether the register is live before the instruction. if it's not
353 // then we don't need to save it in case there are no free registers.
355 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
356 MachineOperand &MO = II->getOperand(i);
357 if (MO.isReg() && MO.isDef()) {
358 DefReg = MO.getReg();
363 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
364 Available &= Candidates;
366 // we use T0 for the first register, if we need to save something away.
367 // we use T1 for the second register, if we need to save something away.
369 unsigned FirstRegSaved =0, SecondRegSaved=0;
370 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
372 Reg = Available.find_first();
375 Reg = Candidates.find_first();
376 Candidates.reset(Reg);
379 FirstRegSavedTo = Mips::T0;
380 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
384 Available.reset(Reg);
385 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
387 if (FrameReg == Mips::SP) {
388 SpReg = Available.find_first();
390 SpReg = Candidates.find_first();
391 // Candidates.reset(SpReg); // not really needed
392 if (DefReg!= SpReg) {
393 SecondRegSaved = SpReg;
394 SecondRegSavedTo = Mips::T1;
397 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
400 Available.reset(SpReg);
401 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
402 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
406 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
407 .addReg(Reg, RegState::Kill);
408 if (FirstRegSaved || SecondRegSaved) {
411 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
413 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
418 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
419 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
420 Opc == Mips::Bimm16 ||
421 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
422 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
423 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
424 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
425 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
426 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
427 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
428 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
429 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
430 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
433 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
434 MachineBasicBlock::iterator I,
435 unsigned Opc) const {
436 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
439 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
440 if (validSpImm8(Imm))
441 return get(Mips::AddiuSpImm16);
443 return get(Mips::AddiuSpImmX16);
446 void Mips16InstrInfo::BuildAddiuSpImm
447 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
449 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
452 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
453 return new Mips16InstrInfo(STI);
456 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
459 case Mips::LbRxRyOffMemX16:
460 case Mips::LbuRxRyOffMemX16:
461 case Mips::LhRxRyOffMemX16:
462 case Mips::LhuRxRyOffMemX16:
463 case Mips::SbRxRyOffMemX16:
464 case Mips::ShRxRyOffMemX16:
465 case Mips::LwRxRyOffMemX16:
466 case Mips::SwRxRyOffMemX16:
467 case Mips::SwRxSpImmX16:
468 case Mips::LwRxSpImmX16:
469 return isInt<16>(Amount);
470 case Mips::AddiuRxRyOffMemX16:
471 if ((Reg == Mips::PC) || (Reg == Mips::SP))
472 return isInt<16>(Amount);
473 return isInt<15>(Amount);
475 llvm_unreachable("unexpected Opcode in validImmediate");
478 /// Measure the specified inline asm to determine an approximation of its
480 /// Comments (which run till the next SeparatorString or newline) do not
481 /// count as an instruction.
482 /// Any other non-whitespace text is considered an instruction, with
483 /// multiple instructions separated by SeparatorString or newlines.
484 /// Variable-length instructions are not handled here; this function
485 /// may be overloaded in the target code to do that.
486 /// We implement the special case of the .space directive taking only an
487 /// integer argument, which is the size in bytes. This is used for creating
488 /// inline code spacing for testing purposes using inline assembly.
490 unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
491 const MCAsmInfo &MAI) const {
493 // Count the number of instructions in the asm.
494 bool atInsnStart = true;
496 for (; *Str; ++Str) {
497 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
498 strlen(MAI.getSeparatorString())) == 0)
500 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
501 if (strncmp(Str, ".space", 6)==0) {
503 Sz = strtol(Str+6, &EStr, 10);
504 while (isspace(*EStr)) ++EStr;
506 DEBUG(dbgs() << "parsed .space " << Sz << '\n');
510 Length += MAI.getMaxInstLength();
513 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
514 MAI.getCommentString().size()) == 0)