1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
17 // Reencoded: jr -> jalr
18 // Reencoded: jr.hb -> jalr.hb
20 def brtarget21 : Operand<OtherVT> {
21 let EncoderMethod = "getBranchTarget21OpValue";
22 let OperandType = "OPERAND_PCREL";
23 let DecoderMethod = "DecodeBranchTarget21";
24 let ParserMatchClass = MipsJumpTargetAsmOperand;
27 def brtarget26 : Operand<OtherVT> {
28 let EncoderMethod = "getBranchTarget26OpValue";
29 let OperandType = "OPERAND_PCREL";
30 let DecoderMethod = "DecodeBranchTarget26";
31 let ParserMatchClass = MipsJumpTargetAsmOperand;
34 def jmpoffset16 : Operand<OtherVT> {
35 let EncoderMethod = "getJumpOffset16OpValue";
36 let ParserMatchClass = MipsJumpTargetAsmOperand;
39 def calloffset16 : Operand<iPTR> {
40 let EncoderMethod = "getJumpOffset16OpValue";
41 let ParserMatchClass = MipsJumpTargetAsmOperand;
44 //===----------------------------------------------------------------------===//
46 // Instruction Encodings
48 //===----------------------------------------------------------------------===//
50 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
51 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
52 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
53 class AUI_ENC : AUI_FM;
54 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
56 class BAL_ENC : BAL_FM;
57 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
58 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
59 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
60 DecodeDisambiguates<"AddiGroupBranch">;
61 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
62 DecodeDisambiguatedBy<"DaddiGroupBranch">;
63 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
64 DecodeDisambiguates<"DaddiGroupBranch">;
65 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
66 DecodeDisambiguatedBy<"DaddiGroupBranch">;
68 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
69 DecodeDisambiguates<"BgtzlGroupBranch">;
70 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
71 DecodeDisambiguatedBy<"BlezlGroupBranch">;
72 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
73 DecodeDisambiguatedBy<"BlezGroupBranch">;
74 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
75 DecodeDisambiguates<"BlezlGroupBranch">;
76 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
77 DecodeDisambiguatedBy<"BgtzGroupBranch">;
79 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
80 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
81 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
82 DecodeDisambiguatedBy<"BgtzGroupBranch">;
84 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
85 DecodeDisambiguatedBy<"BlezlGroupBranch">;
86 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
87 DecodeDisambiguates<"BgtzGroupBranch">;
88 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
89 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
91 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
92 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
93 DecodeDisambiguates<"BlezGroupBranch">;
94 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
96 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
97 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
98 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
99 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
101 class DVP_ENC : COP0_EVP_DVP_FM<0b1>;
102 class EVP_ENC : COP0_EVP_DVP_FM<0b0>;
104 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
105 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
106 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
107 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
108 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
109 DecodeDisambiguatedBy<"BlezGroupBranch">;
110 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
111 DecodeDisambiguatedBy<"DaddiGroupBranch">;
112 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
113 DecodeDisambiguatedBy<"AddiGroupBranch">;
114 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
115 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
116 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
117 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
118 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
119 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
120 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
121 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
123 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
124 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
125 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
126 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
128 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
129 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
131 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
132 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
134 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
135 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
137 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
138 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
139 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
140 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
142 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
143 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
144 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
145 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
147 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
148 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
149 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
150 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
152 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
153 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
154 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
155 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
157 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
158 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
160 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
161 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
162 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
163 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
165 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
167 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
168 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
170 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
171 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
173 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
175 //===----------------------------------------------------------------------===//
177 // Instruction Multiclasses
179 //===----------------------------------------------------------------------===//
181 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
182 RegisterOperand FGROpnd,
184 SDPatternOperator Op = null_frag> {
185 dag OutOperandList = (outs FGRCCOpnd:$fd);
186 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
187 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
188 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
190 InstrItinClass Itinerary = Itin;
193 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
194 RegisterOperand FGROpnd, InstrItinClass Itin>{
195 let AdditionalPredicates = [NotInMicroMips] in {
196 def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
197 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>,
198 MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
199 ISA_MIPS32R6, HARDFLOAT;
200 def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
201 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>,
202 MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
203 ISA_MIPS32R6, HARDFLOAT;
204 def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
205 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin,
207 MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
208 ISA_MIPS32R6, HARDFLOAT;
209 def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
211 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin,
213 MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
214 ISA_MIPS32R6, HARDFLOAT;
215 def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
216 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin,
218 MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
219 ISA_MIPS32R6, HARDFLOAT;
220 def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
222 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin,
224 MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
225 ISA_MIPS32R6, HARDFLOAT;
226 def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
227 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin,
229 MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
230 ISA_MIPS32R6, HARDFLOAT;
231 def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
233 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin,
235 MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
236 ISA_MIPS32R6, HARDFLOAT;
237 def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
239 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>,
240 MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
241 ISA_MIPS32R6, HARDFLOAT;
242 def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
244 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>,
245 MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
246 ISA_MIPS32R6, HARDFLOAT;
247 def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
249 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>,
250 MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
251 ISA_MIPS32R6, HARDFLOAT;
252 def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
253 FIELD_CMP_COND_SUEQ>,
254 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>,
255 MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
256 ISA_MIPS32R6, HARDFLOAT;
257 def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
259 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>,
260 MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
261 ISA_MIPS32R6, HARDFLOAT;
262 def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
263 FIELD_CMP_COND_SULT>,
264 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>,
265 MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
266 ISA_MIPS32R6, HARDFLOAT;
267 def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
269 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>,
270 MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
271 ISA_MIPS32R6, HARDFLOAT;
272 def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
273 FIELD_CMP_COND_SULE>,
274 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>,
275 MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
276 ISA_MIPS32R6, HARDFLOAT;
280 //===----------------------------------------------------------------------===//
282 // Instruction Descriptions
284 //===----------------------------------------------------------------------===//
286 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
287 Operand ImmOpnd, InstrItinClass itin>
288 : MipsR6Arch<instr_asm> {
289 dag OutOperandList = (outs GPROpnd:$rs);
290 dag InOperandList = (ins ImmOpnd:$imm);
291 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
292 list<dag> Pattern = [];
293 InstrItinClass Itinerary = itin;
296 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
298 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
299 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
301 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
302 Operand ImmOpnd, InstrItinClass itin>
303 : MipsR6Arch<instr_asm> {
304 dag OutOperandList = (outs GPROpnd:$rd);
305 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
306 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
307 list<dag> Pattern = [];
308 InstrItinClass Itinerary = itin;
311 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;
313 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
314 InstrItinClass itin = NoItinerary>
315 : MipsR6Arch<instr_asm> {
316 dag OutOperandList = (outs GPROpnd:$rs);
317 dag InOperandList = (ins simm16:$imm);
318 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
319 list<dag> Pattern = [];
320 InstrItinClass Itinerary = itin;
323 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
324 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
326 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
327 InstrItinClass itin = NoItinerary>
328 : MipsR6Arch<instr_asm> {
329 dag OutOperandList = (outs GPROpnd:$rt);
330 dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
331 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
332 list<dag> Pattern = [];
333 InstrItinClass Itinerary = itin;
336 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
338 class BRANCH_DESC_BASE {
340 bit isTerminator = 1;
341 bit hasDelaySlot = 0;
345 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
346 MipsR6Arch<instr_asm> {
347 dag InOperandList = (ins opnd:$offset);
348 dag OutOperandList = (outs);
349 string AsmString = !strconcat(instr_asm, "\t$offset");
351 InstrItinClass Itinerary = II_BC;
355 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
356 RegisterOperand GPROpnd> : BRANCH_DESC_BASE,
357 MipsR6Arch<instr_asm> {
358 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
359 dag OutOperandList = (outs);
360 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
361 list<Register> Defs = [AT];
362 InstrItinClass Itinerary = II_BCCC;
363 bit hasForbiddenSlot = 1;
367 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
368 RegisterOperand GPROpnd>
369 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
370 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
371 dag OutOperandList = (outs);
372 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
373 list<Register> Defs = [AT];
374 InstrItinClass Itinerary = II_BCCZC;
375 bit hasForbiddenSlot = 1;
379 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
380 RegisterOperand GPROpnd>
381 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
382 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
383 dag OutOperandList = (outs);
384 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
385 list<Register> Defs = [AT];
386 InstrItinClass Itinerary = II_BCCZC;
387 bit hasForbiddenSlot = 1;
391 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
393 bit hasDelaySlot = 1;
394 list<Register> Defs = [RA];
398 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
400 list<Register> Defs = [RA];
401 InstrItinClass Itinerary = II_BALC;
405 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
406 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
407 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
408 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
409 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
411 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
412 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
414 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
415 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
417 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
418 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
420 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
421 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
423 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
424 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
425 dag OutOperandList = (outs);
426 string AsmString = instr_asm;
427 bit hasDelaySlot = 1;
428 InstrItinClass Itinerary = II_BC1CCZ;
431 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
432 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
434 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
435 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
436 dag OutOperandList = (outs);
437 string AsmString = instr_asm;
438 bit hasDelaySlot = 1;
440 InstrItinClass Itinerary = II_BC2CCZ;
443 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
444 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
446 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
447 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
449 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
450 RegisterOperand GPROpnd,
451 InstrItinClass itin = NoItinerary>
452 : MipsR6Arch<opstr> {
453 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
454 string AsmString = !strconcat(opstr, "\t$rt, $offset");
455 list<dag> Pattern = [];
456 bit hasDelaySlot = 0;
457 InstrItinClass Itinerary = itin;
460 bit isIndirectBranch = 1;
463 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
464 GPR32Opnd, II_JIALC> {
466 list<Register> Defs = [RA];
469 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
470 GPR32Opnd, II_JIALC> {
472 bit isTerminator = 1;
473 list<Register> Defs = [AT];
476 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
478 bit isIndirectBranch = 1;
479 bit hasDelaySlot = 1;
483 InstrItinClass Itinerary = II_JR_HB;
486 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
488 : MipsR6Arch<instr_asm> {
489 dag OutOperandList = (outs GPROpnd:$rd);
490 dag InOperandList = (ins GPROpnd:$rt);
491 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
492 list<dag> Pattern = [];
493 InstrItinClass Itinerary = itin;
496 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;
498 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
500 SDPatternOperator Op=null_frag>
501 : MipsR6Arch<instr_asm> {
502 dag OutOperandList = (outs GPROpnd:$rd);
503 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
504 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
505 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
506 InstrItinClass Itinerary = itin;
507 // This instruction doesn't trap division by zero itself. We must insert
508 // teq instructions as well.
509 bit usesCustomInserter = 1;
512 class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin>
513 : MipsR6Arch<instr_asm> {
514 dag OutOperandList = (outs GPR32Opnd:$rt);
515 dag InOperandList = (ins);
516 string AsmString = !strconcat(instr_asm, "\t$rt");
517 list<dag> Pattern = [];
518 InstrItinClass Itinerary = Itin;
519 bit hasUnModeledSideEffects = 1;
522 class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;
523 class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>;
525 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
526 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
527 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
528 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
530 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
531 list<Register> Defs = [RA];
534 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
535 list<Register> Defs = [RA];
538 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
539 list<Register> Defs = [RA];
542 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
543 list<Register> Defs = [RA];
546 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
547 list<Register> Defs = [RA];
550 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
551 list<Register> Defs = [RA];
554 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
556 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
557 dag OutOperandList = (outs GPROpnd:$rd);
558 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
559 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
560 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
561 InstrItinClass Itinerary = itin;
564 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
565 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
566 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
567 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
569 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
570 InstrItinClass itin> {
571 dag OutOperandList = (outs FGROpnd:$fd);
572 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
573 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
574 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
577 string Constraints = "$fd_in = $fd";
578 InstrItinClass Itinerary = itin;
581 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
582 MipsR6Arch<"sel.d"> {
583 // We must insert a SUBREG_TO_REG around $fd_in
584 bit usesCustomInserter = 1;
586 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,
589 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
590 : MipsR6Arch<instr_asm> {
591 dag OutOperandList = (outs GPROpnd:$rd);
592 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
593 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
594 list<dag> Pattern = [];
595 InstrItinClass Itinerary = II_SELCCZ;
598 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
599 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
601 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
602 InstrItinClass itin = NoItinerary> {
603 dag OutOperandList = (outs FGROpnd:$fd);
604 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
605 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
606 list<dag> Pattern = [];
607 string Constraints = "$fd_in = $fd";
608 InstrItinClass Itinerary = itin;
611 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;
612 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
613 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
614 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
616 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
617 InstrItinClass itin> {
618 dag OutOperandList = (outs FGROpnd:$fd);
619 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
620 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
621 list<dag> Pattern = [];
622 InstrItinClass Itinerary = itin;
625 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;
626 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;
627 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;
628 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;
630 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;
631 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;
632 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;
633 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;
635 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
636 InstrItinClass itin> {
637 dag OutOperandList = (outs FGROpnd:$fd);
638 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
639 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
640 list<dag> Pattern = [];
641 InstrItinClass Itinerary = itin;
644 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,
645 MipsR6Arch<"seleqz.s">;
646 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,
647 MipsR6Arch<"seleqz.d">;
648 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,
649 MipsR6Arch<"selnez.s">;
650 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,
651 MipsR6Arch<"selnez.d">;
653 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
654 InstrItinClass itin> {
655 dag OutOperandList = (outs FGROpnd:$fd);
656 dag InOperandList = (ins FGROpnd:$fs);
657 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
658 list<dag> Pattern = [];
659 InstrItinClass Itinerary = itin;
662 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;
663 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
664 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
665 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
667 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
668 RegisterOperand GPROpnd, InstrItinClass itin>
669 : MipsR6Arch<instr_asm> {
670 dag OutOperandList = (outs);
671 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
672 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
673 list<dag> Pattern = [];
674 string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
675 InstrItinClass Itinerary = itin;
678 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>;
679 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>;
681 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
682 InstrItinClass itin> {
683 dag OutOperandList = (outs COPOpnd:$rt);
684 dag InOperandList = (ins mem_simm11:$addr);
685 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
686 list<dag> Pattern = [];
688 string DecoderMethod = "DecodeFMemCop2R6";
689 InstrItinClass Itinerary = itin;
692 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;
693 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;
695 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
696 InstrItinClass itin> {
697 dag OutOperandList = (outs);
698 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
699 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
700 list<dag> Pattern = [];
702 string DecoderMethod = "DecodeFMemCop2R6";
703 InstrItinClass Itinerary = itin;
706 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;
707 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;
709 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
710 Operand ImmOpnd, InstrItinClass itin>
711 : MipsR6Arch<instr_asm> {
712 dag OutOperandList = (outs GPROpnd:$rd);
713 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
714 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
715 list<dag> Pattern = [];
716 InstrItinClass Itinerary = itin;
719 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
721 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
722 Operand MemOpnd, InstrItinClass itin>
723 : MipsR6Arch<instr_asm> {
724 dag OutOperandList = (outs GPROpnd:$rt);
725 dag InOperandList = (ins MemOpnd:$addr);
726 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
727 list<dag> Pattern = [];
729 InstrItinClass Itinerary = itin;
732 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
734 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
735 InstrItinClass itin> {
736 dag OutOperandList = (outs GPROpnd:$dst);
737 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
738 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
739 list<dag> Pattern = [];
741 string Constraints = "$rt = $dst";
742 InstrItinClass Itinerary = itin;
745 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
747 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
749 : MipsR6Arch<instr_asm> {
750 dag OutOperandList = (outs GPROpnd:$rd);
751 dag InOperandList = (ins GPROpnd:$rs);
752 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
753 InstrItinClass Itinerary = itin;
756 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
757 InstrItinClass itin> :
758 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
759 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
762 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
763 InstrItinClass itin> :
764 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
765 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
768 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
769 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
771 class SDBBP_R6_DESC {
772 dag OutOperandList = (outs);
773 dag InOperandList = (ins uimm20:$code_);
774 string AsmString = "sdbbp\t$code_";
775 list<dag> Pattern = [];
777 InstrItinClass Itinerary = II_SDBBP;
780 //===----------------------------------------------------------------------===//
782 // Instruction Definitions
784 //===----------------------------------------------------------------------===//
786 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
787 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
788 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
789 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
790 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
791 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
792 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
793 let AdditionalPredicates = [NotInMicroMips] in {
794 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
795 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
796 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
797 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
799 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
800 let AdditionalPredicates = [NotInMicroMips] in {
801 def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
802 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
803 def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
804 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
805 def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
806 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
807 def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
808 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
809 def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
811 def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
812 let AdditionalPredicates = [NotInMicroMips] in {
813 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
814 def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
815 def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
816 def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
817 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
818 def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
819 def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
820 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
821 def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
822 def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
823 def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
825 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
826 let AdditionalPredicates = [NotInMicroMips] in {
827 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
828 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
830 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
831 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
832 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>;
833 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>;
834 let AdditionalPredicates = [NotInMicroMips] in {
835 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
836 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
839 def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6;
840 def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6;
842 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
843 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
844 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
845 let AdditionalPredicates = [NotInMicroMips] in {
846 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
847 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
849 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
850 let AdditionalPredicates = [NotInMicroMips] in {
851 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
853 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
854 let AdditionalPredicates = [NotInMicroMips] in {
855 def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
856 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
857 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
858 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
859 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
860 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
861 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
862 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
863 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
864 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
865 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
867 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
868 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
870 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
871 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
873 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
874 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
875 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
876 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
878 def NAL; // BAL with rd=0
879 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
880 let AdditionalPredicates = [NotInMicroMips] in {
881 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
882 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
883 def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
884 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
885 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
886 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
887 def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
889 def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6,
891 def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
893 def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
895 def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
896 def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
897 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
898 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
901 //===----------------------------------------------------------------------===//
903 // Instruction Aliases
905 //===----------------------------------------------------------------------===//
907 def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
908 def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
910 let AdditionalPredicates = [NotInMicroMips] in {
911 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
912 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
915 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
917 let AdditionalPredicates = [NotInMicroMips] in {
918 def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
921 def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
922 GPR32Opnd:$rt)>, ISA_MIPS32R6;
923 def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
924 GPR32Opnd:$rt)>, ISA_MIPS32R6;
926 //===----------------------------------------------------------------------===//
928 // Patterns and Pseudo Instructions
930 //===----------------------------------------------------------------------===//
932 // comparisons supported via another comparison
933 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
934 def : MipsPat<(setone VT:$lhs, VT:$rhs),
935 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
936 def : MipsPat<(seto VT:$lhs, VT:$rhs),
937 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
938 def : MipsPat<(setune VT:$lhs, VT:$rhs),
939 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
940 def : MipsPat<(seteq VT:$lhs, VT:$rhs),
941 (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>;
942 def : MipsPat<(setgt VT:$lhs, VT:$rhs),
943 (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>;
944 def : MipsPat<(setge VT:$lhs, VT:$rhs),
945 (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>;
946 def : MipsPat<(setlt VT:$lhs, VT:$rhs),
947 (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>;
948 def : MipsPat<(setle VT:$lhs, VT:$rhs),
949 (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>;
950 def : MipsPat<(setne VT:$lhs, VT:$rhs),
951 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
954 let AdditionalPredicates = [NotInMicroMips] in {
955 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
956 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
960 multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
961 Instruction SLTiOp, Instruction SLTiuOp,
962 Instruction SELEQZOp, Instruction SELNEZOp,
963 SDPatternOperator imm_type, ValueType Opg> {
965 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f),
966 (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>;
967 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f),
968 (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>;
970 // reg, immZExt16[_64]
971 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
972 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
973 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
974 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
975 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
976 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
978 // reg, immSExt16Plus1
979 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
980 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))),
981 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>;
982 def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f),
983 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))),
984 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
986 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz),
987 (SELEQZOp RC:$t, RC:$cond)>;
988 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz),
989 (SELNEZOp RC:$t, RC:$cond)>;
990 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f),
991 (SELNEZOp RC:$f, RC:$cond)>;
992 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f),
993 (SELEQZOp RC:$f, RC:$cond)>;
996 let AdditionalPredicates = [NotInMicroMips] in {
997 defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
998 immZExt16, i32>, ISA_MIPS32R6;
1000 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1001 (OR (SELNEZ i32:$t, i32:$cond),
1002 (SELEQZ i32:$f, i32:$cond))>,
1004 def : MipsPat<(select i32:$cond, i32:$t, immz),
1005 (SELNEZ i32:$t, i32:$cond)>,
1007 def : MipsPat<(select i32:$cond, immz, i32:$f),
1008 (SELEQZ i32:$f, i32:$cond)>,