1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64r6 instructions.
12 //===----------------------------------------------------------------------===//
14 // Notes about removals/changes from MIPS32r6:
15 // Reencoded: dclo, dclz
17 //===----------------------------------------------------------------------===//
19 // Instruction Encodings
21 //===----------------------------------------------------------------------===//
23 class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
24 class DAUI_ENC : DAUI_FM;
25 class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
26 class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
27 class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
28 class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
29 class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
30 class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
31 class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
32 class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
33 class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
34 class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
35 class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;
36 class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
37 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
38 class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
39 class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
40 class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
41 class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
43 //===----------------------------------------------------------------------===//
45 // Instruction Descriptions
47 //===----------------------------------------------------------------------===//
49 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
50 dag OutOperandList = (outs GPROpnd:$rs);
51 dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
52 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
53 string Constraints = "$rs = $rt";
54 InstrItinClass Itinerary = itin;
57 class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
58 class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
59 class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
60 class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
61 class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
62 class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
63 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
64 class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
65 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
66 class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
67 class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
68 class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
69 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
70 class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
71 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
72 class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
73 class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
74 class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>;
75 class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
76 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
77 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
79 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
80 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
81 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
82 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
83 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
84 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
85 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
86 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
87 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
88 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
89 class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
90 class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
92 class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
93 GPR64Opnd, II_JIALC> {
95 list<Register> Defs = [RA];
98 class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
101 bit isTerminator = 1;
102 list<Register> Defs = [AT];
105 class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
106 class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
107 //===----------------------------------------------------------------------===//
109 // Instruction Definitions
111 //===----------------------------------------------------------------------===//
113 let AdditionalPredicates = [NotInMicroMips] in {
114 let DecoderMethod = "DecodeDAHIDATI" in {
115 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
116 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
118 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
119 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
120 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
121 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
122 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
123 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
124 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
125 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
126 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
127 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
128 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
129 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
130 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
131 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
132 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
134 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
135 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
136 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
137 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
138 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
140 let AdditionalPredicates = [NotInMicroMips],
141 DecoderNamespace = "Mips32r6_64r6_PTR64" in {
142 def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
143 def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
146 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
147 // Jump and Branch Instructions
148 def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
149 def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
151 def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
152 def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
153 def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
154 def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
155 def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
156 def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
157 def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
158 def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
159 def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
160 def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
162 let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
163 def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
164 def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
167 //===----------------------------------------------------------------------===//
169 // Instruction Aliases
171 //===----------------------------------------------------------------------===//
173 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
175 def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
177 def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
178 //===----------------------------------------------------------------------===//
180 // Patterns and Pseudo Instructions
182 //===----------------------------------------------------------------------===//
185 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
186 (OR64 (SELNEZ64 i64:$t, i64:$cond),
187 (SELEQZ64 i64:$f, i64:$cond))>,
189 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
190 (OR64 (SELEQZ64 i64:$t, i64:$cond),
191 (SELNEZ64 i64:$f, i64:$cond))>,
193 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
194 (OR64 (SELNEZ64 i64:$t, i64:$cond),
195 (SELEQZ64 i64:$f, i64:$cond))>,
197 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
198 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
199 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
201 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
202 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
203 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
206 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
207 (OR64 (SELEQZ64 i64:$t,
208 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
211 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
215 (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
216 (OR64 (SELEQZ64 i64:$t,
217 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
220 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
224 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
225 (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
226 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
227 (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
228 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
229 (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
230 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
231 (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
233 // i64 selects from an i32 comparison
234 // One complicating factor here is that bits 32-63 of an i32 are undefined.
235 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
236 // This would allow us to remove the sign-extensions here.
237 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
238 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
239 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
241 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
242 (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
243 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
245 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
246 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
247 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
249 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
250 (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
252 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
255 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
256 (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
258 (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
262 def : MipsPat<(select i32:$cond, i64:$t, immz),
263 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
265 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
266 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
268 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
269 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
271 def : MipsPat<(select i32:$cond, immz, i64:$f),
272 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
274 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
275 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
277 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
278 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,